JP2007299990A - Semiconductor device - Google Patents

Abstract

In a semiconductor device having a termination structure region and a transition region, the termination structure region and the transition region are further shortened. Do not set the total gate length longer than necessary, and install the gate electrode only in the area that is originally required.
In a transition region 2 between an active region 1 and a termination structure region 3, a trench buried region 5 in which an insulator 20 is buried in a trench groove 19 is provided. In the transition region 2, a P-type channel region 4 shallower than the trench groove 19 is provided on the active region 1 side of the trench buried region 5, and the source electrode 17 is electrically connected to the termination structure region 3 side of the trench buried region 5. Connected P-type bypass region 6 is provided.
[Selection] Figure 2

Description

  The present invention relates to a semiconductor device having a vertical insulated gate semiconductor element for high power.

  Conventionally, as a vertical insulated gate semiconductor element for high power, an insulated gate field effect transistor (hereinafter referred to as MOSFET) and an insulated gate bipolar transistor (hereinafter referred to as IGBT) having a metal-oxide-semiconductor structure are known. It is. These semiconductor elements can be formed alone for high power output applications or as a structure connected in parallel for other high voltage output applications.

  In a semiconductor device having such a vertical semiconductor element, the PN junction is terminated on the main surface on the side where the MOS gate structure is formed (hereinafter referred to as the upper side) outside the active region where the main current flows. It is necessary to provide a planar type termination structure region. When this termination structure region is not provided, the curvature portion of the PN junction exists outside the active region. In this curvature portion, the electric field is more likely to be concentrated than the planar PN junction in the active region. Therefore, the outside of the active region has a higher electric field than the active region, and the critical electric field strength is reached before the active region, resulting in a lower breakdown voltage.

  In general, in a vertical device having a planar termination structure region, the upper electrode is smaller than the opposite electrode among the electrodes in contact with the semiconductor layer for flowing a main current. Therefore, current tends to concentrate on the end of the upper electrode. As a countermeasure, it is known to provide a region (hereinafter referred to as a transition region) that transitions from the active region to the termination structure region.

  As examples of the planar termination structure, a floating guard ring structure, a field plate structure, a RESURF structure, or the like, or a termination structure that combines them is known. Further, a structure in which trench grooves are connected in a loop shape in a planar termination structure region so as to eliminate the end face of the trench groove and prevent a decrease in breakdown voltage due to electric field concentration on the end face of the trench groove is known (for example, (See Patent Document 1).

  Also, a structure is known in which a P-type diffusion region deeper than the trench groove is provided to prevent a breakdown voltage drop due to electric field concentration on the end face of the trench groove (see, for example, Patent Document 2). In Patent Document 2, by providing an inactive cell region surrounding the active cell region and a termination region surrounding the inactive cell region, formation of a parasitic NPN transistor is prevented, and destruction due to current concentration is prevented. Such a structure is also disclosed.

  In the active region, an electrode connected to the emitter electrode is formed in the trench groove through the dielectric film, thereby forming a space charge region in the semiconductor substrate region, and the channel region and the semiconductor substrate region. A structure in which electric field concentration in a space charge region in a semiconductor substrate region is relaxed by coupling with a space charge region generated at a junction is known (see, for example, Patent Document 3). This known example increases the impurity concentration of the semiconductor substrate to such an extent that the on-resistance can be reduced while maintaining a high breakdown voltage.

  Also, a power MOS element having an edge termination structure that completely surrounds the active region is known (see, for example, Patent Document 4). The edge termination structure includes a portion of a termination trench having a conductive material that is insulated by an insulator at the edge opposite the source region, drain region, and channel region. The conductive material of the edge termination structure is conductively connected to the source region and the drain region through the connection hole, the upper surface metallization, and the connection hole.

  A first conductivity type semiconductor substrate; a second conductivity type epitaxial layer provided on the semiconductor substrate; and a first conductivity type first region extending from the upper surface of the epitaxial layer into the epitaxial layer; A second region extending from the upper surface of the epitaxial layer into the epitaxial layer so as to surround the first region and away from the first region; and from the upper surface of the epitaxial layer through the second region and the epitaxial layer Inclined sidewalls extending into the substrate, respective PN junctions formed between the first region and the second region and the epitaxial layer, and provided in the inclined sidewalls, And a thin implanted layer of a first conductivity type impurity that constitutes a low resistance path that electrically connects the region to the substrate, and controls the breakdown voltage characteristics between the first region and the second region Provided with means to And are semiconductor devices are known. The means for controlling the breakdown voltage characteristics includes a first junction termination extending region extending in the lateral direction from the first region toward the second region, and a first junction termination extending region from the second region. And a second junction terminal extension region extending in the lateral direction toward the surface (see, for example, Patent Document 5).

Further, a structure in which a trench is formed between a cell area where an N ⁺ emitter region is disposed and a non-cell area which is a region other than the cell area and a P base layer is separated is known (for example, Patent Documents). 6). A gate electrode is embedded in the trench. This known example can prevent holes from flowing from the non-cell area to the cell area, and can avoid the occurrence of a latch-up phenomenon.

JP 2001-168329 A (FIGS. 3 and 4) Japanese Patent Laying-Open No. 2005-19734 (FIGS. 9, 10, and 14) JP 2001-85688 A (FIGS. 9 and 18) Japanese translation of PCT publication No. 2003-515915 (see D in FIG. 4) JP-A-2-22869 JP 2001-168324 A (FIG. 3, paragraphs 0029 to 0032)

  However, in the case where the above-described inactive cell region is provided, there is a problem in that the on-resistance per unit area is increased because the inactive cell region is a region where the MOSFET does not operate. In addition, since the gate electrode is embedded in the trench groove sandwiched between the termination structure region and the inactive cell region via an insulating film, the total gate length becomes long and the capacity increases. There is a problem that the reliability of the system is impaired.

  In particular, a corner portion of the semiconductor device has a curved portion in a trench groove in which a gate electrode is embedded. The curvature portion and the region where the other trench grooves are formed in a straight line have a problem that the reliability of the gate is lowered because the growth rate of the insulating film is different. In addition, since it is necessary to provide a certain space or more in order to separate the gate electrode and the source electrode, there is a problem that an operation region of the transistor becomes narrow.

  The present invention provides a semiconductor device having a termination structure region and a transition region in order to eliminate the above-described problems caused by the prior art, and which can further shorten the termination structure region and the transition region. With the goal. The present invention also provides a semiconductor device having a termination structure region and a transition region, in which a gate electrode can be installed only in a region that is originally necessary without making the total gate length longer than necessary. The purpose is to do.

  In order to solve the above-described problems and achieve the object, a semiconductor device according to a first aspect of the present invention is a semiconductor device having a transition region between an active region and a termination structure region surrounding the active region. A drift region of a first conductivity type having a surface and a second main surface, a channel region of a second conductivity type selectively provided along the first main surface, and selectively provided in the channel region A first semiconductor region of a first conductivity type, a first electrode connected to both the first semiconductor region and the channel region, and provided along the channel region between the first semiconductor region and the drift region An active region having a gate insulating film and a gate electrode provided along the gate insulating film; an insulator embedded in a trench groove reaching deeper than the channel region from the first main surface; and the trench A transition region having a second conductivity type bypass region connected to the first electrode and connected to the first electrode, and a first conductivity type provided along the second main surface of the drift region A second semiconductor region, a second electrode connected to the second semiconductor region, and a cut surface extending from the first main surface to the second main surface along the outer peripheral edge of the termination structure region. It is characterized by.

  According to a second aspect of the present invention, there is provided a semiconductor device having a first main surface and a second main surface in a semiconductor device having a transition region between an active region and a termination structure region surrounding the active region. A drift region of a type, a channel region of a second conductivity type selectively provided along the first main surface, a first semiconductor region of a first conductivity type selectively provided in the channel region, A first electrode connected to both the first semiconductor region and the channel region, a gate insulating film provided along the channel region between the first semiconductor region and the drift region, and along the gate insulating film An active region having a gate electrode provided, an insulator embedded in a trench groove reaching deeper than the channel region from the first main surface, and the termination structure region side of the trench groove, Or A transition region having a second conductivity type bypass region connected to the first electrode; a second conductivity type second semiconductor region provided along a second main surface of the drift region; and the second semiconductor A second electrode connected to the region; and a cut surface extending from the first main surface to the second main surface along an outer peripheral edge of the termination structure region.

  According to a third aspect of the present invention, there is provided a semiconductor device having a transition region between an active region and a termination structure region surrounding the active region, the first conductive surface having a first main surface and a second main surface. A drift region of a type, a channel region of a second conductivity type selectively provided along the first main surface, a first semiconductor region of a first conductivity type selectively provided in the channel region, A first electrode connected to both the first semiconductor region and the channel region; a first trench groove adjacent to the first semiconductor region and penetrating from the first main surface through the channel region to the drift region; An active region having a gate insulating film provided along an inner peripheral surface, a gate electrode embedded in the first trench groove through the gate insulating film, and deeper than the channel region from the first main surface 2nd trench reaching to An insulator embedded therein, a transition region provided on the termination structure region side of the second trench groove and having a second conductivity type bypass region connected to the first electrode, and a drift region A first conductive type second semiconductor region provided along the second main surface, a second electrode connected to the second semiconductor region, and an outer peripheral edge of the termination structure region from the first main surface. And a cut surface that reaches the second main surface.

  According to a fourth aspect of the present invention, there is provided a semiconductor device having a transition region between an active region and a termination structure region surrounding the active region, the first conductive surface having a first main surface and a second main surface. A drift region of a type, a channel region of a second conductivity type selectively provided along the first main surface, a first semiconductor region of a first conductivity type selectively provided in the channel region, A first electrode connected to both the first semiconductor region and the channel region; a first trench groove adjacent to the first semiconductor region and penetrating from the first main surface through the channel region to the drift region; An active region having a gate insulating film provided along an inner peripheral surface, a gate electrode embedded in the first trench groove through the gate insulating film, and deeper than the channel region from the first main surface 2nd trench reaching to An insulator embedded therein, a transition region provided on the terminal structure region side of the second trench groove and having a second conductivity type bypass region connected to the first electrode, and a drift region A second semiconductor region of a second conductivity type provided along the second main surface, a second electrode connected to the second semiconductor region, and an outer peripheral edge of the termination structure region from the first main surface And a cut surface that reaches the second main surface.

  According to a fifth aspect of the present invention, there is provided a semiconductor device having a transition region between an active region and a termination structure region surrounding the active region, the first conductive having a first main surface and a second main surface. A drift region of a type, a channel region of a second conductivity type selectively provided along the first main surface, a first semiconductor region of a first conductivity type selectively provided in the channel region, A first electrode connected to both the first semiconductor region and the channel region, a gate insulating film provided along the channel region between the first semiconductor region and the drift region, and along the gate insulating film An active region having a gate electrode, an insulating film provided along an inner peripheral surface of the trench groove extending deeper than the channel region from the first main surface, and the trench groove via the insulating film Embedded in A transition region provided on the terminal structure region side of the electrode and the trench groove and having a second conductivity type bypass region connected to the first electrode, and provided along the second main surface of the drift region A second semiconductor region of the first conductivity type formed, a second electrode connected to the second semiconductor region, and a cut extending from the first main surface to the second main surface along the outer peripheral edge of the termination structure region And a surface.

  According to a sixth aspect of the present invention, there is provided a semiconductor device having a first main surface and a second main surface in a semiconductor device having a transition region between an active region and a termination structure region surrounding the active region. A drift region of a type, a channel region of a second conductivity type selectively provided along the first main surface, a first semiconductor region of a first conductivity type selectively provided in the channel region, A first electrode connected to both the first semiconductor region and the channel region, a gate insulating film provided along the channel region between the first semiconductor region and the drift region, and along the gate insulating film An active region having a gate electrode, an insulating film provided along an inner peripheral surface of the trench groove extending deeper than the channel region from the first main surface, and the trench groove via the insulating film Embedded in A transition region provided on the terminal structure region side of the electrode and the trench groove and having a second conductivity type bypass region connected to the first electrode, and provided along the second main surface of the drift region A second semiconductor region of the second conductivity type formed, a second electrode connected to the second semiconductor region, and a cut extending from the first main surface to the second main surface along the outer peripheral edge of the termination structure region And a surface.

  According to a seventh aspect of the present invention, there is provided a semiconductor device having a transition region between an active region and a termination structure region surrounding the active region, the first conductive having a first main surface and a second main surface. A drift region of a type, a channel region of a second conductivity type selectively provided along the first main surface, a first semiconductor region of a first conductivity type selectively provided in the channel region, A first electrode connected to both the first semiconductor region and the channel region; a first trench groove adjacent to the first semiconductor region and penetrating from the first main surface through the channel region to the drift region; An active region having a gate insulating film provided along an inner peripheral surface, a gate electrode embedded in the first trench groove through the gate insulating film, and deeper than the channel region from the first main surface 2nd trench reaching An insulating film provided along an inner peripheral surface of the first electrode, an electrode embedded in the second trench groove through the insulating film, and provided on the terminal structure region side of the second trench groove, and the first A transition region having a second conductivity type bypass region connected to one electrode, a first conductivity type second semiconductor region provided along a second main surface of the drift region, and the second semiconductor region; It is characterized by comprising: a connected second electrode; and a cut surface extending from the first main surface to the second main surface along the outer peripheral edge of the termination structure region.

  According to another aspect of the present invention, there is provided a semiconductor device having a transition region between an active region and a termination structure region surrounding the active region, the first conductive surface having a first main surface and a second main surface. A drift region of a type, a channel region of a second conductivity type selectively provided along the first main surface, a first semiconductor region of a first conductivity type selectively provided in the channel region, A first electrode connected to both the first semiconductor region and the channel region; a first trench groove adjacent to the first semiconductor region and penetrating from the first main surface through the channel region to the drift region; An active region having a gate insulating film provided along an inner peripheral surface, a gate electrode embedded in the first trench groove through the gate insulating film, and deeper than the channel region from the first main surface 2nd trench reaching to An insulating film provided along an inner peripheral surface of the first electrode, an electrode embedded in the second trench groove through the insulating film, and provided on the terminal structure region side of the second trench groove, and the first A transition region having a second conductivity type bypass region connected to one electrode, a second conductivity type second semiconductor region provided along a second main surface of the drift region, and the second semiconductor region; It is characterized by comprising: a connected second electrode; and a cut surface extending from the first main surface to the second main surface along the outer peripheral edge of the termination structure region.

  According to a ninth aspect of the present invention, in the semiconductor device according to the fifth or sixth aspect, an electrode in the trench groove is connected to the first electrode. According to a tenth aspect of the present invention, in the semiconductor device according to the ninth aspect, the electrodes in the trench groove are connected to the first electrode only at four corners of the semiconductor device. .

  According to an eleventh aspect of the present invention, in the semiconductor device according to the seventh or eighth aspect, an electrode in the second trench groove is connected to the first electrode. According to a twelfth aspect of the present invention, in the semiconductor device according to the eleventh aspect, the electrode in the second trench groove is connected to the first electrode only at four corners of the semiconductor device. And

  A semiconductor device according to a thirteenth aspect of the present invention is the semiconductor device according to the first or second aspect, wherein the insulator in the trench groove is silicon oxide. According to a fourteenth aspect of the present invention, in the semiconductor device according to the third or fourth aspect, the insulator in the second trench groove is silicon oxide.

  According to a fifteenth aspect of the present invention, in the semiconductor device according to the third, fourth, seventh, or eighth aspect, the depth of the first trench groove and the depth of the second trench groove are the same. Features. A semiconductor device according to a sixteenth aspect of the present invention is the semiconductor device according to any one of the first to fifteenth aspects, wherein the impurity profile of the bypass region and the impurity profile of the channel region are the same. To do.

  According to a seventeenth aspect of the present invention, in the semiconductor device according to any one of the first to fifteenth aspects, a second conductivity type body region is selectively provided in the channel region. The impurity profile of the bypass region and the impurity profile of the body region are the same. According to an eighteenth aspect of the present invention, in the semiconductor device according to any one of the first to seventeenth aspects, the MOS gate structure of the active region is formed linearly.

  According to the present invention, the trench groove provided in the transition region prevents the minority carriers in the termination structure region from flowing into the active region, and pulls out the minority carriers from the bypass region, thereby turning off in the vicinity of the termination structure region. And avalanche destruction can be avoided. That is, by providing the trench groove in the transition region with a function as a current barrier and a voltage barrier, dynamic tolerance can be improved.

  Further, by filling the inside of the trench groove in the transition region with an oxide film, or by embedding an electrode through the oxide film and fixing the potential of the electrode to a potential different from the gate electrode, It is possible to prevent the increase and shorten or eliminate a region necessary for insulation from the gate potential. Therefore, both high gate reliability and a short transition region can be realized simultaneously.

  Furthermore, when the trench groove in the transition region is filled with silicon oxide, a conventional semiconductor manufacturing process can be used. In addition, by making the trench groove depth of the transition region the same as the trench groove depth of the active region, or by making the impurity profile of the bypass region the same as the impurity profile of the channel region or body region, the transition is performed without adding a process. Since the structure of the region can be manufactured, the semiconductor manufacturing process can be simplified.

  In addition, by forming the distance from the interface between the bypass region and the trench groove in the transition region to the portion of the bypass region farthest from the interface, the distance from the channel depth of the active region is longer, thereby causing avalanche breakdown. This is advantageous because the decrease in pressure resistance is reduced. Alternatively, by forming the distance so as to be wider than the interval between the trench grooves in the active region, it is advantageous in that a decrease in breakdown voltage due to avalanche breakdown is reduced.

  Incidentally, the semiconductor device disclosed in Patent Document 3 increases the impurity concentration of the semiconductor substrate to such an extent that the on-resistance can be reduced. Therefore, it is necessary to form a trench groove over almost the entire surface of the active region, and to form an electrode in the trench groove via a dielectric film. In contrast, the present invention forms a trench groove in the transition region between the active region and the termination structure region, and fills the trench groove with an insulator, or forms an electrode in the trench groove via a dielectric film. Therefore, the mechanism and structure are different from those of the semiconductor device disclosed in Patent Document 3.

  According to the semiconductor device of the present invention, the termination structure region and the transition region can be further shortened. In addition, the gate electrode can be provided only in a necessary region without making the total gate length longer than necessary.

  Hereinafter, preferred embodiments of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings. Note that, in the following description of the embodiments and the accompanying drawings, the same reference numerals are given to the same components, and duplicate descriptions are omitted.

Embodiment 1 FIG.
An example in which the present invention is applied to a 600 V planar gate MOSFET will be described. FIG. 1 is a diagram showing a planar layout on the first main surface side of the semiconductor device according to the first embodiment, in which an electrode, an insulating film, and the like formed on the first main surface are omitted. As shown in FIG. 1, the active region 1 is disposed in the central portion of the semiconductor device. The transition region 2 is arranged outside the active region 1 so as to surround the active region 1. The termination structure region 3 is disposed outside the transition region 2 so as to surround the transition region 2.

  In the transition region 2, a channel region 4, a trench buried region 5, and a bypass region 6 are arranged so as to go around the semiconductor chip in this order from the active region 1 to the termination structure region 3. At the corners of the four corners of the semiconductor chip, the trench buried region 5 is formed to be bent at a right angle with a curvature of about 200 μm. The outer peripheral edge of the termination structure region 3 is cut surfaces 7a and 7b extending from the first main surface to the second main surface of the semiconductor device. Although not shown, the termination structure region 3 is formed with a termination structure such as a field limiting ring.

  Although not shown, the active region 1 is formed with a source region, a channel region, a body region, and the like constituting a MOS gate structure. Although not particularly limited, for example, in the active region 1, a plurality of linearly formed MOS gate structures are arranged in parallel in a stripe shape. Here, it is assumed that each MOS gate structure extends in a direction perpendicular to the alternate long and short dash line A-A ′ in FIG. 1 (a direction parallel to the alternate long and short dash line B-B ′). A gate pad 8 is provided in the active region 1. For example, the gate pad 8 is made of metal.

Next, a cross-sectional configuration of the semiconductor device of First Embodiment will be described. FIGS. 2 and 3 are cross-sectional views taken along section lines AA ′ and BB ′ in FIG. 1, respectively. The configuration of the active region 1 is as follows. For example, the concentration and thickness of the N-type drift region 11 are about 2.5 × 10 ¹⁴ cm ⁻³ and about 50 μm, respectively. The P-type channel region 12 is selectively provided along the first main surface of the drift region 11. For example, the depth of the channel region 12 is about 3 μm. The source region 13 which is an N-type first semiconductor region is selectively provided in the channel region 12.

  The gate insulating film 14 is provided on the first main surface along the region of the channel region 12 between the source region 13 and the drift region 11. For example, the gate insulating film 14 is made of silicon oxide. The gate electrode 15 is provided along the gate insulating film 14. For example, the gate electrode 15 is made of highly doped polysilicon.

  A P-type body region 16 is selectively provided in the channel region 12. The source electrode 17 as the first electrode is connected to the source region 13 and is electrically connected to the channel region 12 through the body region 16. For example, the source electrode 17 is made of metal. The source electrode 17 and the gate electrode 15 are insulated by an interlayer insulating film 18. The above-described MOS gate structure is formed by a general DMOS (Double-Difused-MOS) process.

  The configuration of the transition region 2 is as follows. The conductivity type of channel region 4 and bypass region 6 is P-type. The channel region 4 and the bypass region 6 are selectively provided along the first main surface of the drift region 11. Although the width of the channel region 4 can be designed freely, it is appropriate that it is about ½ cell in a planar gate type device. The channel region 4 and the impurity profile may be the same as the channel region 12 in the active region 1 and the channel region 4 and 12 may be formed by the same process.

  The width of the bypass region 6 is equal to or longer than the depth of the trench groove 19. It is preferable that the width of the bypass region 6 is longer than the channel depth of the active region 1, since a decrease in breakdown voltage due to avalanche breakdown is reduced. The depth of the bypass region 6 is shallower than the depth of the trench groove 19. The shallower the bypass region 6 is, the greater the effect of improving the dynamic resistance, which will be described later, is preferable.

Alternatively, the depth and impurity profile of the bypass region 6 may be the same as the depth and impurity profile of the channel region 12 of the active region 1. In this case, since the bypass region 6 can be formed by the same process as the channel region 12 of the active region 1, it is not necessary to add a step of forming the bypass region 6, which is preferable. For example, by implanting boron ions at a dose of about 2 × 10 ^{13 to} 2 × 10 ¹⁴ cm ⁻² and then performing heat treatment at 1100 ° C. for about 200 minutes, the channel region 12 and the bypass region of the active region 1 6 can be formed simultaneously.

  Alternatively, the depth and impurity profile of the bypass region 6 are made the same as the depth and impurity profile of the body region 16, that is, the body region 22 functions as the bypass region 6, and the body region 22 is processed in the same process as the body region 16. You may make it form. The trench buried region 5 is configured by filling the trench groove 19 with an insulator 20. Trench groove 19 is formed so as to reach deeper than channel region 4 of transition region 2 from the first main surface of drift region 11. For example, the width and depth of the trench groove 19 are about 1 μm and about 5 μm, respectively. For example, the insulator 20 is silicon oxide such as HTO (High Temperature Oxide).

  A P-type body region 21 is selectively provided in the channel region 4 of the transition region 2. The bypass region 6 is selectively provided with a P-type body region 22. Source electrode 17 is electrically connected to channel region 4 and bypass region 6 of transition region 2 through body regions 21 and 22. An interlayer insulating film 23 is provided between the insulator 20 and the source electrode 17 in the trench buried region 5.

  The configuration of the termination structure region 3 is as follows. The P-type field limiting ring 24 is selectively provided along the first main surface of the drift region 11 so as to go around the semiconductor chip. Field oxide films 25 and 26 are provided between the field limiting ring 24 and the transition region 2 and between the field limiting ring 24 and the cut surfaces 7a and 7b. Interlayer insulating films 27 and 28 are provided on the field oxide films 25 and 26.

  The field plate 29 is electrically connected to the field limiting ring 24 through a P-type body region 30. For example, the field plate 29 is made of metal. For example, the interlayer insulating films 18, 23, 27, and 28 are made of BPSG (borophosphosilicate glass). The termination structure described above is formed by a general DMOS process.

The drain region 31, which is an N-type second semiconductor region, is provided along the second main surface of the drift region 11 across the active region 1, the transition region 2, and the termination structure region 3. For example, the concentration and thickness of the drain region 31 are about 2.0 × 10 ¹⁸ cm ⁻³ and 300 μm, respectively. The drain electrode 32 as the second electrode is electrically connected to the drain region 31. For example, the drain electrode 32 is made of metal.

  According to the first embodiment, since no MOS gate electrode is formed in the trench groove 19, no current path is formed in the on state. Further, since the trench groove 19 functions as a current barrier, the current flow in the lateral direction can be restricted. Therefore, it is possible to suppress the current from spreading from the active region 1 to the termination structure region 3. Further, at the time of turn-off, since the trench groove 19 functions as a potential barrier, the potential at the bottom of the trench groove 19 rising due to the current flowing into the bypass region 6 is changed to the potential at the bottom of the trench groove 19 generated by the current flowing into the channel region 4. Until the rise is exceeded, current can be prevented from flowing into the channel region 4 on the active region 1 side. Therefore, dynamic (switching) tolerance can be improved.

  Here, as disclosed in Patent Document 2, when a diffusion layer deeper than the trench groove is formed, the function of the trench groove as a potential barrier is lost. Therefore, in that case, since the width of the channel region 4 on the active region 1 side needs to be widened, the width of the transition region 2 is widened, and the area of the active region 1 is correspondingly reduced. There is an inconvenience of inviting a rise.

  Further, according to the first embodiment, since the gate electrode is not embedded in the trench groove 19, when the gate electrode is embedded in the trench groove 19, the embedded gate electrode and source electrode Since the region necessary for the insulation is unnecessary, the width of the transition region 2 can be reduced. Further, since it is not necessary to increase the MOS gate area, the reliability of the MOS gate is not impaired.

Embodiment 2. FIG.
4 and 5 are diagrams showing a configuration of the semiconductor device of the second embodiment, and are diagrams showing configurations in cross sections corresponding to the cutting lines AA ′ and BB ′ in FIG. 1, respectively. The planar layout on the first main surface side of the semiconductor device of the second embodiment is the same as the layout shown in FIG. As shown in FIGS. 4 and 5, the second embodiment is different from the first embodiment in that the insulating film 41 is provided along the inner peripheral surface of the trench groove 19 in the transition region 2. Is filled with the electrode 42 through the insulating film 41, and the electrode 42 is connected to the source electrode 17. Other configurations are the same as those of the first embodiment.

  The electrode 42 in the trench groove 19 is insulated from the channel region 4 and the bypass region 6 in the transition region 2 by the insulating film 41 in the trench groove 19. For example, the insulating film 41 in the trench groove 19 is made of silicon oxide having a thickness of 100 nm. For example, the electrode 42 in the trench 19 is made of highly doped polysilicon. It is preferable to form the insulating film 41 and the electrode 42 at the same time as the gate insulating film 14 and the gate electrode 15 in the active region 1 because it is not necessary to add a step of filling the trench groove 19.

Embodiment 3 FIG.
The third embodiment is a modification of the second embodiment. 6 is a diagram showing a configuration of the semiconductor device of the third embodiment, and is a diagram showing a configuration in a cross section corresponding to a cutting line AA ′ of FIG. The planar layout on the first main surface side of the semiconductor device of the third embodiment is the same as the layout shown in FIG. As shown in FIG. 6, the third embodiment differs from the second embodiment in that the channel region 4 and the bypass region 6 in the transition region 2 are shallower than the trench groove 19, but the channel region 12 in the active region 1. Is also deeply formed.

  In the third embodiment, the electrode 42 in the trench groove 19 is insulated from the channel region 4 in the transition region 2 by the insulating film 41 and the interlayer insulating film 43 in the trench groove 19, and in the trench groove 19. The insulating film 41 is insulated from the bypass region 6. For example, the interlayer insulating film 43 is made of BPSG and is formed simultaneously with the other interlayer insulating films 18, 27 and 28. Other configurations are the same as those of the second embodiment.

Embodiment 4 FIG.
The fourth embodiment is a modification of the second embodiment. FIG. 7 is a diagram showing a configuration of the semiconductor device according to the fourth embodiment, and is a diagram showing a configuration in a cross section corresponding to the cutting line AA ′ of FIG. The planar layout on the first main surface side of the semiconductor device of the fourth embodiment is the same as the layout shown in FIG. As shown in FIG. 7, the fourth embodiment differs from the second embodiment in that in the transition region 2, the body region 21 in the channel region 4 and the body region 22 in the bypass region 6 extend to the trench groove 19. That is, the source electrode 17 is connected to the electrode 42 in the trench groove 19 in the trench groove 19. Other configurations are the same as those of the second embodiment.

Embodiment 5 FIG.
The fifth embodiment is a modification of the second embodiment. FIG. 8 is a diagram showing a planar layout on the first main surface side of the semiconductor device of the fifth embodiment, in which an electrode, an insulating film, etc. formed on the first main surface are omitted. FIG. 9 is a diagram showing a cross-sectional configuration in the side region (region excluding the four corners) of the semiconductor device of the fifth embodiment, and is a diagram showing a cross-sectional configuration along the cutting line CC ′ in FIG. The cutting line CC ′ is assumed to be a direction perpendicular to the direction in which, for example, each linear MOS gate structure formed in the active region 1 extends.

  As shown in FIGS. 8 and 9, the fifth embodiment is different from the second embodiment in that, in the transition region 2, the electrode 42 in the trench groove 19 is connected only at the corners of the four corners of the semiconductor chip. It is connected to the source electrode 17 (FIG. 9) by (FIG. 8). The connection structure of the electrode 42 and the source electrode 17 may be any of the cross-sectional structures of the above-described second to fourth embodiments. In the side region of the semiconductor chip, the electrode 42 in the trench groove 19 is insulated from the source electrode 17 by the interlayer insulating film 45. For example, the interlayer insulating film 45 is made of BPSG and is formed simultaneously with the other interlayer insulating films 18, 27 and 28. Other configurations are the same as those of the second embodiment.

Embodiment 6 FIG.
The sixth embodiment is a modification of the second embodiment. FIG. 10 is a diagram illustrating a main part of a planar layout on the first main surface side of the semiconductor device of the sixth embodiment, and is a diagram in which an electrode, an insulating film, and the like formed on the first main surface are omitted. . 11 and FIG. 12 are diagrams showing the configurations of cross sections taken along section lines DD ′ and EE ′ of FIG. 10, respectively. These cutting lines DD ′ and EE ′ correspond to the cutting lines AA ′ and BB ′ in FIG. 1, respectively. As shown in FIGS. 10 to 12, the sixth embodiment is different from the second embodiment in that the MOS gate structure in the active region 1 is a trench gate structure including a trench groove 51, a gate insulating film 52 and a gate electrode 53. 54.

  The trench 51 is adjacent to the source region 13 and reaches the drift region 11 through the channel region 12 from the first main surface of the semiconductor device. The gate insulating film 52 is provided along the inner peripheral surface of the trench groove 51. The gate electrode 53 is embedded in the trench groove 51 through the gate insulating film 52. The gate electrode 53 is insulated from the source electrode 17 by the interlayer insulating film 55. For example, the interlayer insulating film 55 is made of BPSG and is formed simultaneously with the other interlayer insulating films 27 and 28. Other configurations are the same as those of the second embodiment.

  The width of the channel region 4 in the transition region 2 can be designed freely. However, in the case of a trench gate type device as in the sixth embodiment, it may be about the depth of the trench groove 51 of the trench gate structure 54. . For example, if the trench groove 51 in the active region 1 and the trench groove 19 in the transition region 2 have the same depth, and the gate insulating film 52 and the gate electrode 53 are made of silicon oxide and highly doped polysilicon, respectively, The trench gate structure 54 in 1, the trench groove 19 in the transition region 2, the insulating film 41 in the trench groove 19 and the electrode 42 can be formed by the same process. This is preferable because the structure of the transition region 2 can be formed without adding a new process.

  According to the second to sixth embodiments, since the trench groove 19 and the bypass region 6 are provided, the dynamic (switching) tolerance can be improved as in the first embodiment. Further, since the electrode 42 in the trench groove 19 is connected to the source electrode 17, when the gate electrode is buried in the trench groove 19, the insulation between the buried gate electrode and the source electrode is prevented. Therefore, since the necessary area is not necessary, the width of the transition area 2 can be reduced. Furthermore, since it is not necessary to increase the MOS gate area, the reliability of the MOS gate is not impaired.

  In the fifth embodiment, since the electrode 42 embedded in the trench 19 is provided for the purpose of fixing the potential to the source potential, unlike the gate electrode, almost no current needs to flow. Therefore, highly doped polysilicon having a higher resistance than the electrode material can be used as the electrode 42. Then, by making the connection structure between the electrode 42 and the source electrode 17 as in the fifth embodiment, the width of the transition region 2 can be further reduced. Therefore, the fifth embodiment is preferable because the area of the active region 1 can be further increased.

  As described above, the present invention is not limited to the above-described embodiment, and various modifications can be made. For example, in the embodiment, the configuration having the combination of the bypass region 6 and the body region 22 has been mainly described. However, in any embodiment, only the bypass region 6 or only the body region 22 is provided instead of this combination. It is good also as a structure. Moreover, the dimension, density | concentration, etc. which were described in embodiment are examples, and this invention is not limited to those values. The active region 1 and the termination structure region 3 can be freely configured. Furthermore, each structural example mentioned above can be combined suitably. For example, in the first to fifth embodiments, the MOS gate structure of the active region 1 may be a trench gate structure as in the sixth embodiment. Moreover, although each example mentioned above is an example of MOSFET, this invention is applicable also to IGBT. In the case of IGBT, the conductivity type of the second semiconductor region is P-type. Further, in each of the above-described examples, the first conductivity type is N-type and the second conductivity type is P-type. However, the present invention may be configured such that the first conductivity type is P-type and the second conductivity type is N-type. The same holds true.

  As described above, the semiconductor device according to the present invention is useful for a semiconductor device having an insulated gate structure, and is particularly suitable for a power MOSFET and an IGBT.

3 is a diagram showing a planar layout on the first main surface side in the first embodiment. FIG. It is a figure which shows the structure of the cross section in sectional line A-A 'of FIG. It is a figure which shows the structure of the cross section in the cutting line B-B 'of FIG. FIG. 6 is a diagram showing a cross-sectional configuration corresponding to a cutting line A-A ′ in FIG. 1 of Embodiment 2. FIG. 6 is a diagram illustrating a cross-sectional configuration corresponding to a cutting line B-B ′ in FIG. 1 according to the second embodiment. FIG. 6 is a diagram showing a cross-sectional configuration corresponding to a cutting line A-A ′ of FIG. FIG. 10 is a diagram illustrating a cross-sectional configuration corresponding to a cutting line A-A ′ of FIG. FIG. 20 is a diagram showing a planar layout on the first main surface side in the fifth embodiment. It is a figure which shows the structure of the cross section in the cutting line C-C 'of FIG. FIG. 25 is a diagram showing a main part of a planar layout on the first main surface side in the sixth embodiment. It is a figure which shows the structure of the cross section corresponding to the cutting line D-D 'of FIG. It is a figure which shows the structure of the cross section in the cutting line E-E 'of FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Active region 2 Transition region 3 Termination structure region 6 Bypass region 7a, 7b Cut surface 11 Drift region 4, 12 Channel region 13 First semiconductor region 14, 52 Gate insulating film 15, 53 Gate electrode 16, 21 Body region 17 First Electrode 19, 51 Trench groove 20 Insulator 31 Second semiconductor region 32 Second electrode 41 Insulating film 42 Electrode

Claims (18)

In a semiconductor device having a transition region between an active region and a termination structure region surrounding the active region,
A first conductivity type drift region having a first main surface and a second main surface;
A second conductivity type channel region selectively provided along the first main surface; a first conductivity type first semiconductor region selectively provided in the channel region; the first semiconductor region; A first electrode connected to both of the channel regions; a gate insulating film provided along the channel region between the first semiconductor region and the drift region; and a gate electrode provided along the gate insulating film An active region having
An insulator embedded in a trench groove reaching deeper than the channel region from the first main surface, and a second conductivity provided on the terminal structure region side of the trench groove and connected to the first electrode A transition region having a type bypass region;
A second semiconductor region of the first conductivity type provided along the second main surface of the drift region;
A second electrode connected to the second semiconductor region;
A cutting surface extending from the first main surface to the second main surface along the outer peripheral edge of the termination structure region;
A semiconductor device comprising: In a semiconductor device having a transition region between an active region and a termination structure region surrounding the active region,
A first conductivity type drift region having a first main surface and a second main surface;
A second conductivity type channel region selectively provided along the first main surface; a first conductivity type first semiconductor region selectively provided in the channel region; the first semiconductor region; A first electrode connected to both of the channel regions; a gate insulating film provided along the channel region between the first semiconductor region and the drift region; and a gate electrode provided along the gate insulating film An active region having
An insulator embedded in a trench groove reaching deeper than the channel region from the first main surface, and a second conductivity provided on the terminal structure region side of the trench groove and connected to the first electrode A transition region having a type bypass region;
A second semiconductor region of a second conductivity type provided along the second main surface of the drift region;
A second electrode connected to the second semiconductor region;
A cutting surface extending from the first main surface to the second main surface along the outer peripheral edge of the termination structure region;
A semiconductor device comprising: In a semiconductor device having a transition region between an active region and a termination structure region surrounding the active region,
A first conductivity type drift region having a first main surface and a second main surface;
A second conductivity type channel region selectively provided along the first main surface; a first conductivity type first semiconductor region selectively provided in the channel region; the first semiconductor region; A first electrode connected to both of the channel regions, along the inner peripheral surface of the first trench groove that reaches the drift region through the channel region from the first main surface adjacent to the first semiconductor region An active region having a gate insulating film provided, a gate electrode embedded in the first trench groove through the gate insulating film;
An insulator embedded in a second trench groove extending deeper than the channel region from the first main surface, and provided on the terminal structure region side of the second trench groove and connected to the first electrode A transition region having a second conductivity type bypass region;
A second semiconductor region of the first conductivity type provided along the second main surface of the drift region;
A second electrode connected to the second semiconductor region;
A cutting surface extending from the first main surface to the second main surface along the outer peripheral edge of the termination structure region;
A semiconductor device comprising: In a semiconductor device having a transition region between an active region and a termination structure region surrounding the active region,
A first conductivity type drift region having a first main surface and a second main surface;
A second conductivity type channel region selectively provided along the first main surface; a first conductivity type first semiconductor region selectively provided in the channel region; the first semiconductor region; A first electrode connected to both of the channel regions, along the inner peripheral surface of the first trench groove that reaches the drift region through the channel region from the first main surface adjacent to the first semiconductor region An active region having a gate insulating film provided, a gate electrode embedded in the first trench groove through the gate insulating film;
An insulator embedded in a second trench groove extending deeper than the channel region from the first main surface, and provided on the terminal structure region side of the second trench groove and connected to the first electrode A transition region having a second conductivity type bypass region;
A second semiconductor region of a second conductivity type provided along the second main surface of the drift region;
A second electrode connected to the second semiconductor region;
A cutting surface extending from the first main surface to the second main surface along the outer peripheral edge of the termination structure region;
A semiconductor device comprising: In a semiconductor device having a transition region between an active region and a termination structure region surrounding the active region,
A first conductivity type drift region having a first main surface and a second main surface;
A second conductivity type channel region selectively provided along the first main surface; a first conductivity type first semiconductor region selectively provided in the channel region; the first semiconductor region; A first electrode connected to both of the channel regions; a gate insulating film provided along the channel region between the first semiconductor region and the drift region; and a gate electrode provided along the gate insulating film An active region having
An insulating film provided along an inner peripheral surface of the trench groove extending deeper than the channel region from the first main surface, an electrode embedded in the trench groove through the insulating film, and the trench groove A transition region provided on the termination structure region side and having a second conductivity type bypass region connected to the first electrode;
A second semiconductor region of the first conductivity type provided along the second main surface of the drift region;
A second electrode connected to the second semiconductor region;
A cutting surface extending from the first main surface to the second main surface along the outer peripheral edge of the termination structure region;
A semiconductor device comprising: In a semiconductor device having a transition region between an active region and a termination structure region surrounding the active region,
A first conductivity type drift region having a first main surface and a second main surface;
A second conductivity type channel region selectively provided along the first main surface; a first conductivity type first semiconductor region selectively provided in the channel region; the first semiconductor region; A first electrode connected to both of the channel regions; a gate insulating film provided along the channel region between the first semiconductor region and the drift region; and a gate electrode provided along the gate insulating film An active region having
An insulating film provided along an inner peripheral surface of the trench groove extending deeper than the channel region from the first main surface, an electrode embedded in the trench groove through the insulating film, and the trench groove A transition region provided on the termination structure region side and having a second conductivity type bypass region connected to the first electrode;
A second semiconductor region of a second conductivity type provided along the second main surface of the drift region;
A second electrode connected to the second semiconductor region;
A cutting surface extending from the first main surface to the second main surface along the outer peripheral edge of the termination structure region;
A semiconductor device comprising: In a semiconductor device having a transition region between an active region and a termination structure region surrounding the active region,
A first conductivity type drift region having a first main surface and a second main surface;
A second conductivity type channel region selectively provided along the first main surface; a first conductivity type first semiconductor region selectively provided in the channel region; the first semiconductor region; A first electrode connected to both of the channel regions, along the inner peripheral surface of the first trench groove that reaches the drift region through the channel region from the first main surface adjacent to the first semiconductor region An active region having a gate insulating film provided, a gate electrode embedded in the first trench groove through the gate insulating film;
An insulating film provided along an inner peripheral surface of the second trench groove extending deeper than the channel region from the first main surface, an electrode embedded in the second trench groove through the insulating film, and A transition region provided on the terminal structure region side of the second trench groove and having a second conductivity type bypass region connected to the first electrode;
A second semiconductor region of the first conductivity type provided along the second main surface of the drift region;
A second electrode connected to the second semiconductor region;
A cutting surface extending from the first main surface to the second main surface along the outer peripheral edge of the termination structure region;
A semiconductor device comprising: In a semiconductor device having a transition region between an active region and a termination structure region surrounding the active region,
A first conductivity type drift region having a first main surface and a second main surface;
A second conductivity type channel region selectively provided along the first main surface; a first conductivity type first semiconductor region selectively provided in the channel region; the first semiconductor region; A first electrode connected to both of the channel regions, along the inner peripheral surface of the first trench groove that reaches the drift region through the channel region from the first main surface adjacent to the first semiconductor region An active region having a gate insulating film provided, a gate electrode embedded in the first trench groove through the gate insulating film;
An insulating film provided along an inner peripheral surface of the second trench groove extending deeper than the channel region from the first main surface, an electrode embedded in the second trench groove through the insulating film, and A transition region provided on the terminal structure region side of the second trench groove and having a second conductivity type bypass region connected to the first electrode;
A second semiconductor region of a second conductivity type provided along the second main surface of the drift region;
A second electrode connected to the second semiconductor region;
A cutting surface extending from the first main surface to the second main surface along the outer peripheral edge of the termination structure region;
A semiconductor device comprising:   The semiconductor device according to claim 5, wherein an electrode in the trench is connected to the first electrode.   The semiconductor device according to claim 9, wherein the electrode in the trench is connected to the first electrode only at four corners of the semiconductor device.   The semiconductor device according to claim 7, wherein an electrode in the second trench groove is connected to the first electrode.   The semiconductor device according to claim 11, wherein the electrode in the second trench groove is connected to the first electrode only at four corners of the semiconductor device.   The semiconductor device according to claim 1, wherein the insulator in the trench is silicon oxide.   5. The semiconductor device according to claim 3, wherein the insulator in the second trench groove is silicon oxide.   9. The semiconductor device according to claim 3, wherein the first trench groove has the same depth as the second trench groove. 10.   The semiconductor device according to claim 1, wherein the impurity profile of the bypass region and the impurity profile of the channel region are the same.   16. The body region of the second conductivity type is selectively provided in the channel region, and the impurity profile of the bypass region and the impurity profile of the body region are the same. The semiconductor device as described in any one. 18. The semiconductor device according to claim 1, wherein the MOS gate structure of the active region is formed in a linear shape.

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