JP2007294510A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of making the reduction of a cost and an improvement in a performance coexist in the semiconductor device forming a plurality of amplifiers on the main surface of a semiconductor substrate. <P>SOLUTION: The two amplifiers E1 and E2, two grounding nodes C1 and C2 and wirings A, F, D0, D1, D2, B0, B1, B2 and Cx are formed on the main surface of the semiconductor substrate. In Fig., the two amplifiers E1 and E2 are arrayed in the vertical direction, the grounding node C1 connected to the lower amplifier E1 is arranged to a section lower than the amplifier E1 and the grounding node C2 connected to the upper amplifier E2 is arranged to the section upper than the amplifier E2. An induction wiring F is branched from the intermediate section of the wiring D0 for a common input, and formed asymmetrically to the wiring D0 for the common input. The wiring Cx for a shielding is disposed among the wirings D1 and D2 for an input connected at each input end of the two amplifiers E1 and E2 and the induction wirings F. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device in which an amplifier is formed on a main surface of a semiconductor substrate.

  A semiconductor device in which an amplifier is formed on the main surface of a semiconductor substrate is used as, for example, a high-frequency power amplifier. The amplifier is a bipolar junction transistor (hereinafter referred to as “BJT”) or a field effect transistor (Field). Effective Transistor, hereinafter referred to as “FET”).

  In general, in an amplifier including a BJT, the emitter terminal of the BJT is AC connected to the ground potential via a capacitive element, or the emitter terminal is connected to the ground potential both AC and DC. . In the amplifier including the FET, the source terminal of the FET is AC connected to the ground potential via the capacitive element, or the source terminal is connected to the ground potential both AC and DC. . In addition, the ground node connected to the emitter terminal or source terminal of the amplifier on the semiconductor substrate is electrically connected to a ground region such as a package separate from the semiconductor substrate via bonding wires, bumps, or through electrodes. The

  As a semiconductor device in which an amplifier is formed on the main surface of such a semiconductor substrate, a configuration disclosed in Non-Patent Document 1 is known. The semiconductor device disclosed in this document has a plurality of amplifiers arranged in parallel, power-divides an electric signal to be amplified, and inputs it to the input terminals of the plurality of amplifiers. The electric signals amplified and output in each of the amplifiers are combined and output.

  When a plurality of amplifiers are arranged, generally, a ground node is provided separately for each of the plurality of amplifiers on the semiconductor substrate, and bonding wires and bumps that connect the ground node and a ground region such as a package to each other. Alternatively, the through electrode is also provided separately. By doing so, the mutual inductance can be reduced and the overall impedance can be reduced.

  Further, when a plurality of amplifiers are arranged, in general, symmetry and uniformity of the arrangement are taken into consideration. As a result, in each of the plurality of amplifiers, a common layout is arranged at a constant interval in a fixed direction, or two types of layouts that are mirror images of each other are alternately arranged at a fixed interval in a fixed direction. Further, the input ends of the plurality of amplifiers arranged in a fixed direction are on one side, and the output ends of the plurality of amplifiers are on the other side.

  FIG. 19 is a diagram schematically showing a layout on a main surface of a semiconductor substrate in a conventional semiconductor device. In this figure, two amplifiers E1, E2, two ground nodes C1, C2, and wirings A, F, D0, D1, D2, B1, B2, B0 are shown. In this drawing, two amplifiers E1 and E2 are arranged in the vertical direction, and a ground node C1 connected to the lower amplifier E1 is arranged further below the amplifier E1 and connected to the upper amplifier E2. A node C2 is arranged further above the amplifier E2. The input terminals of the two amplifiers E1 and E2 are on the left side, and the output terminals of the two amplifiers E1 and E2 are on the right side.

  The common input wiring D0 provided on the input side (left side) of each of the two amplifiers E1 and E2 is connected to the wiring A through an AC coupling capacitive element, and extends from the capacitive element to the branch position PI. Exist. The input wiring D1 extends from the branch position PI to the input end of the amplifier E1, and the input wiring D2 extends from the branch position PI to the input end of the amplifier E2. Further, a wiring F for supplying a DC bias voltage to the amplifiers E1 and E2 is connected to the common input wiring D0 between the capacitive element and the branch position PI, and extends upward from the connection point. ing. The output wiring B1 extends from the output terminal of the amplifier E1 to the branch position PO, the output wiring B2 extends from the output terminal of the amplifier E2 to the branch position PO, and is further output to the right from the branch position PO. The wiring line B0 extends.

In the semiconductor device configured as described above, the AC signal propagated through the common input wiring D0 via the wiring A and the capacitive element and the DC signal propagated through the wiring F are superimposed on each other and branched. The position PI is reached, the power is branched at the branch position PI, and input to the input terminals of the amplifiers E1 and E2 via the input wirings D1 and D2. Further, the electric signals amplified in the amplifiers E1 and E2 and outputted from the output terminal reach the branch position PO through the output wirings B1 and B2, and are combined in power at the branch position PO to be the common output wiring B0. Propagate further.
Cheng-Chi Yen, et al, “A 0.25-μm 20-dBm 2.4-GHz CMOS Power Amplifier With an Integrated Diode Linearizer”, IEEE Microwave and Wireless Components Letters, Vol.13, No.2, pp.45-47 (2003 ).

  By the way, as in the layout shown in FIG. 19, on the main surface of the semiconductor substrate, the amplifiers E1, E2, the ground nodes C1, C2, the input wirings D1, D2, and the output wirings B1, B2 are symmetrical. It can be arranged with good nature. However, the wirings A and F located to the left of the branch position PI are not always arranged with good symmetry. In the layout shown in FIG. 19, the wiring F extends upward from the connection point with the common input wiring D0 and is asymmetric with respect to the common input wiring D0.

  When such an asymmetry exists, the input wirings D1 and D2 have different influences due to capacitive coupling and inductive coupling with the wiring F, and therefore have different potentials and currents. Hereinafter, as described above, the wiring is branched from the middle of the common input wiring or the common output wiring, and is asymmetric with respect to the common input wiring or the common output wiring. Wirings that have different effects due to capacitive coupling and inductive coupling to the output wirings are called induction wirings. If the potentials and currents of the input wirings D1 and D2 are different from each other, the amplitudes and phases of the electrical signals that are amplified by the amplifiers E1 and E2 and output from the output terminal are different from each other. As a result, the power of the electrical signal after power synthesis at the branch position PO is smaller than the sum of the powers of the electrical signals output from the output terminals of the amplifiers E1 and E2.

  20 shows an output electric signal of the amplifier E1, an output electric signal of the amplifier E2, and an electric signal after power combining at the branch position PO in the conventional semiconductor device whose layout is shown in FIG. It is a figure which shows an example. FIG. 20A shows the output electric signal of the amplifier E1, FIG. 20B shows the output electric signal of the amplifier E2, and FIG. 20C shows the electric signal after power combining at the branch position PO. . Thus, a loss occurs during power combining, and amplification performance is degraded. When the distance between the guide wiring F and the input wirings D1 and D2 is intended to be reduced with the aim of further high integration, the above performance deterioration becomes remarkable. For this reason, it is difficult to achieve both cost reduction and high performance.

  The present invention has been made to solve the above-described problems, and is a semiconductor device in which a plurality of amplifiers are formed on the main surface of a semiconductor substrate, and can achieve both cost reduction and high performance. The purpose is to provide.

  A semiconductor device according to the present invention includes, on a main surface of a semiconductor substrate, (1) a plurality of amplifiers each amplifying an electric signal input to an input end and outputting from the output end, and (2) an input of each of the plurality of amplifiers Common input wiring that propagates electrical signals to be input to the end to the branch position, (3) Multiple input wirings that propagate electrical signals from the branch position to the input ends of each of the amplifiers, and (4) Common Inductive wiring that branches off from the middle of the input wiring and is asymmetric with respect to the common input wiring. (5) Arranged between the input wiring and the induction wiring. And shielding wiring that shields the influence on the area.

  Further, the semiconductor device according to the present invention includes (1) a plurality of amplifiers that amplify electric signals input to the input terminals and output from the output terminals, and (2) a plurality of amplifiers, respectively, on the main surface of the semiconductor substrate. Multiple output wirings that propagate the electrical signal output from the output terminal to the branch position, (3) common output wiring that further propagates the electrical signal from the branch position, and (4) from the middle of the common output wiring Branch wiring that is asymmetric with respect to the common output wiring, and (5) is arranged between the output wiring and the induction wiring to shield the influence from the induction wiring to the output wiring. And a shield wiring.

  Further, the shield wiring may be provided on both the input end side and the output end side of the plurality of amplifiers.

  The semiconductor device according to the present invention is a semiconductor device in which a plurality of amplifiers are formed on the main surface of a semiconductor substrate, and can achieve both cost reduction and high performance.

  The best mode for carrying out the present invention will be described below in detail with reference to the accompanying drawings. In the description of the drawings, the same elements are denoted by the same reference numerals, and redundant description is omitted.

(First embodiment)
First, a first embodiment of a semiconductor device according to the present invention will be described. FIG. 1 is a diagram schematically showing a layout on the main surface of a semiconductor substrate in the semiconductor device according to the first embodiment. As shown in this figure, the semiconductor device according to the first embodiment includes two amplifiers E1, E2, two ground nodes C1, C2, and wirings A, F, on the main surface of the semiconductor substrate. D0, D1, D2, B0, B1, B2, and Cx are formed.

  In this drawing, two amplifiers E1 and E2 are arranged in the vertical direction, and a ground node C1 connected to the lower amplifier E1 is arranged further below the amplifier E1 and connected to the upper amplifier E2. A node C2 is arranged further above the amplifier E2. The input terminals of the two amplifiers E1 and E2 are on the left side, and the output terminals of the two amplifiers E1 and E2 are on the right side.

  Each of the two amplifiers E1 and E2 includes a grounded-emitter BJT or a common-source FET, and amplifies an electrical signal input to the input terminal and outputs the amplified signal from the output terminal. In an amplifier including a grounded emitter BJT, the emitter terminal of the BJT is connected to the ground node at least in an AC manner, the base terminal of the BJT is connected to the input terminal of the amplifier, and the collector terminal of the BJT is connected to the output terminal of the amplifier. Has been. On the other hand, in an amplifier including a grounded-source FET, the source terminal of the FET is at least AC-connected to the ground node, the gate terminal of the FET is connected to the input terminal of the amplifier, and the drain terminal of the FET is the output terminal of the amplifier. It is connected to the.

  The common input wiring D0 provided on the input side (left side) of each of the two amplifiers E1 and E2 is connected to the wiring A through an AC coupling capacitive element, and extends from the capacitive element to the branch position PI. Exist. The input wiring D1 extends from the branch position PI to the input end of the amplifier E1, and the input wiring D2 extends from the branch position PI to the input end of the amplifier E2. Further, the induction wiring F for supplying the DC bias voltage to the amplifiers E1 and E2 is connected to the common input wiring D0 between the capacitive element and the branch position PI, and extends upward from the connection point. And is asymmetric with respect to the common input wiring D0. Here, the induction wiring is a wiring branched from the middle of the common input wiring or the common output wiring, and is asymmetric with respect to the common input wiring or the common output wiring. Alternatively, wirings that affect the influence of capacitive coupling and inductive coupling on a plurality of output wirings are called induction wirings. Further, the output wiring B1 extends from the output end of the amplifier E1 to the branch position PO, the output wiring B2 extends from the output end of the amplifier E2 to the branch position PO, and further to the right from the branch position PO. The common output wiring B0 extends.

  The shield wiring Cx is provided on the opposite side of the two amplifiers E1 and E2 across the input wirings D1 and D2 connected to the input ends of the two amplifiers E1 and E2. In other words, the input wirings D1 and D2 and the branch position PI exist on the right side of the shielding wiring Cx, and the guidance wiring F exists on the left side of the shielding wiring Cx. In a plan view, the shield wiring Cx and the common input wiring DO intersect each other, but the intersection has a multilayer wiring structure, and the shield wiring Cx and the common input wiring DO are electrically connected to each other. Not connected. The shield wiring Cx has one end connected to the ground node C1 and the other end connected to the ground node C2.

  The ground nodes C1 and C2 connected to the emitter terminals or the source terminals of the amplifiers E1 and E2 on the semiconductor substrate are electrically connected to a ground region such as a package separate from the semiconductor substrate via bonding wires, bumps, or through electrodes. Connected. As a result, the shield wiring Cx is set to the ground potential.

  In the semiconductor device configured as described above, an AC signal output from another circuit on the same semiconductor substrate is propagated to the wiring A, or an AC signal from an external signal source is propagated. In addition, a DC signal output from another circuit on the same semiconductor substrate is propagated to the guide wiring F, or a DC signal from an external signal source is propagated. The AC signal propagated through the common input wiring D0 via the wiring A and the capacitive element and the DC signal propagated through the induction wiring F are superimposed on each other to reach the branch position PI. The branch position PI The power is branched and input to the input terminals of the amplifiers E1 and E2 via the input wirings D1 and D2. Further, the electric signals amplified in the amplifiers E1 and E2 and outputted from the output terminal reach the branch position PO through the output wirings B1 and B2, and are combined in power at the branch position PO to be the common output wiring B0. Propagate further. Since the induction wiring F is a wiring branched from the common input wiring D0 through which the AC signal propagates, the potential of the induction wiring F varies according to the AC signal. Due to the potential fluctuation of the induction wiring F, the potential of the induction wiring F and the wiring having capacitive coupling or inductive coupling is affected.

  In the semiconductor device according to the present embodiment, since the shielding wiring Cx is provided between the input wirings D1 and D2 and the induction wiring F, each of the input wirings D1 and D2 is connected to the induction wiring F. The influence due to the capacitive coupling and inductive coupling of is reduced, and therefore the difference in potential and current is reduced. Since the difference between the potentials and currents of the input wirings D1 and D2 is reduced, the difference between the amplitude and phase of the electric signals amplified by the amplifiers E1 and E2 and output from the output end is also reduced. As a result, the power of the electrical signal after power synthesis at the branch position PO is substantially equal to the sum of the powers of the electrical signals output from the output ends of the amplifiers E1 and E2.

  FIG. 2 shows an output electric signal of the amplifier E1, an output electric signal of the amplifier E2, and an electric signal after power synthesis at the branch position PO in the semiconductor device according to the first embodiment whose layout is shown in FIG. It is a figure which shows an example of each waveform. 2A shows the output electric signal of the amplifier E1, FIG. 2B shows the output electric signal of the amplifier E2, and FIG. 2C shows the electric signal after the power synthesis at the branch position PO. . In this way, loss during power combining is reduced, and deterioration in amplification performance is suppressed. Even when an attempt is made to reduce the distance between the guide wiring F and the input wirings D1 and D2 in order to achieve high integration in order to reduce costs, the above performance deterioration is suppressed. Thus, both cost reduction and high performance can be achieved.

  Next, the results of the simulation performed to confirm the effect due to the provision of the shield wiring Cx will be described with reference to FIGS. FIG. 3 is a diagram showing three types of wiring layout assumed in the simulation. The type 1 wiring layout shown in FIG. 5A includes a common input wiring D0 and input wirings D1 and D2. The type 1 wiring layout shown in FIG. 6B further includes a guide wiring F in addition to the common input wiring D0 and the input wirings D1 and D2, and the conventional wiring layout shown in FIG. It corresponds to. Further, the type 1 wiring layout shown in FIG. 5C further includes a shielding wiring Cx in addition to the common input wiring D0, the input wirings D1 and D2, and the induction wiring F. FIG. This corresponds to the wiring layout of the present embodiment shown.

  The width of each wiring is 10 μm. The length of the input wirings D1 and D2 in the vertical direction is 200 μm, and the length of the shield wiring Cx in the vertical direction is also 200 μm. The distance between the centers of the input wiring D2 and the induction wiring F is 50 μm, the distance between the centers of the input wirings D1 and D2 and the shielding wiring Cx is 25 μm, and the center between the shielding wiring Cx and the induction wiring F The distance is 25 μm.

  FIG. 4 is a diagram showing a multilayer wiring structure in the vicinity of the intersection between the shield wiring Cx and the common input wiring DO assumed in the simulation. In general, the wiring layer is preferably formed on the surface of the semiconductor substrate. By doing so, the layer thickness can be increased and the impedance can be reduced. However, at the intersection of the shield wiring Cx and the common input wiring DO, for example, the shield wiring Cx is embedded in order to prevent the two wirings from being electrically connected. FIG. 4 shows a state in which the shield wiring Cx is connected by a via hole between the first metal layer and the second metal layer.

The semiconductor substrate is a Si substrate having a thickness of 200 μm and a resistivity of 10 Ω · cm. An electrode is formed on the lower surface of the semiconductor substrate. A first SiO ₂ layer (1.5 μm thickness, relative dielectric constant 4.0) and a first Al metal layer (0.7 μm thickness) are sequentially formed on the upper surface of the semiconductor substrate. ), A second SiO ₂ layer (1.5 μm thick, relative dielectric constant 4.0) and a second Al metal layer (3 μm thick). The first 2SiO ₂ layer via hole is formed, the by the 1Al metal layer through a via hole and a second 2Al metal layer are electrically connected to each other, thereby, the shielding wiring Cx are formed.

  FIG. 5 is a graph showing a simulation result in the case of the type 1 wiring layout shown in FIG. FIG. 6 is a graph showing a simulation result in the case of the type 2 wiring layout shown in FIG. FIG. 7 is a graph showing a simulation result in the case of the type 3 wiring layout shown in FIG. Each figure (a) shows the frequency dependence of the power ratio of the electric signal of input wiring D1, D2. Each figure (b) shows the frequency dependence of the phase difference of the electric signal of input wiring D1, D2. The frequency dependence of the power ratio and phase difference of the electrical signals of the input wirings D1 and D2 is shown when the termination resistance values Rterm of the input wirings D1 and D2 are 5Ω and 50 kΩ, respectively.

  In the case of the type 1 wiring layout shown in FIG. 3A, as shown in FIG. 5, when the termination resistance values of the input wirings D1 and D2 are both 5Ω and 50 kΩ, a frequency of 10 MHz to In the 10 GHz range, the power ratio of the electrical signals of the input wirings D1 and D2 was 0 dB, and the phase difference of the electrical signals of the input wirings D1 and D2 was 0 deg.

  In the case of the type 2 wiring layout shown in FIG. 3B, as shown in FIG. 6, the input wiring is used when the termination resistance values of the input wirings D1 and D2 are both 5Ω and 50 kΩ. The power ratio of the electrical signals D1 and D2 is approximately 0 dB in the frequency range of 10 MHz to 1 GHz, but increases rapidly when the frequency exceeds 1 GHz. Further, the phase difference between the electrical signals of the input wirings D1 and D2 is substantially 0 deg in the frequency range of 10 MHz to 100 MHz, but increases rapidly when the frequency exceeds 100 MHz.

  In the case of the type 3 wiring layout shown in FIG. 3 (c), as shown in FIG. 7, when the termination resistance values of the input wirings D1 and D2 are both 5Ω and 50kΩ, the input wiring The power ratio of the electric signals D1 and D2 is approximately 0 dB in the frequency range of 10 MHz to 100 MHz, but is approximately 0.2 dB at the frequency of 1 GHz, and further increases when the frequency exceeds 1 GHz. Further, the phase difference between the electrical signals of the input wirings D1 and D2 is approximately 0 deg in the frequency range of 10 MHz to 100 MHz, but is approximately 4 deg at the frequency of 1 GHz, and becomes larger when the frequency exceeds 1 GHz.

  As can be seen by comparing FIG. 6 and FIG. 7, in the type 3 wiring layout in which the shielding wiring Cx is provided in contrast to the type 2 wiring layout in which the shielding wiring is not provided, the frequency of 1 GHz is set. In the high frequency region that exceeds, the phase difference between the electrical signals of the input wirings D1 and D2 is small. Thus, by providing the shield wiring Cx, the power ratio and phase difference of the electrical signals of the input wirings D1 and D2 are reduced. Therefore, the electrical signal amplified by the amplifiers E1 and E2 and output from the output terminal Differences in amplitude and phase are also reduced. As a result, the power of the electrical signal after power synthesis at the branch position PO is substantially equal to the sum of the powers of the electrical signals output from the output ends of the amplifiers E1 and E2.

(Second Embodiment)
Next, a second embodiment of the semiconductor device according to the present invention will be described. FIG. 8 is a diagram schematically showing a layout on the main surface of the semiconductor substrate in the semiconductor device according to the second embodiment. As shown in this figure, the semiconductor device according to the second embodiment includes two amplifiers E1, E2, four ground nodes C1, C2, G1, G2, and wiring on the main surface of the semiconductor substrate. A, F, D0, D1, D2, B0, B1, B2, and Cx are formed.

  Compared with the layout of the first embodiment shown in FIG. 1, the layout of the second embodiment shown in FIG. 8 is different in that ground nodes G1 and G2 are provided separately from the ground nodes C1 and C2. In addition, the difference is that a shield wiring Cx extends between the ground node G1 and the ground node G2. The added ground nodes G1 and G2 are electrically connected to a ground region such as a package separate from the semiconductor substrate via bonding wires, bumps or through electrodes. As a result, the shield wiring Cx is set to the ground potential. The semiconductor device according to the second embodiment having such a layout can achieve the same effects as the semiconductor device according to the first embodiment.

  Furthermore, according to the semiconductor device according to the second embodiment, since the wire bonds connected to the ground nodes G1 and G2 can be independent of the amplifier ground nodes C1 and C2, the impedance of the shield wiring Cx can be reduced. The shield effect can be improved. In addition, since the potential of the shield wiring Cx is independent of the ground potential of the amplifier, it is possible to eliminate the influence of fluctuations in the ground potential of the amplifier due to the operation of the amplifier on the shield wiring Cx. Further, the degree of freedom in layout of the shield wiring Cx is increased, and further high integration is possible.

(Third embodiment)
Next, a third embodiment of the semiconductor device according to the present invention will be described. FIG. 9 is a diagram schematically showing a layout on the main surface of the semiconductor substrate in the semiconductor device according to the third embodiment. As shown in this figure, the semiconductor device according to the third embodiment includes two amplifiers E1, E2, two ground nodes C1, C2, and wirings A, F, on the main surface of the semiconductor substrate. D0, D1, D2, B1, B2, and Cx are formed.

  Compared with the layout of the first embodiment shown in FIG. 1, the layout of the third embodiment shown in FIG. 9 is such that the output wirings B1 and B2 are not connected to each other on the semiconductor substrate and the common output wiring B0. It is different in that is not provided. In this case, the output wirings B1 and B2 on the semiconductor substrate are connected to the outside of the semiconductor substrate, and electric signals output from the amplifiers E1 and E2 are combined with power outside the semiconductor substrate. The semiconductor device according to the third embodiment having such a layout can achieve the same effects as the semiconductor device according to the first embodiment.

(Fourth embodiment)
Next, a fourth embodiment of a semiconductor device according to the present invention will be described. FIG. 10 is a diagram schematically showing a layout on the main surface of the semiconductor substrate in the semiconductor device according to the fourth embodiment. As shown in this figure, the semiconductor device according to the fourth embodiment includes two amplifiers E1, E2, two ground nodes C1, C2, and wirings A, G, F, D0, D1, D2, B0, B1, B2, and Cy are formed.

  Compared with the layout of the first embodiment shown in FIG. 1, the layout of the fourth embodiment shown in FIG. 10 is different in that a shield wiring Cy is provided instead of the shield wiring Cx. The difference is that an induction wiring G is further provided on the output side.

  The added shield wiring Cy is provided on the opposite side of the two amplifiers E1 and E2 with the output wirings B1 and B2 connected to the output ends of the two amplifiers E1 and E2 interposed therebetween. In other words, the output wirings B1 and B2 and the branch position PO exist on the left side of the shielding wiring Cy, and the guidance wiring G exists on the right side of the shielding wiring Cy. In a plan view, the shield wiring Cy and the common output wiring BO intersect each other, but the intersection has a multilayer wiring structure, and the shield wiring Cy and the common output wiring BO are electrically connected to each other. Not connected. The shield wiring Cy has one end connected to the ground node C1 and the other end connected to the ground node C2. The induction wiring G is connected to the common output wiring B0, extends upward from the connection point, and is asymmetric with respect to the common output wiring B0.

  The ground nodes C1 and C2 connected to the emitter terminals or the source terminals of the amplifiers E1 and E2 on the semiconductor substrate are electrically connected to a ground region such as a package separate from the semiconductor substrate via bonding wires, bumps, or through electrodes. Connected. As a result, the shield wiring Cy is set to the ground potential.

  In the semiconductor device according to the present embodiment, since the shielding wiring Cy is provided between the output wirings B1 and B2 and the induction wiring G, each of the output wirings B1 and B2 is between the induction wiring G. The influence due to the capacitive coupling and inductive coupling of is reduced, and therefore the difference in potential and current is reduced. Since the difference between the potentials and currents of the output wirings B1 and B2 becomes small, the power of the electric signal after the power synthesis at the branch position PO is the electric power output from the output terminals of the amplifiers E1 and E2. It is approximately equal to the sum of signal powers. In this way, loss during power combining is reduced, and deterioration in amplification performance is suppressed. The above-described performance degradation is also suppressed when attempting to reduce the distance between the guide wiring G and the output wirings B1 and B2 with the intention of high integration. Thus, both cost reduction and high performance can be achieved.

  In the fourth embodiment, no shield wiring is provided on the input side, but the influence due to capacitive coupling or inductive coupling between the input wirings D1, D2 and the induction wiring F is sufficiently reduced. As long as the distance between both wires is large, it is sufficient.

(Fifth embodiment)
Next, a semiconductor device according to a fifth embodiment of the invention will be described. FIG. 11 is a diagram schematically showing a layout on the main surface of the semiconductor substrate in the semiconductor device according to the fifth embodiment. As shown in this figure, the semiconductor device according to the fifth embodiment includes two amplifiers E1, E2, two ground nodes C1, C2, and wirings A, G, on the main surface of the semiconductor substrate. F, D0, D1, D2, B0, B1, B2, Cx, and Cy are formed.

  The input-side shield wiring Cx in the fifth embodiment is the same as the input-side shield wiring Cx in the first embodiment. The output-side shield wiring Cy in the fifth embodiment is the same as the output-side shield wiring Cy in the fourth embodiment. Therefore, the semiconductor device according to the fifth embodiment can achieve the same effects as the semiconductor devices of the first embodiment and the fourth embodiment.

(Sixth embodiment)
Next, a sixth embodiment of a semiconductor device according to the present invention will be described. FIG. 12 is a diagram schematically showing a layout on the main surface of the semiconductor substrate in the semiconductor device according to the sixth embodiment. As shown in this figure, the semiconductor device according to the sixth embodiment includes four amplifiers E1 to E4, four ground nodes C1 to C4, and wirings A, F, on the main surface of the semiconductor substrate. D0 to D6, B0 to B6, Cx1, Cx3, Cx4, and Cx6 are formed.

  In the drawing, four amplifiers E1 to E4 are arranged in order in the vertical direction. A ground node C1 connected to the lowermost amplifier E1 is disposed below the amplifier E1, and a ground node C2 connected to the second amplifier E2 from the bottom is disposed above the amplifier E2, and the second from the top. A ground node C3 connected to the amplifier E3 is arranged below the amplifier E3, and a ground node C4 connected to the uppermost amplifier E4 is arranged above the amplifier E4. Each of the four amplifiers E1 to E4 has an input terminal on the left side, and each of the four amplifiers E1 to E4 has an output terminal on the right side.

  Each of the four amplifiers E1 to E4 includes a grounded-emitter BJT or a common-source FET, and amplifies an electrical signal input to the input terminal and outputs the amplified signal from the output terminal. In an amplifier including a grounded emitter BJT, the emitter terminal of the BJT is connected to the ground node at least in an AC manner, the base terminal of the BJT is connected to the input terminal of the amplifier, and the collector terminal of the BJT is connected to the output terminal of the amplifier. Has been. On the other hand, in an amplifier including a grounded-source FET, the source terminal of the FET is at least AC-connected to the ground node, the gate terminal of the FET is connected to the input terminal of the amplifier, and the drain terminal of the FET is the output terminal of the amplifier. It is connected to the.

  The common input wiring D0 provided on the input side (left side) of each of the four amplifiers E1 to E4 is connected to the wiring A through an AC coupling capacitive element, and extends from the capacitive element to the branch position PI0. Exist. An input wiring D5 extends from the branch position PI0 to another branch position PI1, and an input wiring D6 extends from the branch position PI0 to another branch position PI3. The input wiring D1 extends from the branch position PI1 to the input end of the amplifier E1, and the input wiring D2 extends from the branch position PI1 to the input end of the amplifier E2. An input wiring D3 extends from the branch position PI3 to the input end of the amplifier E3, and an input wiring D4 extends from the branch position PI3 to the input end of the amplifier E4. The induction wiring F is connected to the common input wiring D0 between the capacitive element and the branch position PI0, and extends upward from the connection point.

  The output wiring B1 extends from the output end of the amplifier E1 to the branch position PO1, and the output wiring B2 extends from the output end of the amplifier E2 to the branch position PO1. An output wiring B3 extends from the output end of the amplifier E3 to the branch position PO3, and an output wiring B4 extends from the output end of the amplifier E4 to the branch position PO3. Output wiring B5 extends from branch position PO1 to branch position PO0, and output wiring B6 extends from branch position PO3 to branch position PO0. Further, the common output wiring B0 extends further to the right from the branch position PO0.

  The shield wiring Cx1 is provided on the opposite side of the two amplifiers E1 and E2 across the input wirings D1 and D2 connected to the input ends of the two amplifiers E1 and E2. The shield wiring Cx3 is provided on the opposite side of the two amplifiers E3 and E4 with the input wirings D3 and D4 connected to the input ends of the two amplifiers E3 and E4 interposed therebetween. The shield wirings Cx4 and Cx6 are provided on the opposite side of the four amplifiers E1 to E4 across the input wirings D5 and D6. The shield wirings Cx1 and Cx4 have one end connected to the ground node C1 and the other end connected to the ground node C2. The shield wirings Cx3 and Cx6 have one end connected to the ground node C3 and the other end connected to the ground node C4.

  The ground nodes C1 to C4 connected to the emitter terminals or source terminals of the amplifiers E1 to E4 on the semiconductor substrate are electrically connected to a ground region such as a package separate from the semiconductor substrate via bonding wires, bumps, or through electrodes. Connected. As a result, the shield wirings Cx1, Cx3, Cx4, and Cx6 are set to the ground potential.

  In the semiconductor device configured as described above, an AC signal output from another circuit on the same semiconductor substrate is propagated to the wiring A, or an AC signal from an external signal source is propagated. In addition, a DC signal output from another circuit on the same semiconductor substrate is propagated to the guide wiring F, or a DC signal from an external signal source is propagated. The AC signal propagated through the common input wiring D0 via the wiring A and the capacitive element and the DC signal propagated through the induction wiring F are superimposed on each other to reach the branch position PI0, and the branch position PI0. Is further branched to input power via the input wirings D5 and D6 to branch positions PI1 and PI3, and further branched at the branch positions PI1 and PI3. Is input. In addition, the electric signals amplified by the amplifiers E1 to E4 and output from the output terminal reach the branch positions PO1 and PO3 through the output wirings B1 to B4, and the power is synthesized at the branch positions PO1 and PO3. The branch position PO0 is reached through B5 and B6, and power is synthesized at the branch position PO0, and further propagates through the common output wiring B0.

In the semiconductor device according to the present embodiment, since the shielding wiring Cx1 is provided between the input wirings D1 and D2 and the input wiring D5, each of the input wirings D1 and D2 is connected to the input wiring D5. The influence due to capacitive coupling and inductive coupling between them is reduced. Since the shield wiring Cx3 is provided between the input wirings D3 and D4 and the input wiring D6, the input wirings D3 and D4 are caused by capacitive coupling and inductive coupling with the input wiring D6. This reduces the impact of Further, since the shielding wirings Cx4 and Cx6 are provided between the input wirings D5 and D6 and the induction wiring F, each of the input wirings D5 and D6 is capacitively coupled or induced with the induction wiring F. The effect of binding is reduced,
Therefore, the difference in potential and current between the input wirings D1 to D4 is reduced. Since the potential and current differences of the input wirings D1 to D4 are reduced, the amplitude and phase differences of the electrical signals amplified by the amplifiers E1 to E4 and output from the output end are also reduced. As a result, the power of the electrical signal after the power synthesis at the branch positions PO0, PO1, and PO3 is substantially equal to the sum of the powers of the electrical signals output from the output terminals of the amplifiers E1 to E4. In this way, loss during power combining is reduced, and deterioration in amplification performance is suppressed. Even when an attempt is made to reduce the distance between the guide wiring F and the input wirings D1 to D4 for the purpose of high integration in order to reduce the cost, the above performance deterioration is suppressed. Thus, both cost reduction and high performance can be achieved.

(Seventh embodiment)
Next, a seventh embodiment of the semiconductor device according to the present invention will be described. FIG. 13 is a diagram schematically showing a layout on the main surface of the semiconductor substrate in the semiconductor device according to the seventh embodiment. As shown in this figure, the semiconductor device according to the seventh embodiment includes four amplifiers E1 to E4, four ground nodes C1 to C4, and wirings A, F, on the main surface of the semiconductor substrate. D0 to D6, B0 to B6, and Cx1 to Cx6 are formed.

  Compared with the layout of the sixth embodiment shown in FIG. 12, the layout of the seventh embodiment shown in FIG. 13 is different in that shield wirings Cx2 and Cx5 are further provided. The added shield wiring Cx2 electrically connects the shield wiring Cx1 and the shield wiring Cx3 to each other, and is provided between the amplifiers E1 to E4 and the input wirings D5 and D6. The added shield wiring Cx5 electrically connects the shield wiring Cx4 and the shield wiring Cx6 to each other, and is provided between the input wirings D5 and D6 and the induction wiring F. . The semiconductor device according to the seventh embodiment having such a layout can achieve the same effects as the semiconductor device according to the sixth embodiment.

(Eighth embodiment)
Next, an eighth embodiment of a semiconductor device according to the present invention will be described. FIG. 14 is a diagram schematically showing a layout on the main surface of the semiconductor substrate in the semiconductor device according to the eighth embodiment. As shown in this figure, the semiconductor device according to the eighth embodiment includes four amplifiers E1 to E4, four ground nodes C1 to C4, and wirings A, F, on the main surface of the semiconductor substrate. D0 to D6, B0 to B6, Cx1 to Cx6, and Cy1 to Cy3 are formed.

  Compared with the layout of the seventh embodiment shown in FIG. 13, the layout of the eighth embodiment shown in FIG. 14 is different in that shield wirings Cy1 to Cy3 are further provided. The added shield wiring Cy1 is provided on the opposite side of the two amplifiers E1 and E2 across the output wirings B1 and B2 connected to the output ends of the two amplifiers E1 and E2, respectively. One end is connected to the ground node C1, and the other end is connected to the ground node C2. The added shielding wiring Cy3 is provided on the opposite side of the two amplifiers E3 and E4 with the output wirings B3 and B4 connected to the output ends of the two amplifiers E3 and E4 interposed therebetween, respectively. One end is connected to the ground node C3, and the other end is connected to the ground node C4. The added shield wiring Cy2 electrically connects the shield wiring Cy1 and the shield wiring Cy3 to each other.

  The semiconductor device according to the eighth embodiment having such a layout can achieve the same effects as the semiconductor device according to the seventh embodiment, and further includes shield wirings Cy1 to Cy3. Since it is possible to prevent a difference in amplitude and phase between the electrical signals output from the output terminals of the amplifiers E1 to E4, the loss during power synthesis is reduced from this point as well, and the amplification performance Deterioration is suppressed.

(Ninth embodiment)
Next, a ninth embodiment of a semiconductor device according to the present invention will be described. FIG. 15 is a diagram schematically showing a layout on the main surface of the semiconductor substrate in the semiconductor device according to the ninth embodiment. As shown in this figure, the semiconductor device according to the ninth embodiment includes two amplifiers E1 and E2, three ground nodes G0 to G2, and wirings A, G, and N on the main surface of the semiconductor substrate. F, D0, D1, D2, B0, B1, B2, and Cx are formed.

  Compared with the layout of the second embodiment shown in FIG. 8, the layout of the ninth embodiment shown in FIG. 15 is different in that a ground node G0 is provided instead of the ground nodes C1 and C2. The added ground node G0 is provided at a position between the amplifier E1 and the amplifier E2, and is electrically connected to a ground region such as a package separate from the semiconductor substrate via bumps or through electrodes. The In an amplifier including a grounded emitter BJT, the emitter terminal of the BJT is connected to the ground node G0 at least in an AC manner. On the other hand, in an amplifier including a common source FET, the source terminal of the FET is at least AC-connected to the ground node G0. The semiconductor device according to the ninth embodiment having such a layout can achieve the same effects as the semiconductor device according to the first embodiment.

(10th Embodiment)
Next, a tenth embodiment of a semiconductor device according to the present invention will be described. FIG. 16 is a diagram schematically showing a layout on the main surface of the semiconductor substrate in the semiconductor device according to the tenth embodiment. As shown in this figure, the semiconductor device according to the tenth embodiment has two amplifiers E1, E2, a ground node G0, and wirings A, G, F, D0, D1 on the main surface of the semiconductor substrate. , D2, B0, B1, B2, Cx, Cx1, Cx2 are formed.

  Compared with the layout of the ninth embodiment shown in FIG. 15, the layout of the tenth embodiment shown in FIG. 16 is different in that the ground nodes G1 and G2 are not provided, and the shield wiring Cx is different. It is different in that it is connected to the ground node G0 via wirings Cx1 and Cx2. The wirings Cx1 and Cx2 for connecting the shield wiring Cx and the ground node G0 are made of a wiring layer different from the wiring layer for the input wirings D1 and D2. The semiconductor device according to the ninth embodiment having such a layout can achieve the same effects as the semiconductor device according to the first embodiment.

(Other embodiments)
The present invention is not limited to the above embodiment, and various modifications can be made. For example, each of the input wiring, the output wiring, and the shielding wiring may be formed in parallel with the arrangement direction of the plurality of amplifiers. However, as shown in FIGS. On the other hand, it may be formed obliquely. In the layouts shown in FIGS. 17 and 18, the input wirings D1 and D2 are slanted, and the input wiring D1 and the input wiring D2 are not on the same straight line. In the layout shown in FIG. 18, the shield wirings Cx1 and Cx2 are slanted, and the shield wiring Cx1 and the shield wiring Cx2 are not on the same straight line.

  In other words, when the guide wiring F is asymmetric with respect to the common input wiring, that is, the plurality of input wiring groups, the shielding wiring is not related to the branch position regardless of the arrangement direction of the amplifiers or the arrangement direction of the input wiring. By forming it between the induction wiring F, the input wiring can be shielded from the influence of the induction wiring F. The present invention can also be applied to a semiconductor device having an arbitrary number of amplifiers and an arbitrary number of branches. In the above-described embodiment, the configuration in which both ends of the shield wiring are connected to the reference potential has been described as an example. However, the configuration in which only one end is connected to the reference potential, or the configuration in which the other end is connected to the reference potential. The effects of the present invention can be achieved.

It is a figure which shows typically the layout on the main surface of the semiconductor substrate in the semiconductor device which concerns on 1st Embodiment. The output electric signal of the amplifier E1, the output electric signal of the amplifier E2, and the electric signal after power combining at the branch position PO in the semiconductor device according to the first embodiment whose layout is shown in FIG. It is a figure which shows an example. It is a figure which shows three types of wiring layout assumed in the case of simulation. It is a figure which shows the multilayer wiring structure in the vicinity position of the cross | intersection part of the wiring Cx for shielding assumed in the case of simulation, and wiring DO for common inputs. It is a graph which shows the simulation result in the case of the type 1 wiring layout shown by Fig.3 (a). It is a graph which shows the simulation result in the case of the type 2 wiring layout shown by FIG.3 (b). It is a graph which shows the simulation result in the case of the type 3 wiring layout shown by FIG.3 (c). It is a figure which shows typically the layout on the main surface of the semiconductor substrate in the semiconductor device which concerns on 2nd Embodiment. It is a figure which shows typically the layout on the main surface of the semiconductor substrate in the semiconductor device which concerns on 3rd Embodiment. It is a figure which shows typically the layout on the main surface of the semiconductor substrate in the semiconductor device which concerns on 4th Embodiment. It is a figure which shows typically the layout on the main surface of the semiconductor substrate in the semiconductor device which concerns on 5th Embodiment. It is a figure which shows typically the layout on the main surface of the semiconductor substrate in the semiconductor device which concerns on 6th Embodiment. It is a figure which shows typically the layout on the main surface of the semiconductor substrate in the semiconductor device which concerns on 7th Embodiment. It is a figure which shows typically the layout on the main surface of the semiconductor substrate in the semiconductor device which concerns on 8th Embodiment. It is a figure which shows typically the layout on the main surface of the semiconductor substrate in the semiconductor device which concerns on 9th Embodiment. It is a figure which shows typically the layout on the main surface of the semiconductor substrate in the semiconductor device which concerns on 10th Embodiment. It is a figure which shows typically the layout on the main surface of the semiconductor substrate in the semiconductor device which concerns on other embodiment. It is a figure which shows typically the layout on the main surface of the semiconductor substrate in the semiconductor device which concerns on other embodiment. It is a figure which shows typically the layout on the main surface of the semiconductor substrate in the conventional semiconductor device. FIG. 19 is a diagram illustrating an example of waveforms of an output electric signal of the amplifier E1, an output electric signal of the amplifier E2, and an electric signal after power combining at the branch position PO in the conventional semiconductor device whose layout is shown in FIG. It is.

Explanation of symbols

E1 to E4... Amplifier, C1 to C4, G0 to G2... Ground node, D0 to D6... Input wiring, B0 to B6... Output wiring, F, G. Cy3: Shield wiring.

Claims (2)

On the main surface of the semiconductor substrate,
A plurality of amplifiers that amplify electrical signals input to the input terminals and output from the output terminals;
A common input wiring for propagating an electric signal to be input to an input end of each of the plurality of amplifiers to a branch position;
A plurality of input wirings for propagating electrical signals from the branch positions to the input ends of the plurality of amplifiers;
A wiring branched off from the middle of the common input wiring, and an induction wiring that is asymmetric with respect to the common input wiring;
A shield wiring that is disposed between the input wiring and the induction wiring and shields the influence from the induction wiring to the input wiring;
A semiconductor device comprising: On the main surface of the semiconductor substrate,
A plurality of amplifiers that amplify electrical signals input to the input terminals and output from the output terminals;
A plurality of output wirings for propagating electrical signals output from the output ends of the plurality of amplifiers to a branch position;
A common output wiring that further propagates an electrical signal from the branch position;
Inductive wiring that is branched from the middle of the common output wiring and is asymmetric with respect to the common output wiring;
A shield wiring that is arranged between the output wiring and the induction wiring and shields the influence from the induction wiring to the output wiring;
A semiconductor device comprising:

Images