JP2007288172A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To increase a withstanding voltage of a hetero junction used for reverse blocking in a reverse-blocking switching element that employs a wide bandgap semiconductor with a high withstand voltage and a low loss. <P>SOLUTION: A semiconductor device is a reverse-blocking switching element provided with: a switching element formed of a wide bandgap semiconductor on a first principal surface side where a first terminal 10 is formed, and a hetero junction diode for blocking a reverse current on a second principal surface side where a second terminal 13 is formed. A silicon semiconductor region 30a is provided at the side surface of the semiconductor to prevent deterioration in the withstand voltage of the hetero junction diode. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention provides a reverse blocking semiconductor switching element with high breakdown voltage and low loss.

Wide bandgap semiconductor devices with a band gap of 1.3 eV or more, such as SiC (silicon carbide), GaN (gallium nitride), and diamond, are capable of high pressure, low loss, and high frequency, and can operate at higher temperatures. There is. As a semiconductor device in which such a wide band gap semiconductor and a silicon semiconductor are brought into contact with each other, Patent Document 1 discloses a vertical field transistor realized by forming a GaN-based material on a Si substrate.

  On the other hand, there is a reverse blocking IGBT that improves the reverse blocking voltage of an IGBT (Insulated Gate Bipolar Transistor) for an application circuit such as a matrix converter. Patent Document 2 includes a {111} plane as a side wall, A reverse blocking IGBT using a silicon semiconductor having a groove having a {100} plane as a bottom surface is disclosed.

  Further, Patent Document 3 discloses a reverse blocking type switching element having a heterojunction diode in which a wide band gap semiconductor and a silicon semiconductor are in contact with each other.

Japanese Patent Laying-Open No. 2002-16262 (described in FIG. 1 and paragraph (0011)) Japanese Patent Laying-Open No. 2006-294716 (described in FIG. 1 and paragraph (0018)) JP 2006-186307 A (described in FIG. 1 and paragraph (0011))

  In the above prior art, the one described in Patent Document 1 discloses a structure in which a wide band gap semiconductor and a silicon semiconductor are brought into contact with each other. However, the contact surface is operated as a diode and the junction withstand voltage is increased. There was not enough consideration.

  The method described in Patent Document 2 describes a method of filling a reverse blocking isolation region of a silicon semiconductor substrate with a polysilicon layer or epitaxial silicon after forming a groove. However, a manufacturing method or semiconductor suitable for a wide band gap semiconductor is disclosed. The device structure has not been studied.

  Although the thing of patent document 3 says that the manufacturing process of a peripheral structure can be simplified because the depth direction of a semiconductor substrate is short, since the impurity diffusion rate in a wide band gap semiconductor is slow, the 1st main surface (surface) When an isolation region is formed in the depth direction of the semiconductor substrate so as to reach the heterojunction diode formed on the second main surface (back surface) side, the ion implantation becomes too high in energy or the impurity diffusion time is long. There is a problem of becoming too much.

  An object of the present invention is to provide a high breakdown voltage semiconductor device having a reverse blocking function and a switching function having a heterojunction, and in particular, to provide a semiconductor device using a wide band gap semiconductor having a high breakdown voltage and low loss. It is.

  In the semiconductor device of the present invention, in a reverse blocking switching element having a heterojunction, a heterojunction is formed on the side surface of the peripheral portion of the switching element in order to increase the breakdown voltage of the heterojunction.

  According to the present invention, it is possible to realize a wide band gap semiconductor switching element having reverse blocking characteristics and high breakdown voltage and low loss.

  In the semiconductor circuit of the present invention, in the semiconductor switching element having the first junction and the second junction, at least one region of the main current path between the first main terminal and the second main terminal of the semiconductor switching element is wide. A band gap semiconductor, wherein the forward voltage drop of the second junction is lower than the forward voltage drop of the first junction, and the second junction is in a forward bias state when the switching element is turned on in forward operation. In the reverse operation, a reverse bias state is provided, and in the reverse bias state, a depletion layer at the peripheral end of the second junction is provided to extend toward the first main surface where the first junction is formed.

  FIG. 1 shows a semiconductor device of this embodiment. In the semiconductor device of this embodiment, a SiC power MOSFET is formed on the first main surface side, and a heterojunction diode is formed between the polycrystalline silicon semiconductor region 1 and the n-type SiC semiconductor region 4 on the second main surface side. This is a reverse blocking type SiC power MOSFET. That is, the electrode layer 10 is the source electrode of the SiC power MOSFET and the n-type SiC semiconductor region 4 is the drain region, but the n-type SiC semiconductor region 4 is also the cathode region of the heterojunction diode, and the silicon semiconductor region 1 is heterogeneous. Serves as the anode region of the junction diode. Therefore, the electrode layer 13 is also referred to as an anode electrode of the semiconductor device.

  On the first main surface side, an n-type SiC semiconductor layer has a p-type body region 5a, floating field rings 5b and 5c for securing a drain breakdown voltage, an n-type source region 8a, a contact p-type semiconductor region 6a, a leakage current. A reduction n-type region 8b, a gate insulating film 15, a gate electrode layer 11, an insulating layer 12, and a source electrode layer 10 are formed. A polycrystalline silicon semiconductor region 30a is formed in a direction substantially perpendicular to the first main surface in the periphery of the power MOSFET, and a heterojunction diode is formed between the n-type SiC semiconductor layer 4 and the n-type SiC semiconductor layer 4. Alternatively, more strictly, the silicon semiconductor region 30a is formed so as to surround the side surface of the high breakdown voltage securing region 4 of the semiconductor element. The n-type regions 8a and 8b and the p-type regions 5a and 6a can be formed by ion implantation with high energy, but may be formed using an epitaxial process. In particular, the threshold voltage may be optimized by adding an epitaxial layer in the channel formation region immediately below the gate insulating film 15.

  In the semiconductor device of the present embodiment, the first junction formed by the p-type SiC semiconductor layer 5a and the n-type SiC semiconductor layer 4 secures the breakdown voltage in the off state in the forward operation of the power MOSFET, and the polycrystalline silicon semiconductor region 1 The reverse blocking voltage is ensured by the heterojunction which is the second junction formed by the n-type SiC semiconductor region 4. In addition, when the heterojunction diode is forward-biased like the Schottky diode, current flows mainly by majority carriers, and there is almost no minority carrier injection. Therefore, this semiconductor device is a reverse blocking SiC power MOSFET capable of high-speed switching. In the present embodiment, the switching element is a power MOSFET, but other switching elements such as a JFET, MESFET, and bipolar transistor may be incorporated. In addition, the switching element portion is not SiC, and other semiconductors may be used as long as they are semiconductors capable of forming heterojunction diodes, such as wide band gap semiconductors such as GaN and diamond, and GaAs.

The polycrystalline silicon semiconductor region 30a is subjected to, for example, magnetically enhanced inductively coupled plasma etching under a gas condition of 90% SF ₆ and 10% O ₂ using copper or nickel as a mask. The groove 20 formed in a direction substantially perpendicular to the main surface is formed, and the formed polycrystalline silicon layer 30 is deposited from the first main surface as shown in FIG. 2, and this can be patterned. The silicon semiconductor region 30a is a floating field ring in which the distance between the silicon semiconductor region 1 and the silicon semiconductor region 30a is such that the depletion layer can be connected, and before the breakdown phenomenon occurs due to electric field concentration around the anode-side semiconductor layer 1. Then, the depletion layer reaches 30a, and the electric field concentration is reduced around the anode-side semiconductor layer 1. Further, when a voltage is applied, a depletion layer sequentially spreads from the silicon semiconductor region 30a to the p-type SiC semiconductor regions 5e and 5d arranged as a floating field ring, and a breakdown voltage is deteriorated due to concentration of an electric field at the periphery of the heterojunction diode. High pressure resistance is prevented. In the present embodiment, the n-type SiC semiconductor region 8b is provided so that the leakage current does not flow on the surface of the first main surface. However, it is not necessary when the impurity concentration of the n-type SiC semiconductor region 4 is high. is there. In this embodiment, the floating field rings 5e and 5d are also provided on the first main surface. However, the required breakdown voltage may be obtained only by providing the semiconductor layer 30a. If necessary, impurities may be implanted into the groove by oblique ion implantation after the formation of the groove 20 in order to control the leakage current and adjust the extent of the depletion layer. Further, even if a thin oxide film such as a natural oxide film is formed on a part of the groove, for example, on the side wall, the potential of the silicon semiconductor region 30a can be changed so that the depletion layer extends along the silicon semiconductor region 30a. It doesn't matter.

  In this semiconductor device, since the silicon semiconductor region 30a is realized by forming the trench 20 and forming polycrystalline silicon therein, the impurity profile of the interface of the gate insulating film 15 and the main semiconductor region of SiC is adversely affected. There is an advantage that it is not necessary to use a high-temperature and long-time heat process.

  In addition, after forming the groove 20, a p-type SiC semiconductor region may be formed instead of the silicon semiconductor region 30a by oblique ion implantation of p-type impurities on the side surface of the groove, and then the groove 20 may be filled with an insulator. . However, in this case, the heat treatment for activating the p-type impurity formed on the side surface of the groove may not be sufficiently performed, but the floating field rings 5e and 5d are provided on the first main surface side, so that the floating Due to the synergistic effect with the field rings 5e and 5d, electric field concentration in the peripheral portion can be avoided and high breakdown voltage can be achieved.

  Note that the high breakdown voltage means formed on the first main surface side is not a floating field ring as in this embodiment, but an extension region or diffusion layer using a field plate or a low-concentration p-type semiconductor region, but a silicon semiconductor region. As in the floating field ring, a floating Schottky diode that is realized by being arranged in a ring shape and in contact with the wide band gap semiconductor region 4 may be used.

  Further, in this semiconductor device, the dimension X of the n-type SiC silicon semiconductor region 4 has a thickness that can secure a necessary breakdown voltage so that the on-resistance of the semiconductor element does not increase, but it can be as much as possible by etching from the second main surface. After the thinning, polycrystalline silicon is deposited from the second main surface to form a heterojunction with the n-type SiC semiconductor layer 4. Further, the silicon semiconductor region 1 is stacked thickly so that the thickness dimension Y of the semiconductor region is sufficiently thicker than the dimension X so that the wafer is not easily broken and handling is facilitated. Specifically, it is desirable that the dimension Y is at least twice as large as the dimension X, preferably at least three times as large.

  Here, as long as a heterojunction diode having a small leakage current can be formed between the silicon semiconductor regions 1 and 30a and the SiC semiconductor region 4, a polycrystalline silicon layer or a single crystal silicon layer may be used. The impurity type may be freely selected from n-type and p-type depending on the value of the forward voltage and the magnitude of the leakage current. However, since the resistance of the silicon semiconductor region 1 is added as a parasitic on-resistance to the reverse blocking switching element, it is desirable to increase the impurity concentration to reduce the resistance.

  FIG. 3 shows the semiconductor device of this example. In this embodiment, a silicon semiconductor region 31a formed for the same purpose as the silicon semiconductor region 30a of FIG. 1 is used as shown in FIG. 4 using a polycrystalline silicon layer 31 formed in the same process as the gate electrode layer 31 of the power MOSFET. It is an Example in the case of forming. Although the silicon semiconductor layer 31a and the gate electrode layer 11 use the polycrystalline silicon semiconductor layer 31 formed in the same process, the impurity type and concentration may be set separately, but both are the same type. A polycrystalline silicon layer doped with impurities at a high concentration may be used.

  FIG. 5 shows the semiconductor device of this example. In the semiconductor device of this embodiment, the silicon semiconductor region 30a is in contact with the silicon semiconductor region 1 in this embodiment. Even when the ohmic contact between the silicon semiconductor region 30a and the silicon semiconductor region 1 cannot be obtained, the two regions are connected by a depletion layer extending from the heterojunction on the second main surface side, and further from the second main surface side to the surface side, Further, when a high voltage is applied, a depletion layer is sequentially spread on the floating field rings 5e and 5d formed on the main surface side, and electric field concentration in the periphery of the heterojunction is avoided. For this reason, the high breakdown voltage of the heterojunction diode can be achieved as in the first embodiment.

  FIG. 6 shows the semiconductor device of this example. In this embodiment, the groove 20 is formed from the back surface of the semiconductor, and the silicon semiconductor region 30a of FIG. In the present embodiment, a case is shown in which there is a gap between the p-type diffusion region 5f formed on the first main surface and the silicon semiconductor region 1, but breakdown occurs when a reverse voltage is applied to the heterojunction diode. The p-type diffusion region 5f functions as a floating field ring and can increase the breakdown voltage of the heterojunction diode by setting the distance to which the depletion layer is connected. Further, even when the p-type diffusion region 5f and the silicon semiconductor region 1 are in contact with each other without the gap, the p-type diffusion regions 5f and 5e function as floating field rings. Withstand voltage can be increased. In this embodiment, there is no p-type diffusion region 5f, 5e, the groove 20 is formed shallow, and the electric field around the heterojunction diode even when the vertical dimension corresponding to the silicon semiconductor region 30a in FIG. 5 is short. Is relaxed, and is effective in increasing the breakdown voltage.

  FIG. 7 shows the semiconductor device of this example. This embodiment is an embodiment where the p-type diffusion region 5f and the silicon semiconductor region 1 are in contact with each other in the third embodiment. Also in the case of this embodiment, the depletion layer formed in the SiC region 4 region in contact with the silicon semiconductor region 1 is also connected to the p-type diffusion region 5f, and the depletion layer sequentially spreads to the floating field rings 5e and 5d. The electric field at the end of the diode is relaxed and a high breakdown voltage can be achieved.

  FIG. 8 shows a semiconductor device of this example. In the semiconductor element of this embodiment, the semiconductor wafer is diced and then back-etched, and then the silicon semiconductor region 1 is formed.

  In this case, since the silicon semiconductor region 1 is deposited on the side wall of the semiconductor chip, the same shape as in FIG. 5 is obtained. In this embodiment, the floating field ring 5f shown in FIG. 5 is formed so as to extend to the periphery of the semiconductor chip so as to ensure the withstand voltage even if the chip dicing location is slightly deviated, and is in contact with the silicon semiconductor region 1. It is.

  FIG. 9 shows a semiconductor device of this example. In the semiconductor device of the present embodiment, a SiC substrate having a p-type SiC semiconductor region 60 is used, a silicon semiconductor region 30a is formed in the groove 20 on the first main surface side, and the inside of the groove 21 on the second main surface side. A silicon semiconductor region 32a is also formed. The groove 21 on the second main surface side can also be formed at high speed by using magnetic enhanced inductively coupled plasma etching.

  In this embodiment, the on-resistance is reduced by reducing the dimension X to the minimum dimension necessary for securing the withstand voltage, for example, about several tens of μm or less if it is 10 kV or less even when the semiconductor thickness Y is kept thick. is there. In this embodiment, a deep groove 21 is formed from the second main surface, and polycrystalline silicon is deposited in the groove to form a silicon semiconductor layer 32a. Although it is difficult to form a low-resistance semiconductor region with a wide band gap semiconductor, the substrate-side resistance of the second main surface can be lowered because the low-resistance silicon semiconductor layer 32a is used in this embodiment. In addition, since the thickness Y of the semiconductor region can be made relatively thick, it becomes difficult to break and handling becomes easy. The p-type SiC semiconductor region 60 is necessary for the semiconductor device to have a reverse breakdown voltage.

  Here, although the p-type SiC semiconductor region 60 may be used as a substrate and the n-type SiC semiconductor region 4 may be formed thereon by epitaxial growth, the n-type SiC semiconductor region 4 is used as the SiC substrate, and the p-type SiC semiconductor region is used. 60 may be formed at low cost by ion implantation or a diffusion process from a diffusion source containing a high concentration of p-type impurities. Alternatively, the p-type SiC semiconductor region 60 may be an insulating layer.

  FIG. 10 shows the semiconductor device of this example. In the semiconductor device of the present embodiment, the high-concentration n-type SiC semiconductor region 3 having a sufficiently lower resistance than these two semiconductor regions is provided between the n-type SiC semiconductor region 4 and the n-type SiC semiconductor region 2. is there. Specifically, it is desirable that the resistivity is lower by one digit or more, but it is effective even when the resistivity is less than half. By providing this high-concentration n-type SiC semiconductor region 3, the size of the semiconductor region Y can be increased at the same time while suppressing an increase in on-resistance, so that the wafer is difficult to break and handling becomes easy.

  In the semiconductor device of this embodiment, the thickness X of the n-type SiC semiconductor region 4 and the thickness Z of the n-type SiC semiconductor region 4 necessary for the withstand voltage of the heterojunction diode on the second main surface side are set as much as possible to ensure the breakdown voltage of the power MOSFET. The semiconductor thickness Y was reduced to a level that does not cause a problem for handling. In this embodiment, the dimension Y is effective when it is sufficiently longer than the sum of the dimension X and the dimension Z. That is, for example, it is effective when the dimensions X and Y are about 10 to 20 μm and the dimension Y is 80 to 600 μm when the semiconductor chip is completed.

  The semiconductor layer 32b and the semiconductor layer 32c are formed at the same time as the semiconductor layer 32a by a floating field ring on the second main surface side formed so as to surround the electrode 13, but each is formed electrically separated. . The withstand voltage of the hetero diode on the second main surface may be secured by the floating field ring formed in such a groove.

  The high-concentration n-type SiC semiconductor region 3 may be made of a material other than a semiconductor, such as a metal layer, whose resistivity is one digit or more than that of the semiconductor regions 2 and 4.

  FIG. 11 shows the semiconductor device of this example. In this embodiment, the anode electrode of the heterojunction diode is also taken out from the first main surface side. In this embodiment, the trench 22 is formed so that the area of the heterojunction diode is widened and the on-resistance is lowered, and the silicon semiconductor region 33a is formed. As in the second embodiment, a polycrystalline silicon layer in which the gate electrode layer 11 and the silicon semiconductor region 33a are formed in the same process can also be used in this embodiment. This structure can be used for an integrated circuit by adding a known element isolation region.

  FIG. 12 shows a semiconductor circuit of the present invention using the semiconductor device of this embodiment. In this embodiment, the reverse blocking switching element of the present invention using a heterojunction diode is used for a current source inverter. In the current type inverter, the current smoothing reactor 140 makes the total current flowing through the inverter circuit almost constant, and this current flows through different reverse blocking switching elements depending on the on / off state of each switching element. Thereby, the electric current to load 130, such as a motor, is controlled. In this embodiment, 127, 128, and 129 are coils of a three-phase motor. When the semiconductor device of this embodiment is used, the switching element portion uses a wide bandgap semiconductor, so that a high voltage and low loss are obtained. In the heterojunction diode portion, the impurity concentration and impurity type (n-type or p-type) of the silicon semiconductor layer are obtained. By optimizing the type), it is possible to realize a diode capable of high-speed switching that has a low forward voltage and a small leakage current and does not accumulate minority carriers. For this reason, there is an effect that a current source power conversion circuit such as a current source inverter can be driven at a high frequency and loss can be reduced.

  FIG. 12 shows a semiconductor circuit of the present invention using the semiconductor device of this embodiment.

  This is a semiconductor circuit of the present invention using the semiconductor device of this example. This embodiment is a bidirectional switch using a reverse blocking switch used in a matrix converter circuit mainly used in an elevator or the like. Thus, when the reverse blocking switch of the present invention is connected in parallel in the reverse direction, a bidirectional switch can be realized. When such a bidirectional switch is used in a matrix converter circuit, a matrix converter capable of achieving high frequency and low loss can be realized for the same reason as in the tenth embodiment.

  As described above, the power semiconductor element is described as being n-type. However, in the case of a p-type power semiconductor element, a similar configuration can be realized by reversing the polarity of the circuit and the polarity of the impurity layer. Needless to say, is obtained.

  Further, although the case where SiC is used for the semiconductor region constituting the switching element has been described, other wide band gap semiconductors such as GaN and diamond or GaAs may be used. Moreover, although the case where silicon was used as the semiconductor having a small band gap constituting the heterojunction has been described, other semiconductors may be used as long as the heterojunction can be constituted.

2 is a cross-sectional view of the semiconductor device of Example 1. FIG. Sectional drawing of the manufacturing process of the semiconductor device of Example 1. FIG. Sectional drawing of a semiconductor device in Example 2. FIG. Sectional drawing of the manufacturing process of the semiconductor device of Example 2. FIG. FIG. 10 is a cross-sectional view of the semiconductor device of Example 3; Sectional drawing of the semiconductor device of Example row | line 4. FIG. FIG. 16 is a cross-sectional view of the semiconductor device in Example 5; FIG. 14 is a cross-sectional view of a semiconductor device in Example 6; FIG. 10 is a cross-sectional view of a semiconductor device in Example 7. FIG. 14 is a cross-sectional view of the semiconductor device in Example 8; FIG. 11 is a cross-sectional view of a semiconductor device in Example 9; FIG. 11 is a circuit diagram of a semiconductor device in an embodiment column 10; FIG. 16 is a circuit diagram of the semiconductor device in Example 11;

Explanation of symbols

Reference Signs List 1 Si semiconductor region 2 n-type SiC semiconductor region 3 high-concentration n-type SiC semiconductor region 4 n-type SiC semiconductor regions 5a-5e, 6a-6b, 60p-type SiC semiconductor region 8 n-type SiC semiconductor region 10 source electrode layer 11 gate Electrode layers 12, 40 Insulating layer 13 Anode electrode 15 Gate insulating layers 20, 21, 22 Grooves 30a, 31a, 32a-32c Si semiconductor regions 110, 111, 150, 152 Reverse blocking switching element 112 Ground terminal 113 High voltage terminal 118 High voltage power supply 119, 120 Power supply 123, 124, 125, 126 Switch 140 Current smoothing reactor 152, 153 Bidirectional switch terminal

Claims (16)

In a semiconductor switching element having a first junction and a second junction,
At least one region of the main current path between the first main terminal and the second main terminal of the semiconductor switching element is a wide band gap semiconductor,
The forward voltage drop of the second junction is lower than the forward voltage drop of the first junction;
The second junction is in a forward bias state when the switching element is turned on in a forward operation, and is in a current blocking state in the reverse bias state, and a depletion layer at a peripheral end of the second junction in the reverse bias state. The semiconductor switching element is characterized by comprising means extending toward the first main surface where the first junction is formed. In claim 1,
The second junction is a heterojunction, and one of the semiconductors constituting the heterojunction is a silicon semiconductor;
At least one of said 1st junction is a wide gap semiconductor, The semiconductor switching element characterized by the above-mentioned. In claim 1,
As a means for the depletion layer at the peripheral edge of the second junction to extend to the first main surface side where the first junction is formed, a silicon semiconductor region in the vicinity of the peripheral edge of the second junction and on the first main surface side A semiconductor switching element comprising: In a semiconductor layer device having a switching element on the first terminal side and a heterojunction diode element blocking reverse current on the second terminal side,
The heterojunction diode includes a first semiconductor region of a first semiconductor having a wider band gap and a second semiconductor region of a second semiconductor having a narrow band gap,
A semiconductor switching element comprising means for extending a depletion layer in a peripheral portion of the second semiconductor region of the second semiconductor along a side surface of the first semiconductor region of the first semiconductor. In a semiconductor layer device having a switching element on the first terminal side and a heterojunction diode element blocking reverse current on the second terminal side,
The heterojunction diode includes a first semiconductor region of a first semiconductor having a wider band gap and a second semiconductor region of a second semiconductor having a narrow band gap,
A semiconductor switching element comprising means for extending a depletion layer in a peripheral portion of the second semiconductor region of the second semiconductor in a direction perpendicular to the first main surface. In claim 5,
The first terminal is formed on the semiconductor first main surface side,
The second terminal is formed on the semiconductor second main surface side,
As a means for extending a depletion layer in the periphery of the second region of the second semiconductor in a direction perpendicular to the first main surface, the first main surface and the second main surface in the periphery of the second region of the second semiconductor. A semiconductor switching element, wherein a third semiconductor region of a second semiconductor is provided therebetween.   7. The third semiconductor region of the second semiconductor according to claim 6, wherein the third semiconductor region of the second semiconductor is formed in a groove formed substantially perpendicular to the first main surface in the first semiconductor region of the first semiconductor. Semiconductor switching element.   6. The depletion layer extending to the first main surface side according to claim 5, wherein a depletion layer in a peripheral portion of the second semiconductor region of the second semiconductor extends in a direction perpendicular to the first main surface. A semiconductor switching element comprising means for extending a depletion layer inward from the periphery of a semiconductor chip on the surface side. In claim 5,
As a means for extending a depletion layer in a peripheral portion of the second semiconductor region of the second semiconductor in a direction perpendicular to the first main surface, the first semiconductor region of the first semiconductor on the side surface of the first semiconductor region of the first semiconductor A fifth semiconductor region of a first semiconductor having a conductivity type opposite to that of the first semiconductor,
A semiconductor comprising a floating field ring for relaxing electric field concentration of a depletion layer extending from the second main surface and a high breakdown voltage securing region such as a field plate and a low concentration extension region on the first main surface Switch element.   9. A high breakdown voltage securing region such as a floating field ring, a field plate, or a low concentration extension region provided on the first main surface is provided as means for extending a depletion layer inward from the periphery of the semiconductor chip. A semiconductor switch element. In claim 5,
A second semiconductor region of the second semiconductor is formed in a groove provided in a second main surface;
A fourth semiconductor region of a first semiconductor having a polarity opposite to that of the first semiconductor region of the first semiconductor is provided on a second main surface side where the second semiconductor region of the second semiconductor is not formed. Semiconductor switch element. In a semiconductor layer device having a switching element on the first terminal side and a heterojunction diode element blocking reverse current on the second terminal side,
The heterojunction diode includes a first semiconductor region of a first semiconductor having a wider band gap and a second semiconductor region of a second semiconductor having a narrow band gap,
A semiconductor switching element, wherein the second semiconductor region of the second semiconductor is provided in a direction perpendicular to the first main surface.   13. The semiconductor according to claim 12, wherein the second semiconductor region of the second semiconductor is formed in a groove formed in the first semiconductor region of the first semiconductor in a direction substantially perpendicular to the first main surface. Switching element. In a semiconductor layer device having a switching element on the first terminal side and a heterojunction diode element blocking reverse current on the second terminal side,
The first terminal is provided on the first main surface, and the second terminal is provided on the second main surface. The heterojunction diode has a narrower band gap and a first semiconductor region of the first semiconductor having a wider band gap. A second semiconductor region of the second semiconductor,
It is adjacent to the first semiconductor region of the first semiconductor and is in contact with the switching element on the first terminal side through a low resistance region whose resistivity is one digit or more lower than that of the first semiconductor region of the first semiconductor. Switching element.   A current source power converter using the semiconductor switch element according to claim 1.   A bidirectional switch circuit using the semiconductor switch element according to claim 1.

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