JP2007288165A - Method for producing strain relaxation buffer layer and laminate having strain relaxation buffer layer - Google Patents

Abstract

Disclosed is a method for producing a strain relaxation buffer layer capable of suppressing the surface roughness, and a laminate including such a strain relaxation buffer layer.
Ge ions or Si ions are implanted into a surface 11 of a Si substrate 1 having a crystal structure. Thereby, lattice defects are formed in the Si substrate 1 and in the vicinity of the surface 11. Next, the SiGe layer 2 is grown on the surface 11 of the Si substrate 1. Next, the SiGe layer 2 is annealed. Thereby, the SiGe layer 2 is used as the strain relaxation buffer layer 3. Thereby, the surface roughness of the strain relaxation buffer layer 3 can be suppressed low. Further, the relaxation rate of the strain relaxation buffer layer 3 can be improved by adjusting the implantation energy and dose amount of Ge ions or Si ions implanted into the Si substrate 1.
[Selection] Figure 1

Description

  The present invention relates to a method for producing a strain relaxation buffer layer and a laminate including the strain relaxation buffer layer.

  In order to increase the mobility of electrons (carriers) in MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), strained Si / Ge heterostructures have been proposed. By increasing the mobility of electrons in the MOSFET, the operation of the MOSFET can be accelerated.

  Examples of the strained Si / Ge heterostructure include strained Si-MOSFET, strained SiGe-MOSFET, and strained Ge-MOSFET. In order to realize these structures, it is necessary to produce a relaxed SiGe buffer layer on the Si substrate. In order to realize a high mobility structure, this buffer layer needs to have a high strain relaxation rate, a small surface roughness, and good crystallinity. In addition, it is very important for the SiGe buffer layer to be thin for high speed devices.

  When the thickness of the buffer layer is large, the growth time of this layer becomes long, and the waste of the growth material is also large, so that the cost required for manufacturing becomes high. Further, when used as a MOSFET, the leakage current at the time of off increases.

  In addition, when the surface roughness of the buffer layer is large, roughness scattering occurs in the channel layer (carrier passage in the FET) formed on the buffer layer, and the mobility of the carriers is reduced.

  In order to cope with this problem, a gradient composition buffer method in which the composition of the buffer layer is gradually changed can be used. According to this, threading dislocation can be controlled, and an almost complete relaxed SiGe buffer layer can be obtained. However, in order to use the gradient composition buffer method, generally, the thickness of the buffer layer must be several μm or more. Furthermore, this method has various problems such as an increase in surface roughness and a large fluctuation of distortion due to a cross-hatch pattern generated along with relaxation.

  A low-temperature buffer method has also been proposed in which a Si layer is grown on a Si substrate at a low temperature. When this is used, a Si layer having lattice defects can be obtained, and relaxation of the SiGe layer can be promoted by growing the SiGe layer on the upper surface thereof. This method has an advantage that film thickness, surface roughness, and threading dislocation can be easily suppressed as compared with the gradient composition buffer method. However, in this method, in order to obtain a Si layer having lattice defects, the Si layer must be grown at 400 ° C. or lower. On the other hand, generally used industrial methods for forming a Si thin film are gas source MBE using a gas as a raw material and a CVD method. In these methods, when the growth temperature is low, the growth rate is lowered. For this reason, the low-temperature buffer method has a problem that it is difficult to put it to practical use in industry.

Therefore, the present inventors have proposed a method of forming a lattice defect on the Si substrate by implanting Ar ⁺ ions into the Si substrate and then forming a SiGe relaxation film (buffer layer) on the Si substrate (the following patent) Reference 1). According to this, lattice defects can be effectively formed in the Si substrate in the vicinity of the interface between the SiGe buffer layer and the Si substrate. For this reason, according to this technique, there is an advantage that a high relaxation rate can be obtained while the thickness of the SiGe buffer layer is kept small.

  However, since Ar is an inert gas, it cannot be said that the compatibility with the Si substrate subjected to ion implantation is good, and there is a concern that the crystallinity of the Si substrate may deteriorate.

In addition, H ⁺ , He ^{+ and the} like can be considered as ion species implanted into the Si substrate. However, if the ion implantation defects are not formed near the interface between the SiGe layer and the Si substrate, it is considered that the effectiveness is low. In the case of light ions such as H ⁺ and He ⁺ , in order to form defects near the interface, after growing the SiGe layer, which is a buffer layer, ions must be implanted so that the ions reach the interface from the top surface of the SiGe layer. However, this will cause the quality of the SiGe layer to deteriorate. In addition, since defects remain in the SiGe layer, the crystallinity is deteriorated.

  Therefore, the present inventors have further researched on appropriate implanted ion species, and by implanting Ge ions into the Si substrate, the surface roughness of the obtained buffer layer (SiGe layer) can be kept low. I found. It was also found that the buffer layer relaxation rate can be increased by appropriately setting the ion implantation conditions. In Patent Document 1 below, Ge is described as an option of ion species to be implanted into the substrate, but it does not disclose a specific combination using Ge ions with respect to the Si substrate, and it is realized. The conditions for this are not disclosed. Therefore, Patent Document 1 below does not describe an invention in which Ge ions are implanted into a Si substrate to form lattice defects and thereafter a SiGe strain relaxation buffer layer is obtained. Further, Patent Document 1 below does not show the effect of suppressing surface roughness by a combination of a specific substrate and a specific ion species.

Furthermore, the present inventors have found that the surface roughness of the obtained buffer layer (SiGe layer) can also be kept low by implanting Si ions into the Si substrate. In Patent Document 1 below, Si is described as an option of ion species to be implanted into the substrate, but this does not disclose a specific combination using Si ions for the Si substrate, and realize this. The conditions for this are not disclosed. Therefore, Patent Document 1 below does not describe an invention in which Si ions are implanted into a Si substrate to form lattice defects, and then a SiGe strain relaxation buffer layer is obtained. Further, Patent Document 1 below does not show the effect of suppressing surface roughness by a combination of a specific substrate and a specific ion species.
JP 2003-234289 A

  As described above, the present inventors have particularly found that Si can be selected as the substrate and Ge or Si as the implanted ion species, thereby suppressing the surface roughness in the strain relaxation buffer layer. The present invention has been made based on these findings. An object of the present invention is to provide a method for producing a strain relaxation buffer layer capable of keeping the surface roughness low, and a laminate including such a strain relaxation buffer layer.

The manufacturing method of the strain relaxation buffer layer according to the present invention includes the following steps:
(A) forming a lattice defect in the Si substrate by implanting Ge ions into the Si substrate having a crystal structure;
(B) growing a SiGe layer on the surface of the Si substrate;
(C) annealing the SiGe layer to make the SiGe layer a strain relaxation buffer layer.

  The implantation energy of the Ge ions implanted into the Si substrate is preferably in the range of 10 keV to 40 keV.

The dose amount of the Ge ions implanted into the Si substrate is preferably 5 × 10 ¹⁴ cm ⁻² or more.

The manufacturing method described above may further include the following step (d):
(D) recovering the crystallinity of the Si substrate by annealing the Si substrate after the step (a) and before the step (b).

  The laminate according to the present invention has a Si substrate and a SiGe strain relaxation buffer layer laminated on the surface of the Si substrate. A lattice defect is formed on the surface of the Si substrate by implanting Ge ions. The Si substrate and the SiGe strain relaxation buffer layer have a substantially continuous crystal structure. The strain of the SiGe strain relaxation buffer layer is relaxed.

  By laminating a strained semiconductor layer on the surface of the SiGe strain relaxation buffer layer in the laminate, the semiconductor substrate according to the present invention can be obtained.

In addition, the strain relaxation buffer layer manufacturing method may include the following steps:
(A) forming a lattice defect in the Si substrate by implanting Si ions into the Si substrate having a crystal structure;
(B) growing a SiGe layer on the surface of the Si substrate;
(C) annealing the SiGe layer to make the SiGe layer a strain relaxation buffer layer.

  Moreover, the following structures may be sufficient as the laminated body which concerns on this invention. That is, this laminated body has a Si substrate and a SiGe strain relaxation buffer layer laminated on the surface of the Si substrate. On the surface of the Si substrate, lattice defects are formed by implanting Si ions. The Si substrate and the SiGe strain relaxation buffer layer have a substantially continuous crystal structure. The strain of the SiGe strain relaxation buffer layer is relaxed.

  ADVANTAGE OF THE INVENTION According to this invention, the manufacturing method of the strain relaxation buffer layer which can suppress surface roughness low, and the laminated body provided with such a strain relaxation buffer layer can be provided. In addition, the relaxation rate of the strain relaxation buffer layer can be improved by adjusting the implantation energy or dose of Ge ions or Si ions.

(First embodiment)
Hereinafter, the manufacturing method of the strain relaxation buffer layer according to the first embodiment of the present invention will be described with reference to FIG.

  First, a Si substrate 1 having a crystal structure is prepared. The Si substrate 1 is usually a single crystal substrate of Si. However, as the Si substrate 1, it is sufficient that at least the vicinity of the surface thereof has a degree of crystallinity necessary for the growth of the SiGe layer described later. The Si substrate 1 may be doped with impurities that do not impair the crystallinity of the Si substrate.

Next, Ge ions (that is, Ge ⁺ ions) are implanted into the surface 11 of the Si substrate 1. Thereby, the lattice defect 12 can be formed in the Si substrate 1. In FIG. 1A, lattice defects are schematically illustrated with dots for easy understanding, but actual lattice defects are extremely fine and numerous. Thereafter, in the present embodiment, the substrate 1 can be annealed to recover its crystallinity (described in detail in Examples described later).

  Next, the surface 11 of the Si substrate 1 is cleaned by a method similar to the conventional method. Examples of the cleaning method include wet cleaning and thermal cleaning.

  Next, the SiGe layer 2 is grown on the surface 11 of the Si substrate 1 (see FIG. 1B). As a growth method, for example, solid source MBE or gas source MBE is suitable, but is not particularly limited. The SiGe layer 2 grows while having a crystal structure (epitaxial structure) substantially continuous with the surface of the Si substrate 1. After reaching the predetermined thickness, the growth is stopped.

  Next, the SiGe layer 2 is annealed. Thereby, the SiGe layer 2 can be made into the strain relaxation buffer layer 3 (refer FIG.1 (c)). Thereby, a laminate having the Si substrate 1 and the SiGe strain relaxation buffer layer 3 laminated on the surface of the Si substrate 1 can be obtained. Furthermore, a semiconductor substrate can also be constituted by laminating a strained semiconductor layer 4 (see FIG. 1C) on the surface of the SiGe strain relaxation buffer layer 3 in this laminate.

(Example 1)
An example of the manufacturing method in the first embodiment will be described in detail below.

(Ge ion implantation)
The conditions for Ge ion implantation into the Si substrate 1 before the growth of the SiGe buffer layer 2 were a dose of 6 × 10 ¹⁴ to 1 × 10 ¹⁵ cm ⁻² and an implantation energy of 25 to 80 keV. The surface 11 of the Si substrate 1 was a (001) plane. In the Ar ⁺ ion implantation method shown in Patent Document 1 described above, the implantation conditions with an implantation energy of 25 keV and a dose of 1 × 10 ⁻¹⁵ cm ⁻² were the optimum conditions for the relaxation of the SiGe buffer layer. Therefore, using SRIM (simulation software obtained from The Stopping and Range of Ions in Matter: http://www.srim.org/#SRIM), Ar ⁺ ions are implanted, and Ge ⁺ ions are implanted. The conditions under which the defect distributions were completely equal were estimated. Here, the defect distribution refers to the density distribution of Si atoms subjected to displacement (Recoil Si density). The result of the simulation is shown in FIG. FIG. 2A shows the results for Ge ions, and FIG. 2B shows the results for Ar ions. From this result, when Ar ⁺ ions were implanted with an implantation energy of 25 keV and a dose of 1 × 10 ¹⁵ cm ^-2 and Ge ⁺ ions were implanted with an implantation energy of 40 keV and a dose of 6 × 10 ¹⁴ cm ^-2 It can be seen that the distributions of In addition, it can be said that Si is amorphized in a region where the Recoil Si density is equal to or higher than 5 × 10 ²² cm ⁻³ , which is the atomic density of Si. Therefore, it can be seen from FIG. 2 that this dose amount promotes amorphization on the surface of the Si substrate. If the surface of the Si substrate is amorphized, hydrogen termination cannot be performed by a normal Si substrate cleaning method, which may make it difficult to produce a high-quality buffer layer. Therefore, after Ge ion implantation, heat treatment was performed in a nitrogen atmosphere at 700 ° C. for 10 minutes to restore crystallinity. As described above, by annealing the Si substrate after the Ge ion implantation and before the growth of the SiGe layer, the crystallinity of the Si substrate can be recovered, and a high-quality buffer layer can be easily manufactured.

Thereafter, the Si substrate was cleaned before being put into the chamber of the molecular beam epitaxy (MBE) apparatus. As a cleaning method, the Ishizaka-Shiraki method, the RCA cleaning method and the like are often used. In this example, the hydrogen termination method, which is said to be relatively simple and less contaminated, was used. Therefore, the cleaning process of cleaning with a mixed solution of sulfuric acid and hydrogen peroxide (H ₂ SO ₄ : H ₂ O ₂ = 2: 1) for 5 minutes and then etching with hydrofluoric acid to remove the oxide film is performed twice. went. After cleaning, the surface of the Si substrate was hydrophobic, which confirmed that it was hydrogen terminated.

  After cleaning the Si substrate, the Si substrate was carried into the MBE chamber and heat treatment was performed for cleaning. In cleaning and heat treatment, the surface of the Si substrate is slightly contaminated, and the contamination may become a defect. Therefore, after heat treatment, a 5 nm Si layer was grown on the Si substrate.

Thereafter, the SiGe layer was grown using a solid source MBE at a growth temperature of 500 ° C., a Ge composition of 20-30%, and a film thickness of 100 nm. Thereafter, the SiGe layer was annealed to promote relaxation of the strain, thereby forming a strain relaxation buffer layer (detailed annealing conditions will be described later). In this way, a strain relaxation buffer layer was obtained from the SiGe layer. Furthermore, for comparison, a sample in which Ar ⁺ ions are implanted with an implantation energy of 25 keV and a dose of 1 × 10 ¹⁵ cm ⁻² in place of Ge ⁺ ions (Comparative Example 1) and a sample in which no ion implantation is performed (Comparative Example 2) was also produced at the same time.

(Evaluation of Example 1)
(Raman spectroscopy and X-ray diffraction)
In order to obtain the relaxation rate of the obtained SiGe strain relaxation buffer layer (SiGe buffer layer), measurement was performed using a Raman spectroscopic device and an X-ray diffraction device. The SiGe buffer layer is produced as follows. First, a SiGe layer is fabricated with a growth temperature of 500 ° C., a buffer layer thickness of 100 nm, and a Ge composition of 20%. Thereafter, as described above, in order to promote relaxation, the SiGe layer was heat-treated (annealed) at 900 ° C. for 1 hour. Since the melting point of Ge exists in the vicinity of 950 ° C., the heat treatment was performed at 900 ° C. to prevent diffusion. Thereby, a SiGe buffer layer was obtained.

Fig. 3 shows the top of a Si substrate implanted with Ge ion implantation at an implantation energy of 40 keV and an implantation dose of 6 × 10 ¹⁴ cm ^-2 , and an implantation energy of 25 keV and an implantation dose of 6 × 10 ¹⁴ cm ^-2 . The Raman spectra before and after the heat treatment are shown for samples obtained by growing 100 nm of Si _0.8 Ge _0.2 having a Ge composition of 20% on the Si substrate on which Ge ion implantation was performed. FIG. 4 shows an X-ray diffraction spectrum of a sample obtained by performing ion implantation and growing a SiGe buffer layer under the same conditions.

Referring to the Raman spectrum of FIG. 3, first, the peak present at 521 cm ⁻¹ is the peak of the Si substrate, and the peak at a lower value is the peak of the SiGe buffer layer. The peak position when the SiGe buffer layer is completely relaxed exists at 508.9 cm ⁻¹ , and the peak position when completely distorted exists at 515.5 cm ⁻¹ . Looking at the spectrum before annealing, the peak of the SiGe buffer layer is present in the vicinity of 515.5 cm ⁻¹ , indicating that the film is distorted before annealing. On the other hand, looking at the spectrum after annealing, it can be seen that relaxation occurred because the peak was shifted to the lower wavenumber side than before annealing.

  Next, referring to the X-ray diffraction spectrum of FIG. 4, the peak of the SiGe buffer layer in the sample before the heat treatment is located on the low angle side, and fringes due to the film thickness are observed. This indicates that the Si substrate and the SiGe buffer layer are lattice-matched and the interface is steep. The peak position when this SiGe buffer layer is completely relaxed is 34.26 °, and the peak position when completely strained is at 34.05 °. Looking at the spectrum before annealing, it can be seen that the SiGe buffer layer is almost completely distorted because there is a peak near 34.05 °. On the other hand, after annealing, the peak of the SiGe buffer layer shifts to the high angle side, and it can be confirmed that the fringes disappear. This means that relaxation of the SiGe layer was promoted. From the above, it can be seen that the relaxation proceeds greatly by the heat treatment of the SiGe layer. Hereinafter, the sample after the heat treatment is further evaluated.

(Evaluation of surface morphology by atomic force microscope)
First, surface morphologies when Si _0.8 Ge _0.2 is grown on a substrate into which Ar ⁺ ions or Ge ⁺ ions are ion-implanted under the condition that the Ge composition is thin (Ge composition 20%) are shown in FIGS. The surface morphology of each sample was measured with an atomic force microscope (AFM). When Ar ⁺ ions are implanted at an implantation energy of 25 keV and an implantation dose of 1 × 10 ¹⁵ cm ^-2 (Comparative Example 1), the surface roughness of the strain relaxation buffer layer is RMS 0.50 nm and the relaxation rate is 75%. (FIG. 5A). On the other hand, in Ge ⁺ ion implantation, the surface morphology of the strain relaxation buffer layer of the sample obtained under the same implantation conditions (implantation energy 40 keV, implantation dose 6 × 10 ¹⁴ cm ^-2 ) with the same defect density distribution is The surface roughness RMS was 0.41 nm, and the relaxation rate was 26% (FIG. 5B).

Thus, although the defect density distribution was completely the same, the surface roughness and the relaxation rate differed greatly between Comparative Example 1 and the Example. This means that the defect structure and relaxation mechanism differ between Ar ⁺ ions and Ge ⁺ ions. Further, in this example, the relaxation rate when Ge ⁺ ion implantation was performed was 26%. This is because the alignment between the Si substrate and Ge ⁺ ions is good, and the amount of defects is reduced. Therefore, it is considered that relaxation is less likely to occur. Therefore, by increasing the Ge ⁺ ion implantation dose to 1 × 10 ¹⁵ cm ^-2 and reducing the implantation energy to 25 keV, defects were distributed near the SiGe / Si interface, making it easier to cause relaxation. As a result, a surface roughness RMS of 0.34 nm and a relaxation rate of 71% were obtained (FIG. 5C). Therefore, by increasing the implantation dose and reducing the implantation energy in this embodiment, the SiGe relaxation has a smaller surface roughness and the same relaxation rate as compared with the Ar ⁺ ion implantation sample (Comparative Example 1). A buffer substrate can be produced. In addition, a cross-hatch pattern is seen in the surface morphology of the sample (example) in Ge ⁺ ion implantation (see FIGS. 5B and 5C), but the roughness height is about 1 to 2 nm. It can be said that a very flat surface is realized which is significantly smaller than the roughness of several tens of nm seen in the cross-hatch pattern of the SiGe relaxation layer (by the gradient composition buffer method).

Next, a Si _0.73 Ge _0.27 layer was grown on a Si substrate subjected to Ar ⁺ ion implantation (Comparative Example 1) or Ge ⁺ ion implantation (Example) under a condition where the Ge composition was high (Ge composition 27%). The surface morphology at the time is shown in FIGS. First, in the case of Ar ⁺ ion implantation (Comparative Example 1), the surface roughness is RMS 0.72 nm, the relaxation rate is 83%, and the surface roughness is increased by increasing the Ge composition of the SiGe layer ( FIG. 6A). On the other hand, in the sample (Example) in which Ge ⁺ ion implantation was performed under the same implantation conditions (implantation energy 40 keV, implantation dose 6 × 10 ¹⁴ cm ^-2 ) as in the case of Ar ⁺ ion implantation, the defect density distribution The roughness was RMS 0.36 nm and the relaxation rate was 55% (FIG. 6B). In the case of the example, as seen when the Ge composition is thin, the roughness is small but the relaxation rate is low. This is also considered to indicate a difference in defect structure and relaxation mechanism between the example and the comparative example. Therefore, when the implantation dose in the example was increased and the implantation energy was lowered, the surface roughness was RMS 0.48 nm and the relaxation rate was 64% (FIG. 6C). From these results, it is possible to suppress the increase in surface roughness and obtain the same relaxation rate by the Ge ⁺ ion implantation method (Example) as compared with the case of Ar ⁺ ion implantation (Comparative Example 1). I understood that.

(Relief mechanism)
In the above description, it has been stated that the structure of defects and the mechanism of relaxation are considered to be different between Ar ⁺ ion implantation (Comparative Example 1) and Ge ⁺ ion implantation (Example). A possible conceptual diagram of each relaxation mechanism is shown in FIG.

First, in Ar ⁺ ion implantation (Comparative Example 1), due to the mismatch between the Si substrate and Ar ⁺ ions, point defects gather near the SiGe / Si interface to form voids 5 (FIG. 7). (See (a)). This generates dislocations and promotes relaxation. However, since the formation of the void 5 prevents the propagation of misfit dislocations, the cross hatch pattern is not seen and the surface becomes rough, resulting in an increase in surface roughness. On the other hand, in the case of Ge ⁺ ion implantation (Example), since the alignment between the Si substrate and Ge ⁺ ions is good, only good point defects are formed near the SiGe / Si interface without forming voids. . For this reason, the occurrence of misfit dislocations is promoted, and the generated dislocations propagate through the heterointerface, thereby increasing the strain relaxation rate and causing large roughness on the surface, and periodically arranged crosses. A hatch pattern is generated (FIG. 7B). As a result, it is considered that the surface roughness is greatly suppressed.

(Dependence of relaxation rate on injection energy)
FIG. 8 shows the relationship between the relaxation rate and the implantation energy in the strain relaxation buffer layer obtained in the above-described embodiment. Here, the dose amount of implanted Ge ions was set to 6 × 10 ¹⁴ cm ⁻² , and the implantation energy was changed between 0 to 50 keV. The relaxation rate of the SiGe layer before annealing is indicated by a black square, and the relaxation rate of the strain relaxation buffer layer obtained after annealing is indicated by a black circle. The data at 0 keV in FIG. 8 is the data in Comparative Example 1.

  In the result of FIG. 8, the relaxation rate is the highest when the implantation energy is about 25 keV, and the relaxation rate is decreased when the implantation energy is higher than that. This is considered to be caused by the fact that when high energy implantation is performed, defects caused by ion implantation are distributed at positions deeper than the surface and are not likely to be dislocation sources. Further, it can be seen from the results of FIG. 8 that the relaxation rate can be improved by setting the implantation energy of Ge ions implanted into the Si substrate 1 in the range of 10 keV to 40 keV. Further, when the implantation energy is less than 10 keV, there are the following disadvantages. In other words, during cleaning of the substrate after implantation, the surface of the Si substrate is etched by cleaning chemicals, and the surface portion disappears by about several nm. For this reason, if the implantation energy is too low and the defect depth becomes shallow, defects introduced by ion implantation may be lost by cleaning. On the other hand, when Ge ions are implanted into the Si substrate, by setting the implantation energy to 10 keV, defects can be formed at a depth that does not disappear by normal cleaning (for example, a depth of 5 nm or more).

(Dependence of relaxation rate on implantation dose)
Next, FIG. 9 shows the relationship between the relaxation rate and the implantation dose in the respective strain relaxation buffer layers obtained in the above-described Example and Comparative Example 1. Here, the implantation energy of the implanted ion species (Ar or Ge) was 25 keV, and the dose was varied between 0 and 1 × 10 ¹⁵ cm ⁻² . As described above, the ion species in the examples is Ge ⁺ , and the ion species in Comparative Example 1 is Ar ⁺ . The relaxation rate of the SiGe layer before annealing (Comparative Example 1) is a white circle, the relaxation rate of the strain relaxation buffer layer after annealing is a black circle, the relaxation rate of the SiGe layer (Example) before annealing is a white triangle, and the strain relaxation after annealing The relaxation rate of the buffer layer is indicated by a black triangle. The data at the dose amount 0 in FIG. 9 is the data in Comparative Example 1.

According to the result of FIG. 9, in the example, the relaxation rate increases with an increase in the implantation dose. Here, a relaxation rate exceeding 70% was obtained at a dose of 1 × 10 ¹⁵ cm ⁻² . This relaxation rate is equal to the sample of Ar ion implantation which is a comparative example. From this, it can be seen that according to the method of the embodiment, a high relaxation rate can be achieved while suppressing an increase in surface roughness. Furthermore, according to this result, it is considered that the relaxation rate can be increased by increasing the dose amount in the example. That is, it can be seen that a high relaxation rate can be obtained by setting the dose amount of Ge ions implanted into the Si substrate 1 to 5 × 10 ¹⁴ cm ⁻² or more. Further, considering the results of FIG. 8 in combination, in order to obtain a high relaxation rate, the dose of Ge ions is set in the above range, and the implantation energy is set in the range of 15 keV to 40 keV. preferable.

(Second Embodiment)
Next, a method for manufacturing a strain relaxation buffer layer according to the second embodiment of the present invention will be described with reference to FIGS. In the description of this embodiment, the same reference numerals are used for the elements common to the first embodiment, thereby simplifying the description.

  In this embodiment, as shown in FIG. 10, Si ions are used instead of Ge ions. The outline of the manufacturing method is the same as that of the first embodiment. However, the optimum conditions obtained are slightly different from those in the first embodiment, as shown in the data of the following examples.

(Example 2)
An example of the manufacturing method in the second embodiment will be described in detail below.

First, Si ions were implanted into the Si substrate 1 to generate lattice defects. Thereafter, the SiGe buffer layer 2 was grown on the Si substrate 1 at a growth temperature of 500 ° C., a Ge composition of 20%, and a film thickness of 100 nm. FIG. 11 shows X-ray diffraction spectra before and after heat treatment for a sample subjected to Si ion implantation at an implantation energy of 25 keV and a dose amount of 5 × 10 ¹⁴ cm ⁻² and a sample not subjected to ion implantation. Sample preparation conditions other than those described above may be basically the same as those in Example 1 unless otherwise specified. In this graph, in order from the top, (1) without ion implantation and before annealing, (2) without ion implantation and after annealing, (3) with ion implantation and before annealing, (4) with ion implantation and It shows after annealing.

  In the sample before annealing, a fringe corresponding to the film thickness of the SiGe layer, showing the steepness of the Si / SiGe interface, is seen regardless of whether or not ion implantation is performed. It can be seen that the SiGe buffer layer 2 and the Si substrate 1 are lattice-matched, and no relaxation occurs during growth. It can be seen that the subsequent heat treatment shifts the SiGe peak to the high angle side, and the fringe disappears due to misfit dislocations, which promotes relaxation. By this annealing, the peak of the sample with Si ion implantation is shifted to a higher angle side and the relaxation rate increases to 75% compared to the relaxation rate of the sample without ion implantation being 20%. Was. The reason is that defects due to ion implantation functioned as a dislocation source by annealing, and as a result, contributed to an increase in the relaxation rate of the SiGe layer.

(Optimization of Si ion implantation conditions)
Next, the optimization of Si ion implantation conditions is studied. FIG. 12A shows the dependence of the relaxation rate on the implantation dose after the heat treatment. Here, the implantation energy is 20 keV. In 1.3 × 10 ¹⁵ cm ^-2 , which is the condition with the same defect distribution as the optimum Ar ion implantation condition, relaxation is hardly promoted, but when the dose is increased to 3 × 10 ¹⁵ cm ^-2 , A relaxation rate of 60% or more is obtained. It is considered that the increase in implantation dose increases the amount of defects serving as a dislocation source and improves the relaxation rate.

FIG. 12B shows the result when the implantation energy is 25 keV. As in the case of 20 keV, increasing the dose amount increases the relaxation rate, while 5 × 10 ¹⁴ cm ^{-2 where} the dose amount is small has the largest relaxation rate.

In the case of Si ions, it is considered that the crystal recoverability is stronger than other ion species, and if the dose is large, the defects disappear, and the effect of improving the relaxation rate is reduced. Actually, it is known that a region made amorphous by Si ion implantation is easy to recover from crystals, and defects mainly remain in the outer region (region having a low implantation density). In the case of Si ions, the optimum ion dose is considered to be 1 to 10 × 10 ¹⁴ cm ⁻² .

(Evaluation of surface morphology)
Subsequently, the surface morphology of the SiGe buffer layer 2 produced by the Si ion implantation method was evaluated. FIG. 13 shows an AFM image of the SiGe buffer layer 2 before the heat treatment. In this buffer layer 2, steps such as cross hatching due to misfit dislocation are not observed, and flatness of A (Angstrom) order is maintained. In this embodiment, since the growth temperature of the SiGe buffer layer 2 is set to a relatively low value of 500 ° C., increase in surface roughness due to elastic relaxation and occurrence of dislocations is suppressed.

  After the heat treatment of the SiGe buffer layer 2 (FIG. 14), the surface roughness is 0.18 nm and the surface flatness comparable to the Si substrate 1 is maintained while having a relaxation rate of 70% or more. This is considered to be due to the effect of implanting Si ions with better matching to the Si substrate 1. In FIG. 14, as the surface morphology, a uniform cross-hatch pattern is seen on the sample surface. This suggests that misfit dislocations are generated very uniformly at the interface due to the effect of ion implantation defects. Yes.

In order to measure the strain field of the SiGe buffer layer 2, spatially resolved Raman mapping was performed. FIG. 15 shows a Raman mapping image after the heat treatment in the sample of this example manufactured by using the Si ion implantation method. Similarly, FIG. 16 shows a Raman mapping image after heat treatment for a sample manufactured without performing ion implantation. In any case, the measurement range is 20 × 20 μm ² , and the scale of Raman shift is 1.0 cm ⁻¹ . The Raman shift of the peak in the SiGe buffer layer 2 shifts to the lower wavenumber side as the relaxation rate is higher, indicating that the relaxation rate is higher as the contrast is higher. It can be seen that the sample subjected to ion implantation does not show the cross-hatch pattern-like strain fluctuations seen in the sample prepared without ion implantation, and the strain relaxation is uniformly distributed in the plane. This indicates that due to lattice defects caused by Si ion implantation, dislocations are uniformly generated in the plane to cause strain relaxation.

  In addition, the manufacturing method of the strain relaxation buffer layer which concerns on this invention, and the laminated body provided with the strain relaxation buffer layer are not limited to above-described embodiment. The configuration of the present embodiment can be variously modified within the scope of the invention described in the claims.

It is explanatory drawing for demonstrating the manufacturing method of the distortion relaxation buffer layer which concerns on 1st Embodiment of this invention. It is a graph which shows the relationship between defect distribution (vertical axis) and depth (horizontal axis) when ion species are implanted into a Si substrate. 2A shows a simulation result when Ge ions are implanted at an implantation energy of 40 ekV and a dose amount of 6 × 10 ¹⁴ cm ⁻² , and FIG. 2B shows an Ar ion implantation energy of 25 ekV and a dose amount of 1 The simulation result when injecting at × 10 ¹⁵ cm ^-2 is shown. Ge ion implantation was performed on a Si substrate on which Ge ion implantation was performed under conditions of an implantation energy of 40 keV and an implantation dose of 6 × 10 ¹⁴ cm ⁻² , and an implantation energy of 25 keV and an implantation dose of 6 × 10 ¹⁴ cm ^−2. 3 is a graph showing Raman spectra before and after heat treatment in a sample obtained by growing 100 nm of Si _0.8 Ge _0.2 having a Ge composition of 20% on a performed Si substrate. The vertical axis of this graph is intensity (arbitrary unit), and the horizontal axis is Raman shift (cm ^-2 ). FIG. 4 is a graph showing an X-ray diffraction spectrum of a sample in which ion implantation and growth of a SiGe buffer layer are performed under the same conditions as in FIG. ). The surface morphology of the strain relaxation buffer layer (composition: Si _0.8 Ge _0.2 ) is shown when Ar ⁺ ions are implanted into a Si substrate with an implantation energy of 25 keV and an implantation dose of 1 × 10 ¹⁵ cm ^-2 (Comparative Example 1). FIG. Shows the surface morphology of the strain relaxation buffer layer (composition: Si _0.8 Ge _0.2 ) when Ge ⁺ ions are implanted into a Si substrate with an implantation energy of 40 keV and an implantation dose of 6 × 10 ¹⁴ cm ^-2 (Example). FIG. Diagram showing the surface morphology of a strain relaxation buffer layer (composition: Si _0.8 Ge _0.2 ) when Ge ⁺ ions are implanted into a Si substrate with an implantation energy of 25 keV and an implantation dose of 1 × 10 ¹⁵ cm ^-2 (Example). It is. The surface morphology of the strain relaxation buffer layer (composition: Si _0.73 Ge _0.27 ) when Ar ⁺ ions are implanted into a Si substrate with an implantation energy of 25 keV and an implantation dose of 1 × 10 ¹⁵ cm ^-2 (Comparative Example 1). FIG. Shows the surface morphology of the strain relaxation buffer layer (composition: Si _0.73 Ge _0.27 ) when Ge ⁺ ions are implanted into a Si substrate with an implantation energy of 40 keV and an implantation dose of 6 × 10 ¹⁴ cm ^-2 (Example). FIG. Diagram showing the surface morphology of a strain relaxation buffer layer (composition: Si _0.73 Ge _0.27 ) when Ge ⁺ ions are implanted into a Si substrate at an implantation energy of 25 keV and an implantation dose of 1 × 10 ¹⁵ cm ^-2 (Example). It is. It is a conceptual diagram about the mechanism of relaxation of a SiGe layer. FIG. 7A shows a void formation state in the vicinity of the SiGe / Si interface in the case of Ar ⁺ ion implantation (Comparative Example 1). FIG. 7B shows a good point defect formation state in the vicinity of the SiGe / Si interface in the case of Ge ⁺ ion implantation (Example). It is a graph which shows the relationship between the relaxation rate in a SiGe layer, and the implantation energy of ion seed | species, Comprising: A vertical axis | shaft is relaxation rate (%) and a horizontal axis is implantation energy (keV). It is a graph which shows the relationship between the relaxation rate in a SiGe layer, and the implantation dose amount of an ion seed | species, Comprising: A vertical axis | shaft is a relaxation rate (%) and a horizontal axis | shaft is a dose amount (* 10 ^{< 15} > cm ^<-2> ). It is explanatory drawing for demonstrating the manufacturing method of the distortion relaxation buffer layer which concerns on 2nd Embodiment of this invention. It is a graph which shows the X-ray-diffraction spectrum in the (004) plane before and behind heat processing in the SiGe buffer layer concerning 2nd Embodiment. The vertical axis of this graph is the logarithmic intensity (arbitrary unit), and the horizontal axis is the angle (°). It is a graph which shows the Si ion implantation dose dependence of the relaxation rate in the SiGe buffer layer concerning a 2nd embodiment. The figure (a) shows the case where the implantation energy of Si ions is 20 keV, and the figure (b) shows the case where the implantation energy is 25 keV. In these graphs, the vertical axis represents the relaxation rate (%), and the horizontal axis represents the dose of Si ions. It is the AFM image before heat processing in the SiGe buffer layer concerning a 2nd embodiment. It is the AFM image after heat processing in the SiGe buffer layer concerning a 2nd embodiment. It is a Raman mapping image in the SiGe buffer layer which concerns on 2nd Embodiment, Comprising: It is a thing at the time of producing | generating a SiGe buffer layer after performing Si ion implantation to a board | substrate. It is a Raman mapping image in the SiGe buffer layer as a comparative example, and is a case where the SiGe buffer layer is generated without performing Si ion implantation on the substrate.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Si substrate 11 Si substrate surface 12 Lattice defect 2 SiGe layer 3 Strain relaxation buffer layer 4 Strain semiconductor layer 5 Void

Claims (8)

A method for producing a strain relaxation buffer layer comprising the following steps:
(A) forming a lattice defect in the Si substrate by implanting Ge ions into the Si substrate having a crystal structure;
(B) growing a SiGe layer on the surface of the Si substrate;
(C) annealing the SiGe layer to make the SiGe layer a strain relaxation buffer layer.   The manufacturing method according to claim 1, wherein an implantation energy of the Ge ions implanted into the Si substrate is in a range of 10 keV to 40 keV. The manufacturing method according to claim 1, wherein a dose amount of the Ge ions implanted into the Si substrate is 5 × 10 ¹⁴ cm ⁻² or more. The manufacturing method according to any one of claims 1 to 3, further comprising the following step (d):
(D) recovering the crystallinity of the Si substrate by annealing the Si substrate after the step (a) and before the step (b).   A Si substrate and a SiGe strain relaxation buffer layer laminated on the surface of the Si substrate, and lattice defects are formed on the surface of the Si substrate by implanting Ge ions. The SiGe strain relaxation buffer layer has a substantially continuous crystal structure, and the SiGe strain relaxation buffer layer has a relaxed strain.   6. A semiconductor substrate, wherein a strained semiconductor layer is laminated on the surface of the SiGe strain relaxation buffer layer in the laminate according to claim 5. A method for producing a strain relaxation buffer layer comprising the following steps:
(A) forming a lattice defect in the Si substrate by implanting Si ions into the Si substrate having a crystal structure;
(B) growing a SiGe layer on the surface of the Si substrate;
(C) annealing the SiGe layer to make the SiGe layer a strain relaxation buffer layer.   A Si substrate and a SiGe strain relaxation buffer layer laminated on the surface of the Si substrate, and lattice defects are formed on the surface of the Si substrate by implantation of Si ions; The SiGe strain relaxation buffer layer has a substantially continuous crystal structure, and the SiGe strain relaxation buffer layer has a relaxed strain.