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JP2007288038A - Semiconductor device - Google Patents

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JP2007288038A
JP2007288038A JP2006115421A JP2006115421A JP2007288038A JP 2007288038 A JP2007288038 A JP 2007288038A JP 2006115421 A JP2006115421 A JP 2006115421A JP 2006115421 A JP2006115421 A JP 2006115421A JP 2007288038 A JP2007288038 A JP 2007288038A
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wiring
insulating film
dummy
columnar electrode
semiconductor device
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Yoshitaka Aoki
由隆 青木
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Casio Computer Co Ltd
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Casio Computer Co Ltd
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Abstract

【課題】 シリコン基板の上面中央部に設けられた高周波集積回路上の上層絶縁膜の上面を高周波集積回路とのクロストークを避けるための配線形成禁止領域とした半導体装置において、実装時の接合力が不足しないようにする。
【解決手段】 上層絶縁膜５の上面の配線形成禁止領域７の周囲には配線９が設けられている。配線９の接続パッド部上面には柱状電極１０が設けられている。配線９を含む上層絶縁膜５の上面には封止膜１１が設けられている。封止膜１１上において配線形成禁止領域７の周囲には半田ボール１４が表面処理層１２を介して柱状電極１０の上面に接続されて設けられている。封止膜１１上において配線形成禁止領域７内にはダミー表面処理層１３およびダミー半田ボール１５が設けられている。そして、ダミー半田ボール１５の存在により実装時の接合力が不足しないようにすることができる。
【選択図】 図１PROBLEM TO BE SOLVED: To provide a bonding force at the time of mounting in a semiconductor device in which an upper surface of an upper insulating film on a high frequency integrated circuit provided in a central portion of the upper surface of a silicon substrate is a wiring formation prohibited region for avoiding crosstalk with the high frequency integrated circuit Do not run out.
A wiring 9 is provided around a wiring formation prohibition region 7 on the upper surface of an upper insulating film 5. A columnar electrode 10 is provided on the upper surface of the connection pad portion of the wiring 9. A sealing film 11 is provided on the upper surface of the upper insulating film 5 including the wiring 9. On the sealing film 11, a solder ball 14 is provided around the wiring formation prohibition region 7 so as to be connected to the upper surface of the columnar electrode 10 through the surface treatment layer 12. A dummy surface treatment layer 13 and dummy solder balls 15 are provided in the wiring formation prohibition region 7 on the sealing film 11. The presence of the dummy solder ball 15 can prevent the bonding force at the time of mounting from being insufficient.
[Selection] Figure 1

Description

この発明は半導体装置に関する。   The present invention relates to a semiconductor device.

従来の半導体装置には、半導体基板の上面中央部に所定の機能の集積回路が設けられ、半導体基板の上面周辺部に複数の接続パッドが集積回路に接続されて設けられ、半導体基板の上面に絶縁膜が設けられ、絶縁膜の上面に配線が接続パッドに接続されて設けられ、配線の接続パッド部上面に柱状電極が設けられたものがある（例えば、特許文献１参照）。この場合、複数の柱状電極は半導体基板上の全面にマトリクス状に配置されている（特許文献１の図２参照）。   In the conventional semiconductor device, an integrated circuit having a predetermined function is provided at the center of the upper surface of the semiconductor substrate, and a plurality of connection pads are provided connected to the integrated circuit at the periphery of the upper surface of the semiconductor substrate. In some cases, an insulating film is provided, a wiring is provided on the upper surface of the insulating film so as to be connected to a connection pad, and a columnar electrode is provided on the upper surface of the connection pad portion of the wiring (for example, see Patent Document 1). In this case, the plurality of columnar electrodes are arranged in a matrix on the entire surface of the semiconductor substrate (see FIG. 2 of Patent Document 1).

特開平５−２１８０４２号公報Japanese Patent Laid-Open No. 5-218042

ところで、上記のような半導体装置を、例えばブルートゥースの送受信信号回路を内蔵し、携帯電話等の電子機器に組み込んで、高周波用として使用する場合には、半導体基板の上面中央部に設けられた高周波集積回路上の絶縁膜の上面を高周波集積回路とのクロストークを避けるための配線形成禁止領域とし、この配線形成禁止領域の周囲における絶縁膜の上面に配線および柱状電極を設けることになる。しかしながら、このようにした場合には、半導体装置を配線形成禁止領域の周囲のみに設けられた柱状電極を介して回路基板上に実装すると、実装時の接合力が不足し、実装上の信頼性が低下するという問題がある。   By the way, when the semiconductor device as described above has a built-in Bluetooth transmission / reception signal circuit, is incorporated in an electronic device such as a cellular phone, and is used for high frequency, the high frequency provided at the center of the upper surface of the semiconductor substrate is used. The upper surface of the insulating film on the integrated circuit is used as a wiring formation prohibition region for avoiding crosstalk with the high-frequency integrated circuit, and wiring and columnar electrodes are provided on the upper surface of the insulating film around the wiring formation prohibition region. However, in this case, if the semiconductor device is mounted on the circuit board via the columnar electrodes provided only around the wiring formation prohibition region, the bonding force at the time of mounting is insufficient, and the mounting reliability is reduced. There is a problem that decreases.

そこで、この発明は、実装時の接合力が不足しないようにすることができる半導体装置を提供することを目的とする。   SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device capable of preventing a bonding force from being insufficient at the time of mounting.

上記目的を達成するため、請求項１に記載の発明は、上面周辺部に複数の接続パッドが設けられた半導体基板と、前記半導体基板の上面に設けられた絶縁膜と、前記絶縁膜の上面周辺部に前記接続パッドに接続されて設けられた配線と、前記配線の接続パッド部上面に設けられた柱状電極と、前記配線を含む前記絶縁膜の上面に上面が前記柱状電極の上面と面一となるように設けられた封止膜と、前記柱状電極の上面に設けられた半田層と、前記封止膜の上面中央部に設けられたダミー半田層とを備えていることを特徴とするものである。
請求項５に記載の発明は、上面周辺部に複数の接続パッドが設けられた半導体基板と、前記半導体基板の上面に設けられ、上面中央部を配線非形成領域とされた第１の絶縁膜と、前記第１の絶縁膜の上面周辺部に前記接続パッドに接続されて設けられた第１の配線と、前記第１の配線を含む前記第１の絶縁膜の上面に設けられた第２の絶縁膜と、前記第２の絶縁膜の上面全体に前記第１の配線の接続パッド部に接続されて設けられた第２の配線と、前記第２の配線の接続パッド部上面に設けられた柱状電極と、前記第２の配線を含む前記第２の絶縁膜の上面に上面が前記柱状電極の上面と面一となるように設けられた封止膜と、前記柱状電極の上面に設けられた半田層とを備えていることを特徴とするものである。 In order to achieve the above object, the invention according to claim 1 is a semiconductor substrate in which a plurality of connection pads are provided on the periphery of the upper surface, an insulating film provided on the upper surface of the semiconductor substrate, and an upper surface of the insulating film. A wiring provided in the peripheral portion connected to the connection pad, a columnar electrode provided on the upper surface of the connection pad portion of the wiring, and an upper surface on the upper surface of the insulating film including the wiring is an upper surface of the columnar electrode A sealing film provided to be uniform, a solder layer provided on an upper surface of the columnar electrode, and a dummy solder layer provided on a central portion of the upper surface of the sealing film, To do.
According to a fifth aspect of the present invention, there is provided a semiconductor substrate having a plurality of connection pads provided on the periphery of the upper surface, and a first insulating film provided on the upper surface of the semiconductor substrate and having a central portion on the upper surface as a wiring non-forming region A first wiring connected to the connection pad on the periphery of the upper surface of the first insulating film, and a second wiring provided on the upper surface of the first insulating film including the first wiring An insulating film, a second wiring provided on the entire upper surface of the second insulating film connected to the connection pad portion of the first wiring, and an upper surface of the connection pad portion of the second wiring. A columnar electrode, a sealing film provided on an upper surface of the second insulating film including the second wiring so that an upper surface thereof is flush with an upper surface of the columnar electrode, and an upper surface of the columnar electrode. And a solder layer formed thereon.

請求項１に記載の発明によれば、封止膜の上面周辺部に半田層を柱状電極の上面に接続させて設け、封止膜の上面中央部にダミー半田層を設けているので、ダミー半田層の存在により実装時の接合力が不足しないようにすることができ、ひいては実装上の信頼性を向上することができる。
請求項５に記載の発明によれば、第１の絶縁膜の上面中央部が配線非形成領域であっても、その上に設けられた第２の絶縁膜の上面全体を配線形成可能領域とし、第２の絶縁膜の上面全体に設けられた第２の配線の接続パッド部上面に柱状電極を設け、柱状電極の上面に半田層を設けているので、実装時の接合力が不足しないようにすることができ、ひいては実装上の信頼性を向上することができる。 According to the first aspect of the present invention, the solder layer is provided on the periphery of the upper surface of the sealing film so as to be connected to the upper surface of the columnar electrode, and the dummy solder layer is provided at the center of the upper surface of the sealing film. Due to the presence of the solder layer, it is possible to prevent the bonding force at the time of mounting from being insufficient, and as a result, the mounting reliability can be improved.
According to the fifth aspect of the present invention, even if the central portion of the upper surface of the first insulating film is a non-wiring region, the entire upper surface of the second insulating film provided thereon is defined as a wiring-formable region. Since the columnar electrode is provided on the upper surface of the connection pad portion of the second wiring provided on the entire upper surface of the second insulating film and the solder layer is provided on the upper surface of the columnar electrode, the bonding force at the time of mounting is not insufficient. As a result, the mounting reliability can be improved.

（第１実施形態）
図１（Ａ）はこの発明の第１実施形態としての半導体装置の平面図を示し、図１（Ｂ）は図１（Ａ）のＢ−Ｂ線に沿う断面図を示す。この半導体装置は、一般的にはＣＳＰ(chip size package)と呼ばれるものであり、例えばブルートゥースの送受信信号回路を内蔵し、携帯電話等の電子機器に組み込まれるものである。 (First embodiment)
FIG. 1A is a plan view of a semiconductor device as a first embodiment of the present invention, and FIG. 1B is a cross-sectional view taken along line BB in FIG. This semiconductor device is generally called a CSP (chip size package). For example, the semiconductor device incorporates a Bluetooth transmission / reception signal circuit and is incorporated in an electronic device such as a mobile phone.

この半導体装置は平面正方形状のシリコン基板（半導体基板）１を備えている。シリコン基板１の上面中央部の図１（Ａ）において点線で囲まれた領域（図１（Ｂ）において矢印で示す領域）には所定の機能の高周波集積回路（図示せず）が設けられ、上面周辺部にはアルミニウム系金属等からなる複数の接続パッド２が高周波集積回路に接続されて設けられている。接続パッド２の中央部を除くシリコン基板１の上面には酸化シリコン等からなる絶縁膜３が設けられ、接続パッド２の中央部は絶縁膜３に設けられた開口部４を介して露出されている。   This semiconductor device includes a silicon substrate (semiconductor substrate) 1 having a planar square shape. A high-frequency integrated circuit (not shown) having a predetermined function is provided in a region surrounded by a dotted line in FIG. 1A in the center of the upper surface of the silicon substrate 1 (a region indicated by an arrow in FIG. 1B). A plurality of connection pads 2 made of aluminum-based metal or the like are connected to the high-frequency integrated circuit around the upper surface. An insulating film 3 made of silicon oxide or the like is provided on the upper surface of the silicon substrate 1 excluding the central portion of the connection pad 2, and the central portion of the connection pad 2 is exposed through an opening 4 provided in the insulating film 3. Yes.

絶縁膜３の上面にはポリイミド系樹脂、エポキシ系樹脂、ベンゾシクロブテン（ＢＣＢ）等からなる上層絶縁膜５が設けられている。絶縁膜３の開口部４に対応する部分における上層絶縁膜５には開口部６が設けられている。ここで、シリコン基板１の上面中央部に設けられた高周波集積回路上の上層絶縁膜７の上面、つまり図１（Ａ）において点線で囲まれた領域（図１（Ｂ）において矢印で示す領域）は、高周波集積回路とのクロストークを避けるための配線形成禁止領域（配線非形成領域）７となっている。   An upper insulating film 5 made of polyimide resin, epoxy resin, benzocyclobutene (BCB) or the like is provided on the upper surface of the insulating film 3. An opening 6 is provided in the upper insulating film 5 in a portion corresponding to the opening 4 of the insulating film 3. Here, the upper surface of the upper insulating film 7 on the high-frequency integrated circuit provided at the center of the upper surface of the silicon substrate 1, that is, the region surrounded by the dotted line in FIG. 1A (the region indicated by the arrow in FIG. 1B) ) Is a wiring formation prohibition region (wiring non-forming region) 7 for avoiding crosstalk with the high-frequency integrated circuit.

上層絶縁膜５の上面には銅等からなる下地金属層８が設けられている。下地金属層８の上面全体には銅からなる配線９が設けられている。下地金属層８を含む配線９の一端部は、絶縁膜３および上層絶縁膜５の開口部４、６を介して接続パッド２に接続されている。この場合、下地金属層８を含む配線９は、配線形成禁止領域７の周囲における絶縁膜５の上面に設けられている。配線９の接続パッド部上面には銅からなる柱状電極１０が設けられている。配線９を含む上層絶縁膜５の上面にはエポキシ系樹脂、ポリイミド系樹脂等からなる封止膜１１がその上面が柱状電極１０の上面と面一となるように設けられている。   A base metal layer 8 made of copper or the like is provided on the upper surface of the upper insulating film 5. A wiring 9 made of copper is provided on the entire upper surface of the base metal layer 8. One end of the wiring 9 including the base metal layer 8 is connected to the connection pad 2 through the openings 4 and 6 of the insulating film 3 and the upper insulating film 5. In this case, the wiring 9 including the base metal layer 8 is provided on the upper surface of the insulating film 5 around the wiring formation prohibition region 7. A columnar electrode 10 made of copper is provided on the upper surface of the connection pad portion of the wiring 9. A sealing film 11 made of epoxy resin, polyimide resin, or the like is provided on the upper surface of the upper insulating film 5 including the wiring 9 so that the upper surface is flush with the upper surface of the columnar electrode 10.

柱状電極１０の上面にはチタン／銅等からなる酸化防止用の表面処理層１２が設けられている。配線形成禁止領域７に対応する部分における封止膜１１の上面中央部にはダミー表面処理層１３が設けられている。表面処理層１２およびダミー表面処理層１３は、メタルマスクを用いたスパッタ、無電解メッキ等により形成されている。表面処理層１２上には半田ボール（半田層）１４が設けられている。ダミー表面処理層１３上にはダミー半田ボール（ダミー半田層）１５が設けられている。   An anti-oxidation surface treatment layer 12 made of titanium / copper or the like is provided on the upper surface of the columnar electrode 10. A dummy surface treatment layer 13 is provided at the center of the upper surface of the sealing film 11 in a portion corresponding to the wiring formation prohibition region 7. The surface treatment layer 12 and the dummy surface treatment layer 13 are formed by sputtering using a metal mask, electroless plating, or the like. A solder ball (solder layer) 14 is provided on the surface treatment layer 12. A dummy solder ball (dummy solder layer) 15 is provided on the dummy surface treatment layer 13.

ここで、図１（Ａ）に示すように、複数の半田ボール１４は封止膜１１の上面周辺部つまり配線形成禁止領域７の周囲に対応する部分に設けられ、複数のダミー半田ボール１５は封止膜１１の上面中央部つまり配線形成禁止領域７に対応する部分に設けられている。これにより、複数の半田ボール１４および複数のダミー半田ボール１５は封止膜１１上の全面にマトリクス状に配置されている。   Here, as shown in FIG. 1A, the plurality of solder balls 14 are provided in the periphery of the upper surface of the sealing film 11, that is, the portion corresponding to the periphery of the wiring formation prohibition region 7, and the plurality of dummy solder balls 15 are The seal film 11 is provided at the center of the upper surface, that is, at the portion corresponding to the wiring formation prohibition region 7. Thus, the plurality of solder balls 14 and the plurality of dummy solder balls 15 are arranged in a matrix on the entire surface of the sealing film 11.

そして、封止膜１１の上面中央部に設けられた複数のダミー半田ボール１５は、この半導体装置を回路基板（図示せず）上に実装する際に、封止膜１１の上面周辺部に設けられた半田ボール１４のみでは実装時の接合力が不足するため、これを回避して接合力を補強するためのものである。したがって、ダミー半田ボール１５の存在により実装時の接合力が不足しないようにすることができ、ひいては実装上の信頼性を向上することができる。   A plurality of dummy solder balls 15 provided at the center of the upper surface of the sealing film 11 are provided at the periphery of the upper surface of the sealing film 11 when the semiconductor device is mounted on a circuit board (not shown). The solder ball 14 alone is insufficient for the bonding force at the time of mounting, and this is for avoiding this and reinforcing the bonding force. Therefore, the presence of the dummy solder balls 15 can prevent the bonding force at the time of mounting from being insufficient, and as a result, the mounting reliability can be improved.

（第２実施形態）
図２（Ａ）はこの発明の第２実施形態としての半導体装置の平面図を示し、図２（Ｂ）は図２（Ａ）のＢ−Ｂ線に沿う断面図を示す。この半導体装置において、図１（Ａ）、（Ｂ）に示す半導体装置と異なる点は、上層絶縁膜５の上面中央部の配線形成禁止領域７にダミー下地金属層１６を含むダミー配線１７を設け、ダミー配線１７の上面にダミー柱状電極１８を設け、ダミー柱状電極１８の上面にダミー表面処理層１３を介してダミー半田ボール１５を設けた点である。 (Second Embodiment)
2A is a plan view of a semiconductor device as a second embodiment of the present invention, and FIG. 2B is a cross-sectional view taken along line BB in FIG. 2A. This semiconductor device is different from the semiconductor device shown in FIGS. 1A and 1B in that a dummy wiring 17 including a dummy base metal layer 16 is provided in the wiring formation prohibition region 7 at the center of the upper surface of the upper insulating film 5. The dummy columnar electrode 18 is provided on the upper surface of the dummy wiring 17, and the dummy solder ball 15 is provided on the upper surface of the dummy columnar electrode 18 via the dummy surface treatment layer 13.

この場合、ダミー下地金属層１６を含むダミー配線１７は平面円形状の接続パッド部のみからなり、絶縁膜３および上層絶縁膜５にはダミー下地金属層１６に対応する開口部は形成されておらず、電気的にはシリコン基板１の高周波集積回路には接続されていない。したがって、上層絶縁膜５の上面中央部の配線形成禁止領域７にダミー下地金属層１６を含むダミー配線１７を設けても、ダミー配線１７とシリコン基板１の上面中央部に設けられた高周波集積回路との間でクロストークが発生することはない。この場合、ダミー下地金属層１６を含むダミー配線１７は、相互には接続されていないことが望ましいが、支障がなければ、適宜、隣接のものと接続されるように一体的にパターン形成してもよい。   In this case, the dummy wiring 17 including the dummy base metal layer 16 includes only a planar circular connection pad portion, and openings corresponding to the dummy base metal layer 16 are not formed in the insulating film 3 and the upper insulating film 5. In addition, it is not electrically connected to the high frequency integrated circuit of the silicon substrate 1. Therefore, even if the dummy wiring 17 including the dummy base metal layer 16 is provided in the wiring formation prohibition region 7 in the central portion of the upper surface of the upper insulating film 5, the high frequency integrated circuit provided in the central portion of the upper surface of the dummy wiring 17 and the silicon substrate 1. Crosstalk does not occur between In this case, it is desirable that the dummy wirings 17 including the dummy base metal layer 16 are not connected to each other. However, if there is no problem, the dummy wirings 17 may be integrally patterned so as to be connected to adjacent ones as appropriate. Also good.

（第３実施形態）
図３（Ａ）はこの発明の第３実施形態としての半導体装置の平面図を示し、図３（Ｂ）は図３（Ａ）のＢ−Ｂ線に沿う断面図を示す。この半導体装置において、図１（Ａ）、（Ｂ）に示す半導体装置と大きく異なる点は、ダミー半田ボール１５を有せず、上層絶縁膜および配線を２層とした点である。 (Third embodiment)
3A is a plan view of a semiconductor device as a third embodiment of the present invention, and FIG. 3B is a cross-sectional view taken along line BB in FIG. 3A. This semiconductor device differs greatly from the semiconductor device shown in FIGS. 1A and 1B in that the dummy solder ball 15 is not provided and the upper insulating film and the wiring are formed in two layers.

すなわち、第１の上層絶縁膜５Ａの上面には第１の下地金属層８Ａを含む第１の配線９Ａが設けられている。第１の下地金属層８Ａを含む第１の配線９Ａの一端部は、絶縁膜３および第１の上層絶縁膜５Ａの開口部４、６Ａを介して接続パッド２に接続されている。第１の配線９Ａを含む第１の上層絶縁膜５Ａの上面には、第１の上層絶縁膜５Ａと同一の材料からなる第２の上層絶縁膜５Ｂが設けられている。   That is, the first wiring 9A including the first base metal layer 8A is provided on the upper surface of the first upper insulating film 5A. One end of the first wiring 9A including the first base metal layer 8A is connected to the connection pad 2 via the insulating film 3 and the openings 4 and 6A of the first upper insulating film 5A. A second upper layer insulating film 5B made of the same material as that of the first upper layer insulating film 5A is provided on the upper surface of the first upper layer insulating film 5A including the first wiring 9A.

第２の上層絶縁膜５Ｂの上面には第２の下地金属層８Ｂを含む第２の配線９Ｂが設けられている。第２の下地金属層８Ｂを含む第２の配線９Ｂの一端部は、第２の上層絶縁膜５Ｂの開口部６Ｂを介して第１の配線９Ａの接続パッド部に接続されている。第２の配線９Ｂの接続パッド部上面には柱状電極１０が設けられている。第２の配線９Ｂを含む第２の上層絶縁膜５Ｂの上面には封止膜１１がその上面が柱状電極１０の上面と面一となるように設けられている。柱状電極１０の上面には半田ボール１５が設けられている。   A second wiring 9B including a second base metal layer 8B is provided on the upper surface of the second upper insulating film 5B. One end portion of the second wiring 9B including the second base metal layer 8B is connected to the connection pad portion of the first wiring 9A through the opening 6B of the second upper insulating film 5B. A columnar electrode 10 is provided on the upper surface of the connection pad portion of the second wiring 9B. A sealing film 11 is provided on the upper surface of the second upper insulating film 5B including the second wiring 9B so that the upper surface thereof is flush with the upper surface of the columnar electrode 10. A solder ball 15 is provided on the upper surface of the columnar electrode 10.

そして、この半導体装置では、第１の上層絶縁膜５Ａの上面中央部が配線形成禁止領域７であっても、第１の上層絶縁膜５Ａとその上に設けられた第２の上層絶縁膜５Ｂとの合計厚さにより、第２の上層絶縁膜５Ｂの上面全体をシリコン基板１の高周波集積回路とのクロストークを防止して配線形成可能領域とし、第２の上層絶縁膜５Ｂの上面全体に設けられた第２の配線９Ｂの接続パッド部上面に柱状電極１０を設け、柱状電極１０の上面に半田ボール１４を設けているので、実装時の接合力が不足しないようにすることができ、ひいては実装上の信頼性を向上することができる。   In this semiconductor device, even if the central portion of the upper surface of the first upper layer insulating film 5A is the wiring formation prohibition region 7, the first upper layer insulating film 5A and the second upper layer insulating film 5B provided thereon are provided. Thus, the entire upper surface of the second upper insulating film 5B is prevented from crosstalk with the high-frequency integrated circuit of the silicon substrate 1 to form a wiring formable region, and is formed on the entire upper surface of the second upper insulating film 5B. Since the columnar electrode 10 is provided on the upper surface of the connection pad portion of the provided second wiring 9B and the solder ball 14 is provided on the upper surface of the columnar electrode 10, the bonding force at the time of mounting can be prevented from being insufficient. As a result, the mounting reliability can be improved.

ところで、図１（Ｂ）に示す半導体装置では、絶縁膜５の上面の配線形成禁止領域７の周囲に配線９を設けているので、配線９の引き回し可能面積が比較的小さくなり、ひいては柱状電極１０および半田ボール１４の狭ピッチ化を強いられる。これに対し、図３（Ｂ）に示す半導体装置では、第２の上層絶縁膜５Ｂの上面全体に第２の配線９Ｂを設けているので、柱状電極１０および半田ボール１４の狭ピッチ化を強いられないようにすることができる。この場合、例えば、図３（Ｂ）において左側に示すように、第１の配線９Ａの少なくとも一部は実質的に接続パッド部のみとすることも可能である。   By the way, in the semiconductor device shown in FIG. 1B, since the wiring 9 is provided around the wiring formation prohibition region 7 on the upper surface of the insulating film 5, the wiringable area of the wiring 9 becomes relatively small, and as a result, the columnar electrode 10 and the solder balls 14 are forced to narrow. In contrast, in the semiconductor device shown in FIG. 3B, since the second wiring 9B is provided on the entire upper surface of the second upper insulating film 5B, the pitch between the columnar electrodes 10 and the solder balls 14 is strongly reduced. Can be prevented. In this case, for example, as shown on the left side in FIG. 3B, at least a part of the first wiring 9A can be substantially only the connection pad portion.

なお、図１（Ａ）、（Ｂ）に示す半導体装置では、シリコン基板１の上面中央部に高周波集積回路が設けられていることにより、絶縁膜５の上面中央部を配線形成禁止領域７とした場合について説明したが、本発明はこれに限定されるものではない。例えば、接続パッド２の数や配線９の引き回し、あるいは回路基板の配線等の関係により、柱状電極１０をシリコン基板１の周縁部のみに形成すればよく、シリコン基板１の中央部にまで形成する必要が無い場合、あるいは形成することができない場合においては、いかような集積回路を有するシリコン基板１に対しても、封止膜１１の上面中央部にダミー半田ボール１５を設け、実装時の接合力が十分となるようにすることができる。   In the semiconductor device shown in FIGS. 1A and 1B, since the high-frequency integrated circuit is provided in the central portion of the upper surface of the silicon substrate 1, the central portion of the upper surface of the insulating film 5 is connected to the wiring formation inhibition region 7. However, the present invention is not limited to this. For example, the columnar electrode 10 may be formed only on the peripheral edge of the silicon substrate 1 depending on the number of the connection pads 2, the wiring 9, or the wiring of the circuit board. When it is not necessary or cannot be formed, a dummy solder ball 15 is provided at the center of the upper surface of the sealing film 11 for the silicon substrate 1 having any integrated circuit, and bonding at the time of mounting is performed. The power can be sufficient.

（Ａ）はこの発明の第１実施形態としての半導体装置の平面図、（Ｂ）はそのＢ−Ｂ線に沿う断面図。(A) is a top view of the semiconductor device as 1st Embodiment of this invention, (B) is sectional drawing which follows the BB line. （Ａ）はこの発明の第２実施形態としての半導体装置の平面図、（Ｂ）はそのＢ−Ｂ線に沿う断面図。(A) is a top view of the semiconductor device as 2nd Embodiment of this invention, (B) is sectional drawing which follows the BB line. （Ａ）はこの発明の第３実施形態としての半導体装置の平面図、（Ｂ）はそのＢ−Ｂ線に沿う断面図。(A) is a top view of the semiconductor device as 3rd Embodiment of this invention, (B) is sectional drawing which follows the BB line.

符号の説明Explanation of symbols

１ シリコン基板
２ 接続パッド
３ 絶縁膜
５ 上層絶縁膜
７ 配線形成禁止領域（配線非形成領域）
９ 配線
１０ 柱状電極
１１ 封止膜
１２ 表面処理層
１３ ダミー表面処理層
１４ 半田ボール（半田層）
１５ ダミー半田ボール（ダミー半田層）
１７ ダミー配線
１８ ダミー柱状電極
５Ａ 第１の上層絶縁膜
５Ｂ 第２の上層絶縁膜
９Ａ 第１の配線
９Ｂ 第２の配線 DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Connection pad 3 Insulating film 5 Upper-layer insulating film 7 Wiring formation prohibition area | region (wiring non-formation area | region)
9 Wiring 10 Columnar electrode 11 Sealing film 12 Surface treatment layer 13 Dummy surface treatment layer 14 Solder ball (solder layer)
15 Dummy solder ball (dummy solder layer)
17 dummy wiring 18 dummy columnar electrode 5A first upper-layer insulating film 5B second upper-layer insulating film 9A first wiring 9B second wiring

Claims (7)

上面周辺部に複数の接続パッドが設けられた半導体基板と、前記半導体基板の上面に設けられた絶縁膜と、前記絶縁膜の上面周辺部に前記接続パッドに接続されて設けられた配線と、前記配線の接続パッド部上面に設けられた柱状電極と、前記配線を含む前記絶縁膜の上面に上面が前記柱状電極の上面と面一となるように設けられた封止膜と、前記柱状電極の上面に設けられた半田層と、前記封止膜の上面中央部に設けられたダミー半田層とを備えていることを特徴とする半導体装置。   A semiconductor substrate provided with a plurality of connection pads on the periphery of the upper surface; an insulating film provided on the upper surface of the semiconductor substrate; a wiring provided on the periphery of the upper surface of the insulating film connected to the connection pads; A columnar electrode provided on an upper surface of a connection pad portion of the wiring; a sealing film provided on an upper surface of the insulating film including the wiring so that an upper surface is flush with an upper surface of the columnar electrode; and the columnar electrode A semiconductor device comprising: a solder layer provided on an upper surface of the semiconductor device; and a dummy solder layer provided on a central portion of the upper surface of the sealing film. 請求項１に記載の発明において、前記ダミー半田層は、前記絶縁膜の上面中央部に設けられたダミー配線の上面に設けられたダミー柱状電極の上面に設けられていることを特徴とする半導体装置。   2. The semiconductor according to claim 1, wherein the dummy solder layer is provided on an upper surface of a dummy columnar electrode provided on an upper surface of a dummy wiring provided in a central portion of the upper surface of the insulating film. apparatus. 請求項１または２に記載の発明において、前記絶縁膜の上面中央部は配線非形成領域となっていることを特徴とする半導体装置。   3. The semiconductor device according to claim 1, wherein a central portion of the upper surface of the insulating film is a wiring non-forming region. 請求項３に記載の発明において、前記半導体基板の上面中央部に高周波集積回路が設けられていることを特徴とする半導体装置。   4. The semiconductor device according to claim 3, wherein a high-frequency integrated circuit is provided at a central portion of the upper surface of the semiconductor substrate. 請求項１に記載の発明において、前記半田層下における前記柱状電極の上面に表面処理層が設けられ、前記ダミー半田層下における前記封止膜の上面にダミー表面処理層が設けられていることを特徴とする半導体装置。   The invention according to claim 1, wherein a surface treatment layer is provided on the upper surface of the columnar electrode under the solder layer, and a dummy surface treatment layer is provided on the upper surface of the sealing film under the dummy solder layer. A semiconductor device characterized by the above. 上面周辺部に複数の接続パッドが設けられた半導体基板と、前記半導体基板の上面に設けられ、上面中央部を配線非形成領域とされた第１の絶縁膜と、前記第１の絶縁膜の上面周辺部に前記接続パッドに接続されて設けられた第１の配線と、前記第１の配線を含む前記第１の絶縁膜の上面に設けられた第２の絶縁膜と、前記第２の絶縁膜の上面全体に前記第１の配線の接続パッド部に接続されて設けられた第２の配線と、前記第２の配線の接続パッド部上面に設けられた柱状電極と、前記第２の配線を含む前記第２の絶縁膜の上面に上面が前記柱状電極の上面と面一となるように設けられた封止膜と、前記柱状電極の上面に設けられた半田層とを備えていることを特徴とする半導体装置。   A semiconductor substrate provided with a plurality of connection pads on the periphery of the upper surface, a first insulating film provided on the upper surface of the semiconductor substrate, the central portion of the upper surface being a non-wiring region, and the first insulating film A first wiring provided on the periphery of the upper surface connected to the connection pad; a second insulating film provided on an upper surface of the first insulating film including the first wiring; and the second wiring A second wiring provided on the entire upper surface of the insulating film connected to the connection pad portion of the first wiring; a columnar electrode provided on the upper surface of the connection pad portion of the second wiring; A sealing film provided on an upper surface of the second insulating film including the wiring so that an upper surface thereof is flush with an upper surface of the columnar electrode; and a solder layer provided on the upper surface of the columnar electrode. A semiconductor device. 請求項６に記載の発明において、前記半導体基板の上面中央部に高周波集積回路が設けられていることを特徴とする半導体装置。   7. The semiconductor device according to claim 6, wherein a high-frequency integrated circuit is provided at a central portion of the upper surface of the semiconductor substrate.
JP2006115421A 2006-04-19 2006-04-19 Semiconductor device Pending JP2007288038A (en)

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