JP2007281348A - Semiconductor device, and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To secure the reliability of a semiconductor device provided with a gate electrode having a sidewall. <P>SOLUTION: A silicon oxide film is formed on the main surface of a semiconductor substrate 1S so as to cover an auxiliary gate electrode 4G while increasing the supply amount of oxygen with the lapse of time by a CVD method using mixed gas containing mono-silane and oxygen. In the silicon oxide film, much silicon is contained in a semiconductor substrate side lower layer as compared with an upper layer of the silicon oxide film. Then the silicon oxide film is etched back to form a sidewall 16 on the sidewall of the auxiliary gate electrode 4G. On the main surface of the semiconductor substrate 1S which is exposed by the etch-back, a tunnel insulating film 15 is formed. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing technique thereof, and particularly to a technique effective when applied to the manufacture of a semiconductor device having a gate electrode having a sidewall.

  Electrically rewritable non-volatile memory elements such as flash memory can be rewritten on-board, which can shorten development time and improve development efficiency. Applications are expanding for various purposes such as tuning by destination and program update after shipment. In particular, in recent years, there has been an increasing need for a microcomputer incorporating an MPU (Micro Processing Unit) and a flash memory.

  Japanese Patent Laying-Open No. 2005-85903 (Patent Document 1) discloses a technology related to an auxiliary gate electrode type flash memory. A plurality of auxiliary gate electrodes extending in a predetermined direction are arranged adjacent to each other on a semiconductor substrate in the memory area of the flash memory. In the upper layer of the plurality of auxiliary gate electrodes, a plurality of word lines extending in a direction perpendicular to the extending direction of the auxiliary gate electrodes are arranged adjacent to each other. A floating gate electrode is arranged between each of the plurality of auxiliary gate electrodes and between each of the word lines and the semiconductor substrate in a state of being electrically separated from other members. . The floating gate electrode is formed such that the height of the upper surface thereof is higher than the height of the upper surface of the auxiliary gate electrode.

Japanese Patent Laid-Open No. 11-163337 (Patent Document 2) discloses a technique related to a field effect transistor having an LDD structure. A side wall made of non-doped polysilicon is formed as a protective insulating film on the side wall portion of the gate electrode of the field effect transistor, and impurities are simultaneously introduced into the source / drain diffusion layer formation region and the side wall. Then, the low concentration region and the high concentration region of the LDD process are simultaneously formed by the same heat treatment.
JP 2005-85903 A JP-A-11-163337

  For example, the present inventors have studied the manufacture of a semiconductor device including an auxiliary gate electrode type flash memory as disclosed in Patent Document 1 above. The semiconductor device studied by the present inventors will be described below with reference to FIGS. 20 and 21 are cross-sectional views schematically showing the main part of the flash memory during the manufacturing process studied by the present inventors.

  The memory cell MC0 examined by the present inventors has an auxiliary gate electrode 4G, a control gate electrode 5 and a charge storage floating gate electrode 6G formed on the main surface of the semiconductor substrate 1S. Between the auxiliary gate electrode 4G and the semiconductor substrate 1S, there is a gate insulating film 8, and between the floating gate electrode 6G and the semiconductor substrate 1S, on the tunnel insulating film 15, the auxiliary gate electrode 4G, and the floating gate electrode 6G. An ONO film 18 is provided between the control gate electrode 5. Further, a sidewall 116 of the auxiliary gate electrode 4G is provided between the auxiliary gate electrode 4G and the floating gate electrode 6G to insulate and separate them.

  As shown in FIG. 20, an auxiliary gate electrode 4 </ b> G is provided on the main surface of the semiconductor substrate 1 </ b> S via a gate insulating film 8. A cap film 10 and an insulating film 11 are provided on the auxiliary gate electrode 4G. The cap film 10 functions as an etching stopper in a later process, and the insulating film 11 intersects the height of the floating gate electrode formed in the later process (the main surface of the semiconductor substrate 1). (Dimension in the direction).

  For example, silicon oxide is deposited on the main surface of the semiconductor substrate 1S provided with the auxiliary gate electrode 4G, the cap film 10 and the insulating film 11 by, for example, a CVD method using a mixed gas of monosilane and oxygen. By etching back, the sidewall 116 is formed on the side wall of the laminated film of the auxiliary gate electrode 4G, the cap film 10 and the insulating film 11. Further, a groove 28 is formed between the adjacent auxiliary gate electrodes 4G. In this etch back process, the surface of the semiconductor substrate 1S is scraped, and the scraped portion 109 is formed. The effect of this semiconductor substrate 1S shaving will be described later.

  After the sidewalls 116 are formed, a conductor film is deposited on the tunnel tunnel insulating film 15 and the tunnel insulating film 15 on the bottom of the trench 28 (the shaved portion 109), and the insulating film 11 is removed. As shown in FIG. 21, a floating gate electrode 6G made of the conductive film is formed between the auxiliary gate electrodes 4G.

  Further, an ONO film 18 is formed so as to cover the floating gate electrode 6G and the auxiliary gate electrode 4G, and a control gate electrode 5 composed of the conductor film 5a and the conductor film 5b is formed on the ONO film 18.

  However, the memory cell MC0 formed in this way has a problem that the detrap characteristic deteriorates. In addition, the threshold distribution that can be determined as multi-valued has a problem that the bottom of the distribution is shifted (expanded) after writing, and multi-valued determination cannot be performed. These problems are considered to be caused by the semiconductor substrate 1S that has been shaved in the etch-back process for forming the sidewall 116.

  In addition, even in a field effect transistor formed as a peripheral circuit of a memory cell, when a similar etch back process is performed when a sidewall is formed on a gate electrode, the surface of the semiconductor substrate may be scraped. It is done. FIG. 22 is a cross-sectional view schematically showing a main part of a field effect transistor examined by the present inventors. In the figure, PW1 is a well, 32a and 32b are semiconductor regions, 34 is a silicide layer, 8 is a gate insulating film, 4A is a gate electrode, 10 is a cap film, 11 is an insulating film, and 117 is a sidewall.

As shown in FIG. 22, when the surface of such a semiconductor substrate 1S is scraped, the end portion of the silicide layer 34 is connected to the n ⁺ type semiconductor region 32b and the semiconductor substrate in the depth direction and the gate length direction. It becomes close to the joint surface with 1S. The silicide layer 34 is mainly formed of a metal compound of metal such as CoSi ₂ (cobalt silicide) or NiSi (nickel silicide) and silicon. According to the study by the present inventors, the main surface of the semiconductor substrate 1S is shaved and a depression is formed, whereby the silicide layer 34 is formed on the upper surface of the depression. In this case, the end portion of the silicide layer 34 approaches the bonding surface between the n ⁺ type semiconductor region 32b and the semiconductor substrate 1S. Here, when a voltage is applied to the silicide layer 34, the electric field concentrates on the junction surface, which causes problems such as the occurrence of a leakage current to the semiconductor substrate 1 </ b> S.

  Further, the silicide layer 34 may grow abnormally and reach the semiconductor substrate 1S. As such factors, there are unreacted cobalt, impurities, or natural oxide films that could not be removed by the cleaning before the silicide layer 34 forming step on the surface of the semiconductor substrate 1S, and the silicide layer corresponding to the presence or absence of these. This is because problems such as occurrence of thick portions and thin portions occur.

  An object of the present invention is to provide a technique capable of ensuring the reliability of a semiconductor device including a gate electrode having a sidewall.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  According to the present invention, a silicon oxide film formed on a main surface of a semiconductor substrate is etched back so that a side wall provided on a side wall of the gate electrode covers the gate electrode, and the silicon oxide film is an upper layer of the silicon oxide film. The lower layer contains a lot of silicon.

  Further, according to the present invention, in the formation of the silicon oxide film serving as a side wall provided on the side wall of the gate electrode, the supply amount of oxygen is increased with time.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  According to the present invention, the reliability of a semiconductor device including a gate electrode having a sidewall can be improved.

  In the drawings used in the following embodiments, even plan views may be hatched to make the drawings easy to see. In all the drawings for explaining the embodiments, the same members are denoted by the same reference symbols in principle, and the repeated explanation thereof is omitted. In the following embodiments, MISFET (Metal Insulator Semiconductor Field Effect Transistor) which is a field effect transistor is abbreviated as MIS, n-channel type MIS is abbreviated as nMIS, and p-channel type MIS is abbreviated as pMIS. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  In this embodiment, an example in which the present invention is applied to a semiconductor device provided with, for example, a 4 Gbit AND type flash memory will be described.

  1 is a plan view of a main part of the flash memory according to the present embodiment, FIG. 2 is a cross-sectional view taken along line Y1-Y1 in FIG. 1, FIG. 3 is a cross-sectional view taken along line X1-X1 in FIG. Cross-sectional views taken along line X2-X2 are shown. In addition, the code | symbol X of FIG. 1 has shown the 1st direction, and the code | symbol Y of the figure has shown the 2nd direction orthogonal to the 1st direction X.

  A semiconductor substrate (hereinafter simply referred to as a substrate) 1S of the semiconductor chip on which the flash memory of the present embodiment is formed is made of, for example, p-type silicon (Si) single crystal, and its main surface (device formation surface) is Active region 2, isolation region 3, a plurality of auxiliary gate electrodes 4G, a plurality of word lines (control gate electrodes) 5, a plurality of floating gate electrodes 6G, a plurality of nonvolatile memory cells (hereinafter simply referred to as memory cells) MC and a plurality of Are selected nMISQsn0 and selected nMISQsn1.

  Looking at the cross section of the substrate 1S, the p-type well PW1 and the n-type well PW1 are formed in the memory region (the region where the memory cells MC are formed) and the selection transistor region (the region where the selection nMISQsn is formed) of the substrate 1S. A buried region NISO is formed. For example, boron (B) is introduced into the p-type well PW1, and the outer periphery (side surface and bottom surface) thereof is surrounded by the n-type buried region NISO. For example, phosphorus (P) is introduced into the n-type buried region NISO.

The active region 2 is a region where a device is formed. The planar outline of the active region 2 is defined by the separation region 3. The isolation region 3 is a trench-type isolation region called STI (Shallow Trench Isolation) or SGI (Shallow Groove Isolation), for example. That is, an insulating film such as silicon oxide (SiO ₂ or the like) is buried in the groove dug in the substrate 1S.

  Each of the plurality of auxiliary gate electrodes 4G has a rectangular shape whose planar shape extends in the first direction X. The auxiliary gate electrodes 4G are arranged in parallel in the second direction Y with a desired distance therebetween. The dimension (width) in the second direction Y of the thin portion of the auxiliary gate electrode 4G is, for example, about 65 nm. Further, the interval between adjacent auxiliary gate electrodes 4G is, for example, about 115 nm. The auxiliary gate electrode 4G is arranged so that most of it overlaps the active region 2 in a plane. When a desired voltage is applied to the auxiliary gate electrode 4G, an n-type inversion layer is formed on the main surface portion of the substrate 1S in the active region 2 along the auxiliary gate electrode 4G. This n-type inversion layer is a portion for forming a bit line (a source and a drain of the memory cell MC).

  A mechanism in which the source and drain of the memory cell MC are electrically connected to the global bit line and the common drain wiring will be described below with reference to FIG. Note that the cross-sectional structures of the X2-X2 line and the X3-X3 line in FIG. 1 are the same symmetrically except that they are electrically connected to the global bit line or the common drain wiring. A detailed description of the X3 line is omitted.

When a desired voltage is applied to desired auxiliary gate electrode 4G, a drain bit line (n-type inversion layer) is formed in active region 2 below auxiliary gate electrode 4G shown in FIG. That is, as shown in FIG. 4, it is electrically connected to a desired selected nMISQsn through an n ⁻ type semiconductor region 7 formed on the main surface portion of the substrate 1S, and further connected to the common drain wiring and the electric via the selected nMISQsn. Connected. The n ⁻ type semiconductor region 7 is formed by introducing, for example, arsenic (As) between the auxiliary gate electrode 4G and the selected nMISQsn on the extension line in the first direction X. Further, as described above, the same applies to the connection of the source of the memory cell MC to the global bit line. That is, each auxiliary gate electrode 4G is provided to form a source region and a drain region of the memory cell MC.

  As described above, in the present embodiment, in the region where each memory cell MC is formed, the bit line inversion layer is formed on the main surface portion of the substrate 1S of the active region 2 by the auxiliary gate electrode 4G. That is, since the semiconductor region for the bit line is not formed, the size of the memory cell MC can be greatly reduced, and the overall size of the memory region can be greatly reduced. The auxiliary gate electrode 4G has an isolation function between adjacent memory cells MC in addition to the function of forming the bit line.

  For example, four auxiliary gate electrodes 4G (G0 to G3) are arranged in the unit area of the memory area. That is, four auxiliary gate electrodes 4G (G0 to G3) form one set. In FIG. 1, a wide region 4GA for connection to the upper layer wiring is formed at the right end of one auxiliary gate electrode 4G (G1) in the unit region, and an upper layer is formed at the left end of the adjacent auxiliary gate electrode 4G (G2). A wide region 4GA for connection with the wiring is formed, the right end of the auxiliary gate electrode 4G (G3) adjacent below the wiring is connected to the wiring 4LA, and the left end of the auxiliary gate electrode 4G (G0) adjacent below the wiring is the wiring. It is connected to 4LB.

  The wirings 4LA and 4LB have a strip-like pattern extending in the second direction Y of FIG. 1, and one auxiliary gate electrode 4G (G3, G0) is integrally connected to each of the wirings 4LA and 4LB. ing. That is, the wirings 4LA and 4LB are common wirings for the plurality of auxiliary gate electrodes 4G that supply the same potential.

  Such auxiliary gate electrodes 4G (G0 to G3), 4GA and wirings 4LA, 4LB are formed, for example, by patterning a low-resistance polycrystalline silicon film in the same process. Here, the plurality of auxiliary gate electrodes 4G for supplying the same potential, the wide region 4GA, and the wirings 4LA and 4LB are integrally formed and electrically connected to each other in the same layer for ease of formation and the like. .

  The thickness of the auxiliary gate electrode 4G and the wirings 4LA and 4LB is, for example, about 50 nm. By thinning the auxiliary gate electrode 4G in this way, the coupling ratio between the auxiliary gate electrode 4G and the floating gate electrode 6G can be reduced, so that the floating gate electrode 6G can be lowered.

The gate insulating film 8 between the auxiliary gate electrode 4G and the wirings 4LA and 4LB and the main surface of the substrate 1S is made of, for example, silicon oxide, and the thickness thereof is, for example, about 8.5 nm in terms of silicon dioxide. . Further, a cap film 10 made of, for example, silicon nitride (Si ₃ N ₄ or the like) is formed on the upper surfaces of the auxiliary gate electrode 4G and the wirings 4LA and 4LB. Further, an insulating film 11 made of, for example, silicon oxide is deposited on the auxiliary gate electrode 4G on the outer periphery of the memory region, the wide region 4GA, and the cap film 10 of the wirings 4LA, 4LB. An insulating film 12 made of is deposited.

  The auxiliary gate electrode 4G is electrically connected to the upper first layer wiring M1 through the plug PG in the contact hole CT. The contact hole CT is opened in the cap film 10 and the insulating films 11 and 12, and is disposed in a part of the wide region 4GA and the wirings 4LA and 4LB.

  The plurality of word lines 5 (WL) are formed in 256 for one block of memory cells (memory mat). In the present embodiment, WL0 to WL2 are shown for easy understanding.

  Each of the word lines 5 (WL0 to 2) has a rectangular shape whose planar shape extends in the second direction Y. That is, the word lines 5 (WL0 to 2) are arranged substantially in parallel at a desired distance along the first direction X in FIG. 1 in a state orthogonal to the auxiliary gate electrodes 4G (G0 to 3). Is arranged in.

  A portion of the word line 5 located between adjacent auxiliary gate electrodes 4G serves as a control gate electrode of the memory cell MC. The design dimension of the word line 5 in the first direction X and the design interval between adjacent word lines 5 are equal, for example, about 90 nm. In this way, by making the design dimension of the word line 5 in the first direction X equal to the design interval between the adjacent word lines 5, the control gate electrode 5 (conductor film 5a) and the floating gate electrode 6G. Since the calculation of the coupling ratio can be facilitated, the coupling ratio can be set to a better value. That is, the coupling ratio between the control gate electrode 5 (conductor film 5a) and the floating gate electrode 6G can be maximized.

Each word line 5 is a laminated film of a conductor film 5a made of, for example, low-resistance polycrystalline silicon and a conductor film 5b made of a refractory metal silicide film such as tungsten silicide (WSi _x ) formed on the upper surface thereof. It is formed by. On the upper surface of the word line 5, an insulating film 13 made of, for example, silicon oxide is deposited. Note that the outermost word lines 5 in the first direction X have a pattern that does not contribute to the memory operation, and are formed wider than the other word lines 5 in consideration of thinning during exposure. Further, as shown in the cross-sectional view of FIG. 2, in the Y direction of each memory cell MC, the lower conductor film 5a of the word line 5 is formed so as to be buried between the floating gate electrodes 6G via the ONO film 18. Yes.

  The plurality of floating gate electrodes 6G are disposed in a state of being electrically insulated between adjacent portions of the auxiliary gate electrodes 4G (G0 to G3) and intersections of the word lines 5 (WL0 to WL2). The floating gate electrode 6G is a charge storage layer for data of the memory cell MC, and is formed of, for example, low resistance polycrystalline silicon.

  The floating gate electrode 6G is formed in a rectangular shape when viewed in plan. The dimension of the floating gate electrode 6G in the first direction X is substantially equal to the dimension of the word line 5 in the first direction X, for example, about 90 nm, and the dimension of the floating gate electrode 6G in the second direction Y is the auxiliary gate. The distance between adjacent electrodes 4G is slightly shorter, for example, about 65 nm.

  The floating gate electrode 6G is provided on the main surface of the substrate 1S through the tunnel insulating film 15 when viewed in cross section. The tunnel insulating film 15 is an insulating film that functions as a tunnel insulating film of the memory cell MC, and is made of, for example, silicon oxynitride (SiON). This silicon oxynitride is a film having a configuration in which nitrogen (N) is segregated at the interface between silicon oxide and the substrate 1S.

  Although the tunnel insulating film 15 may be formed of, for example, silicon oxide, the reliability of the tunnel insulating film 15 can be improved by forming it with silicon oxynitride. That is, by bonding nitrogen to an unstable bond or trap level formed on the main surface of the substrate 1S due to damage or the like given to the substrate 1S before the tunnel insulating film 15 is formed, the tunnel insulating film 15 Reliability can be improved. The thickness of the tunnel insulating film 15 is a silicon dioxide equivalent film thickness, for example, about 9 nm.

  An insulating film (silicon oxide film) serving as a sidewall 16 is formed between the floating gate electrode 6G and the auxiliary gate electrode 4G, whereby the auxiliary gate electrode 4G and the floating gate electrode 6G are insulated. ing. In addition, an insulating film 17 is formed between the floating gate electrode 6G and the word line 5 adjacent to each other in the first direction X, so that the floating gate electrodes 6G and the word lines 5 adjacent to each other in the first direction X are connected. Insulated. The insulating film and the insulating film 17 that become the sidewalls 16 are made of, for example, a silicon oxide film.

  Here, in the present embodiment, the sidewall 16 is formed by etching back a silicon oxide film formed on the main surface of the substrate 1S so as to cover the auxiliary gate electrode 4G. The silicon oxide film that becomes the sidewall 16 contains a larger amount of silicon in the lower layer than in the upper layer. As will be described later, this silicon oxide film is formed by increasing the supply amount of oxygen over time by a CVD method using a mixed gas containing monosilane and oxygen. For this reason, the silicon oxide film used as the sidewall 16 has a concentration distribution in which silicon decreases from the lower layer to the upper layer. Further, the silicon oxide film to be the sidewall 16 containing more silicon in the lower layer than the upper layer may be a laminated film. That is, the lowermost layer of the laminated film only needs to contain more silicon than the layers other than the lowermost layer.

  An ONO film 18 is formed between the floating gate electrode 6G and the control gate electrode of the word line 5. The ONO film 18 is a film that forms a capacitor between the floating gate electrode 6G and the control gate electrode, and has, for example, a so-called ONO structure in which silicon oxide, silicon nitride, and silicon oxide are sequentially stacked from the lower layer. The thickness of the ONO film 18 is a silicon dioxide equivalent film thickness, for example, about 16 nm.

  The floating gate electrode 6G is formed in a quadrangular prism shape in a direction intersecting the main surface of the substrate 1S (see FIGS. 2 and 3), and has a shape protruding from the surface of the semiconductor substrate 1S. ing. That is, the floating gate electrode 6G is formed in a rectangular column shape on the semiconductor substrate 1S via the tunnel insulating film 15 in a region sandwiched between the auxiliary gate electrodes 4G. The floating gate electrode 6G is formed such that the height (height from the main surface of the substrate 1S) is higher than the height of the first electrode 4G (height from the main surface of the substrate 1S). The height H1 of the floating gate electrode 6G (the height from the upper surface of the insulating film 15) is, for example, about 270 to 300 nm. The protruding height H2 of the floating gate electrode 6G (the height from the upper surface of the ONO film 18 on the first electrode 4G) is, for example, about 190 nm.

  The capacitors of the floating gate electrode 6G and the control gate electrode 5 are formed on the side wall and the upper surface of the floating gate electrode 6G. That is, a capacitor is formed between the word line 5 and the floating gate electrode 6G through the ONO film 18 in the direction in which the word line 5 extends (YY direction in FIG. 1). This capacitance is calculated as the sum of capacitance values formed on the upper surface portion and the side wall portion of the floating gate electrode 6G. Accordingly, even if the minimum processing dimension is further reduced, the area occupied by the memory cell MC is increased by increasing the floating gate electrode 6G to increase the facing area between the floating gate electrode 6G and the control gate electrode 5. Since the capacitance of the capacitor can be increased, the coupling ratio between the floating gate electrode 6G and the control gate electrode 5 can be improved.

  Therefore, the controllability of the voltage control of the floating gate electrode 6G by the control gate electrode can be improved, so that the writing and erasing speed of the flash memory can be improved even at a low voltage, and the voltage of the flash memory can be lowered. can do. That is, both miniaturization and low voltage of the flash memory can be realized.

  The plurality of selected nMISQsn are disposed on the bit line side serving as the drain and the bit line side serving as the source of the memory cell MC. On the bit line side serving as the drain of FIG. 1, each selected nMISQsn0 is arranged for each bit line along the second direction Y on the right side of FIG. Further, on the bit line side serving as the source, each selected nMISQsn1 is arranged for each bit line along the second direction Y on the left side of FIG.

  As shown in FIG. 1, the gate electrode 4LC1 of the selected nMISQsn0 on the bit line side serving as the drain is a part of the strip-like wiring 4LC extending in the second direction Y along the wiring 4LA (the strip of the active region 2). A portion intersecting the region). For the selected nMISQsn1 on the bit line side serving as the source, the wiring 4LD1 serving as the gate electrode is part of the strip-shaped wiring 4LD extending in the second direction Y along the wiring 4LB (with the band-shaped region of the active region 2). (Intersection). The gate electrode 4LC1, the wirings 4LC, 4LD1 and the wiring 4LD are made of, for example, a low-resistance polycrystalline silicon film, and are patterned simultaneously when the auxiliary gate electrode 4G, the wide region 4GA and the wirings 4LA, 4LB are patterned.

  As shown in FIG. 4, a cap film 10 is deposited on the gate electrode 4LC1 and the wiring 4LC. The gate electrode 4LC1 and the wiring 4LC are electrically connected to the upper first layer wiring M1 through the plug PG in the contact hole CT. The gate insulating film 21 of each selected nMISQsn is made of, for example, silicon oxide, and is formed between the gate electrode 4LC1 and the substrate 1S.

One semiconductor region 22a for the source and drain of each selected nMISQsn is formed of the n ⁻ type semiconductor region 7 for bit line connection. Other semiconductor region 22b for source and drain of each selection nMISQsn has, n end formed near the gate electrode 4LC1 ^- -type semiconductor regions 22b1, n from the edge of the gate electrode 4LC1 ^- -type semiconductor region 22b1 formed correspondingly spaced, n ^- and a semiconductor region 22b2 of the high-concentration n ⁺ -type than type semiconductor region 22 b 1. For example, arsenic (As) is introduced into the semiconductor regions 22a and 22b.

  Next, writing, reading and erasing operations of the flash memory according to the present embodiment will be described. FIG. 5 is a cross-sectional view schematically showing the main part of the flash memory during operation.

  Data writing is based on the source side hot electron injection method. Thus, efficient data writing can be performed at high speed with low current. In addition, multi-value data can be stored in each memory cell MC.

  In the data write operation, for example, about 15 V is applied to the word line WL0 (5) to which the selected memory cell MC is connected, and 0 V is applied to the other word line WL1 (5), for example. For example, about 1V is applied to the first electrode G0 (4G) for forming the source of the selected memory cell MC, and about 7V is applied to the first electrode G1 (4G) for forming the drain of the selected memory cell MC. Apply. Thereby, an n-type inversion layer 23a for forming a source is formed on the main surface portion of the substrate 1S facing the first electrode G0 (4G), and the main surface portion of the substrate 1S facing the first electrode G1 (4G). Then, an n-type inversion layer 23b for forming a drain is formed.

  Further, for example, 0 V is applied to the other first electrodes G2 (4G) and G3 (4G). Thus, an inversion layer is not formed on the main surface portion of the substrate 1S facing the first electrodes G2 (4G) and G3 (4G), and isolation between the selected and non-selected memory cells MC is performed.

In this state, for example, a voltage of about 7V is applied to the wiring 4LC to turn on the selected nMISQsn0, and a voltage of about 4V applied to the common drain wiring CD is applied to the n ⁻ type semiconductor region 7 and the n type semiconductor region 7. This is supplied to the drain of the selected memory cell MC through the inversion layer 23b.

  However, in this state, the non-selected memory cell MC connected to the word line WL0 (5) is also in the same state as the selected memory cell MC, and data is also written to the non-selected memory cell MC.

  Therefore, for example, 0V is applied to the global bit line GBL0 to which the source forming inversion layer 23a of the selected memory cell MC is connected, while the source type n-type inversion layer 23a of the unselected memory cell MC is applied. For example, about 1.2 V is applied to the global bit line GBL2 to which is connected. Further, for example, 0 V is applied to the other global bit line GBL1.

  As a result, a write current flows from the drain to the source in the selected memory cell MC. At this time, the charge accumulated in the n-type inversion layer 23a on the source side flows as a certain channel current, and the tunnel insulating film 15 Then, data is written into the selected memory cell MC at a high speed by efficiently injecting it into the floating gate electrode 6G via (a constant charge injection method). On the other hand, the drain current does not flow from the drain to the source of the non-selected memory cell MC so that data is not written.

  In data read, the direction of the read current is opposite to that of the write operation. That is, the read current flows from the global bit lines GBL0 and GBL2 toward the common drain wiring CD.

  In the data read operation, for example, about 2 to 5 V is applied to the word line WL0 (5) to which the selected memory cell MC is connected, and 0 V is applied to the other word line WL1 (5), for example. Further, for example, about 5 V is applied to the first electrodes G0 (4G) and G1 (4G) for forming the source and drain of the selected memory cell MC. Thereby, an n-type inversion layer 23a for source is formed on the main surface portion of the substrate 1S facing the first electrode G0 (4G), and the main surface portion of the substrate 1S facing the first electrode G1 (4G) is formed. An n-type inversion layer 23b for the drain is formed.

  Further, for example, 0 V is applied to the other first electrodes G2 (4G) and G3 (4G). Thus, isolation is performed so that an inversion layer is not formed on the main surface portion of the substrate 1S facing the first electrodes G2 (4G) and G3 (4G).

Here, for example, about 1V is applied to the global bit lines GBL0 and GBL2 to which the n-type inversion layer 23a for the source of the selected memory cell MC is connected, and for example, 0V is applied to the other global bit lines GBL1. . In this state, for example, a voltage of about 3V is applied to the wiring 4LC to turn on the selected nMISQsn, and a voltage of about 0V applied to the common drain wiring CD is applied to the n ⁻ type semiconductor region 7 and the n type semiconductor region 7. This is supplied to the drain of the selected memory cell MC through the inversion layer 23b. In this way, data is read from the selected memory cell MC.

  At this time, since the threshold voltage of the selected memory cell MC changes depending on the state of the accumulated charge in the floating gate electrode 6G, the selected memory cell MC can be selected in the state of the current flowing between the source and drain of the selected memory cell MC. Can be determined.

  In the data erasing operation, a negative voltage is applied to the word line 5 to be selected, thereby performing FN (Fowlor Nordheim) tunnel emission from the floating gate electrode 6G to the substrate 1S. That is, for example, about −16 V is applied to the word line 5 to be selected, while a positive voltage is applied to the substrate 1S. For example, 0 V is applied to the auxiliary gate electrode 4G, and no n-type inversion layer is formed. As a result, the charge for data stored in the floating gate electrode 6G is discharged to the substrate 1S through the tunnel insulating film 15, and the data in the plurality of memory cells MC are erased collectively.

  Next, an example of a method for manufacturing the flash memory according to the present embodiment will be described with reference to FIGS. 6 to 17 are cross-sectional views showing the main part of the semiconductor device during the manufacturing process along the line Y1-Y1 in FIG. 1, in which (a) shows the memory region and (b) shows the peripheral circuit region. .

  First, as shown in FIG. 6, a groove type is formed on the main surface (device forming surface) of a substrate 1S made of, for example, p-type silicon single crystal (at this stage, a planar circular semiconductor wafer (hereinafter simply referred to as a wafer)). An isolation region 3 is formed. The isolation region 3 is formed by embedding an insulating film made of, for example, silicon oxide in a groove dug in the main surface of the substrate 1S, and the isolation region 3 forms an active region that is a region where a device is formed. Define the planar outline. Next, an insulating film 25 made of, for example, silicon oxide is formed on the main surface of the substrate 1S in the active region 2.

  Subsequently, as shown in FIG. 7, after the n-type buried region NISO is formed by selectively introducing, for example, phosphorus (P) into the memory region of the substrate 1S by a normal ion implantation method or the like, A p-type well PW1 is formed by selectively introducing, for example, boron (B) into the memory region and the peripheral circuit region of the substrate 1S. Further, for example, phosphorus is selectively introduced into the peripheral circuit region of the substrate 1S to form the n-type well NW1. After this well structure is formed, the insulating film 25 is removed.

  Subsequently, as shown in FIG. 8, a gate insulating film 8 made of, for example, silicon oxide or the like is formed on the main surface of the substrate 1S (wafer) so as to have a thickness of, for example, about 8.5 nm in terms of silicon dioxide. For example, it is formed by a thermal oxidation method such as an ISSG (In-Situ Steam Generation) oxidation method. Next, a conductive film 4 made of, for example, low-resistance polycrystalline silicon is deposited on the gate insulating film 8 by, for example, a CVD (Chemical Vapor Deposition) method so as to have a thickness of, for example, about 50 nm. A cap film 10 made of silicon nitride is deposited by a CVD method or the like so as to have a thickness of about 70 nm, for example.

  Subsequently, an insulating film 11 made of, for example, silicon oxide is deposited on the cap film 10 by, for example, a CVD method using TEOS (Tetraethoxysilane) gas, and then a hard mask film made of, for example, low-resistance polycrystalline silicon. 26a is deposited by a CVD method or the like, and an antireflection film 27a made of, for example, silicon oxynitride (SiON) is deposited thereon by a plasma CVD method or the like. Thereafter, a resist pattern RP1 for forming the auxiliary gate electrode 4G is formed on the antireflection film 27a.

  Subsequently, as shown in FIG. 9, using the resist pattern RP1 as an etching mask, the antireflection film 27a and the hard mask film 26a exposed therefrom are etched, and then the resist pattern RP1 is removed. Here, the pattern of the antireflection film 27a and the hard mask film 26a for forming the auxiliary gate electrode is formed by the etching process.

  Subsequently, as shown in FIG. 10, the insulating film 11, the cap film 10 and the conductor film 4 exposed therefrom are etched using the antireflection film 27a and the hard mask film 26a as an etching mask. Here, the auxiliary gate electrode 4G and the wide region 4GA are patterned by etching the conductor film 4. At this time, the width direction dimension (dimension in the second direction Y in FIG. 1) of the auxiliary gate electrode 4G is, for example, about 75 nm, and the adjacent interval in the second direction Y of the auxiliary gate electrode 4G is, for example, about 105 nm.

  In the etching process, the antireflection film 27a is etched when the insulating film 11 and the cap film 10 are etched, and the hard mask film 26a is etched when the conductor film 4 is etched. Therefore, the antireflection film 27a and the hard mask film 26a are not left after the etching process.

  Subsequently, an impurity such as boron is introduced into a region without the auxiliary gate electrode 4G and the conductor film 4 on the main surface portion of the substrate 1S (wafer) by a normal ion implantation method or the like. By this impurity introduction process, the threshold voltage of the substrate 1S under the auxiliary gate electrode 4G having a relatively low p-type impurity concentration becomes lower than the threshold voltage of the substrate 1S under the floating gate electrode 6G.

  This boron introduction step may not be performed depending on circumstances. The inventor's investigation has confirmed that the flash memory operates normally regardless of whether or not boron is introduced. Further, this boron introduction step can be performed after the formation of an insulating film 16 (side wall in the periphery) described later.

  Subsequently, as shown in FIG. 11, an insulating film 16 made of, for example, silicon oxide is deposited on the main surface of the substrate 1S by, for example, a CVD method using a mixed gas containing monosilane and oxygen, and then etched back. To do. By etching back the insulating film 16, the sidewall 16 is formed on the side wall of the laminated film of the auxiliary gate electrode 4G, the cap film 10 and the insulating film 11, and the gate insulating film 8 at the bottom of the trench 28 is removed. The main surface of the substrate 1S is exposed. Due to the formation of the sidewall 16, the dimension (width) of the groove 28 in the second direction Y is, for example, about 65 nm. If the boron introduction process is not performed, the boron introduction process can be performed after the sidewall 16 is formed.

  Here, the process of forming the sidewall 16 will be specifically described. 18A and 18B are explanatory diagrams of the formation process of the sidewall 16, in which FIG. 18A is a schematic diagram showing an enlarged main part of FIG. 11, and FIG. 18B is a schematic diagram before the sidewall 16 is formed following FIG. FIG. 4C is a diagram showing the ratio of silicon and oxygen in the A direction in the sidewall 16.

  When a silicon oxide film to be the sidewall 16 is deposited on the substrate 1S so as to cover the auxiliary gate electrode 4G by the CVD method using a mixed gas containing monosilane and oxygen using the same CVD apparatus, the oxygen is gradually increased. The gas flow rate is adjusted so that the supply amount of silicon increases, in other words, the gas flow rate is adjusted so that the silicon supply amount decreases with time.

  In the present embodiment, as shown in FIG. 18C, the silicon ratio contained in the lower side wall 16 (lowermost layer 16a) is increased, and the silicon ratio contained in the upper side wall 16 (uppermost layer 16c). Is low. The silicon ratio contained in the intermediate sidewall 16 (intermediate layer 16b) is set to an intermediate value between the lower sidewall 16 (lowermost layer 16a) and the upper sidewall 16 (uppermost layer 16c).

  For this reason, as shown in FIG. 18B, the silicon oxide film (the lowermost layer 16a) deposited earlier contains a large amount of silicon, and the silicon oxide film deposited later (the uppermost layer 16c) contains oxygen. Many will be included. That is, more silicon is contained in the lower layer than the upper layer of the silicon oxide film to be the sidewall 16. In addition, since the supply amount of oxygen increases with time, the silicon oxide film to be the sidewall 16 has a concentration distribution in which silicon decreases from the lower layer to the upper layer.

  When the silicon oxide film to be the sidewall 16 in which the composition of silicon and oxygen is changed is anisotropically dry-etched, as shown in FIG. The etching rate gradually decreases to the layer 16b and the lowermost layer 16c rich in silicon, and the etching can be stopped before the substrate 1S is cut. In addition, since the substrate 1S can be prevented from being scraped, the characteristics of the tunnel insulating film 15 formed thereafter, that is, the characteristics and reliability of the memory cell MC can be improved.

  Note that Patent Document 2 (Japanese Patent Laid-Open No. 11-163337) discloses a structure in which a protective insulating film containing excess silicon is formed on a substrate and on a bottom surface of a sidewall and a diffusion layer. Unlike the silicon dioxide film, this protective insulating film is used to transmit boron impurities well. On the other hand, in the embodiment of the present invention, as shown in FIG. 18, the sidewall 16 made of a silicon oxide film containing excess silicon is formed in the lower layer portion, and the sidewall 16 is formed. A silicon oxide film containing excess silicon is not formed on the non-substrate 1S, and the substrate 1S is exposed. Further, as described above, the silicon oxide film (sidewall 16) containing a large amount of silicon in the lower layer is different in that it is used to prevent the substrate 1S from being scraped when the sidewall 16 is formed by etching.

  Subsequently, as shown in FIG. 12, by subjecting the substrate 1S (wafer) to a thermal oxidation treatment such as an ISSG oxidation method, for example, oxidation is performed on the main surface of the substrate 1S at the bottom of the groove 28, for example. After forming an insulating film made of silicon, heat treatment (oxynitriding treatment) is performed in a gas atmosphere containing nitrogen (N), so that nitrogen is segregated at the interface between the insulating film and the substrate 1S to form the bottom of the trench 28. Then, a tunnel insulating film 15 made of silicon oxynitride (SiON) is formed. This insulating film 15 is a film that functions as a tunnel insulating film of the memory cell MC, and the thickness thereof is a silicon dioxide equivalent film thickness, for example, about 9 nm.

  Subsequently, a conductor film 6 made of, for example, low-resistance polycrystalline silicon is deposited on the main surface of the substrate 1S by a CVD method or the like.

  Subsequently, as shown in FIG. 13, the conductor film 6 on the entire main surface of the substrate 1S is subjected to an etch back process or a chemical mechanical polishing (CMP) process by an anisotropic dry etching method. . The conductor film 6 is left only in the trench 28 by the etch back process or the CMP process.

  Subsequently, as shown in FIG. 14, a resist pattern (not shown) is formed such that the memory area (area where the memory cell MC group is arranged) is exposed on the main surface of the substrate 1S (wafer) and the other areas are covered. After that, using this as an etching mask, the insulating films 11 and 16 exposed therefrom are etched by a dry etching method or the like. At this time, the silicon nitride cap film 10 is used as an etching stopper by increasing the etching selection ratio between silicon oxide and silicon and silicon nitride so that silicon oxide is easier to remove than silicon and silicon nitride. In addition, the insulating films 11 and 16 made of silicon oxide are selectively removed. As a result, a groove 29 is formed between adjacent conductor films 6 in the second direction Y.

  Subsequently, as shown in FIG. 15, an insulating film made of, for example, silicon oxide, an insulating film made of silicon nitride, and an insulating film made of silicon oxide are sequentially formed on the main surface of the substrate 1S (wafer) from the lower layer by the CVD method or the like. By depositing, an ONO film 18 for an interlayer film is formed.

  Subsequently, a refractory metal silicide such as tungsten silicide is formed on the ONO film 18 of the substrate 1S as a conductor film 5a made of, for example, low-resistance polycrystalline silicon and a conductor film 5b having a resistance lower than that of the conductor film 5a. A film is deposited sequentially from the lower layer by a CVD method or the like. The conductor films 5a and 5b are patterned in a subsequent process to form the word line 5 of the memory cell MC. The conductor film 5a has a thickness of about 100 to 150 nm, for example, and the conductor film 5b made of a refractory metal silicide film has a thickness of about 100 nm, for example.

  Subsequently, an insulating film 13 made of, for example, silicon oxide is deposited on the conductor film 5b by a CVD method using TEOS gas or the like. After patterning the laminated film deposited in this order on the insulating film 13 in the order of a hard mask film (not shown) and an antireflection film (not shown), the insulating film 13 exposed from the laminated film is used as an etching mask. The conductor film 5b and the conductor film 5a are etched. Thereby, a plurality of planar belt-like word lines 5 extending in the second direction Y of FIG. 1 are formed.

  Subsequently, as shown in FIG. 16, the conductive film 4 for forming the auxiliary gate electrode remaining in the peripheral circuit region is patterned by the photolithography technique and the dry etching technique, so that the MIS of the peripheral circuit is formed in the peripheral circuit area. Gate electrodes 4A and 4B are formed. At the time of this patterning, the excessive gate insulating film 8 is also removed, and the gate insulating film 8 remains only under the gate electrodes 4A and 4B.

Subsequently, as shown in FIG. 17, ion implantation is performed from the exposed main surface side of the substrate 1S using a photoresist pattern (not shown) having an opening in a region where nMISQn for the peripheral circuit is formed. An n ⁻ type semiconductor region 32a for the source and drain of nMISQn for the circuit is formed. Further, using a photoresist pattern (not shown) having an opening in the region where the pMISQp for the peripheral circuit is formed, a p ⁻ type drain for the drain of the pMIS source for the peripheral circuit is formed from the exposed main surface side of the substrate 1S. A semiconductor region 33a is formed.

  Subsequently, after an insulating film made of a silicon oxide film is deposited on the main surface of the substrate 1S (wafer) by, for example, a CVD method using TEOS gas, the insulating film is etched back by an anisotropic dry etching method or the like. Thus, sidewalls made of the insulating film are formed on the sidewalls of the gate electrodes 4A and 4B.

  Here, the step of forming the sidewall 17 can be performed in the same manner as the step of forming the sidewall 16 described above.

  When a silicon oxide film to be the sidewall 17 is deposited on the substrate 1S so as to cover the gate electrodes 4A and 4B by the CVD method using a mixed gas containing monosilane and oxygen using the same CVD apparatus, the time passes. The gas flow rate is adjusted so that the supply amount of oxygen increases. Thus, the silicon oxide film deposited earlier contains a lot of silicon, and the silicon oxide film deposited later contains a lot of oxygen. That is, more silicon is contained in the lower layer than the upper layer of the silicon oxide film to be the sidewall 17. Further, since the supply amount of oxygen increases with time, the silicon oxide film to be the sidewall 17 has a concentration distribution in which silicon decreases from the lower layer to the upper layer.

  When the silicon oxide film to be the sidewall 17 whose composition of silicon and oxygen is changed is subjected to anisotropic dry etching, the etching rate is gradually reduced from the upper layer with less silicon to the lower layer with much silicon, and the substrate The etching can be stopped before cutting 1S. As described above, in this embodiment, since the substrate 1S can be prevented from being scraped, the leakage current in the semiconductor regions 32b and 33b formed thereafter can be reduced. That is, the reliability of the semiconductor device can be improved.

Subsequently, an n ⁺ type semiconductor region 32b for the source and drain of nMISQn for the peripheral circuit and a p ⁺ type semiconductor region 33b for the drain of the source of pMISQp are formed separately. Specifically, first, an n-type impurity is ion-implanted from the exposed main surface side of the substrate 1S using a photoresist pattern (not shown) having an opening in a region where nMISQn for peripheral circuits is formed. Also, p-type impurities are ion-implanted from the exposed main surface side of the substrate 1S using a photoresist pattern (not shown) having an opening in a region where the pMISQp for peripheral circuits is formed. Thereafter, activation annealing of n-type and p-type impurity ions is performed in an oxygen atmosphere to form an n ⁺ -type semiconductor region 32b and a p ⁺ -type semiconductor region 33b.

At this time, the silicon ratio contained in the lower layer of the sidewall 17 containing a large amount of silicon (the portion corresponding to the sidewall 16a in FIG. 18A) is larger than the silicon ratio contained in the upper layer of the sidewall 17, Excess silicon is oxidized by the annealing process in an oxygen atmosphere, and the composition is close to that of the silicon oxide film SiO ₂ . For this reason, the insulation of the lower layer of the sidewall 17 can be improved.

  As described above, since the semiconductor regions 32b and 33b can be formed without the substrate 1S being scraped, the leakage current in the semiconductor regions 32b and 33b can be reduced. That is, the reliability of the semiconductor device can be improved.

  Further, due to the annealing process when forming the semiconductor regions 32b and 33b, excess silicon is oxidized in the lower layer of the sidewall 17 containing a large amount of silicon. For this reason, the insulation of the sidewall 17 can be improved. That is, the reliability of the semiconductor device can be improved.

Thereafter, a metal film such as cobalt (Co) or Ni (nickel) is deposited on the surfaces of the gate electrode 11 of the nMISQn for the peripheral circuit and the n ⁺ type semiconductor region 32b for the source and drain, and these metal films are deposited. By reacting with silicon contained in the semiconductor substrate or the gate electrode, a metal silicide film (metal compound film) such as a CoSi ₂ (cobalt silicide) film or a NiSi (nickel silicide) film is formed.

In this embodiment, since the chipping of the substrate 1S can be made extremely small, the metal silicide layer and the semiconductor substrate 1S (here, the well PW1), which is one of the problems of the present application as shown in FIG. It is possible to reduce the possibility of occurrence of leak current between the two.
The same effect is also obtained for the gate electrode 11 of pMISQp and the p ⁺ -type semiconductor region 33b for the drain of the source.

  Thereafter, the semiconductor device including the flash memory shown in FIGS. 1 to 4 is completed through a normal wiring formation process.

  The flash memory manufactured through such a manufacturing process can ensure reliability. FIG. 19 is a characteristic diagram showing a change in detrapping with respect to the remaining film thickness monitor. The film thickness monitor remaining film is the QC value of the film thickness monitor pattern of the product wafer. That is, FIG. 18 shows the remaining film amount of the stacked film of the silicon oxide film to be the sidewall 16 and the silicon oxide film to be the gate insulating film 8 on the substrate 1S after the dry etching.

  As shown in FIG. 19, the flash memory (see FIG. 21) studied by the present inventors described above has a large detrapping voltage value (ΔVth) as the film thickness monitor remaining film value becomes smaller. It has deteriorated. That is, the reliability of the flash memory is reduced.

  As shown in FIGS. 20 and 21, the surface of the substrate 1S is shaved in the cross section of the memory cell having the flash memory examined by the present inventors when the film thickness monitor residual film value is 0 nm. I was able to observe. That is, since the film thickness monitor residual film on the horizontal axis in FIG. 19 is an actually measured value of the film thickness monitor pattern, the substrate 1S is already exposed in the actual memory cell even if this pattern is displayed as the number of remaining film nm. Alternatively, it is conceivable that the detrapping voltage value (ΔVth) increases as the substrate is scraped.

  However, the flash memory according to the present invention shows a constant detrapping voltage value regardless of the change in the film thickness monitor remaining film value. That is, the reliability of the flash memory can be ensured.

  Specifically, when the silicon oxide film to be the sidewall 16 contains more silicon in the lower layer than the upper layer, the etching rate is reduced, and the etching can be easily stopped on the surface of the substrate 1S. That is, the substrate 1S can be prevented from being scraped, and the reliability of the flash memory can be ensured.

  In the case of multi-level writing, in the flash memory studied by the present inventors, the threshold voltage distribution becomes narrower and cannot be written in multi-level. This cause also shows a close relationship with the substrate scraping at the time of etching, and the flash memory of the present invention that prevents the substrate scraping can be written in multiple values.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, in the above-described embodiment, the case where the present invention is applied to an AND type flash memory alone has been described. However, the present invention is not limited to this. For example, a system LSI (Large Scale Integrated circuit) having an EEPROM alone semiconductor device, EEPROM, or flash memory. The present invention can also be applied to memory-embedded semiconductor devices such as

  Further, for example, in the above-described embodiment, the case where the silicon oxide film serving as the sidewall has a concentration distribution in which silicon decreases from the lower layer to the upper layer has been described. However, if the lower layer contains a large amount of silicon, the upper layer May have either more or less silicon, and layers containing more or less silicon may be alternately stacked. However, in order to shorten the etching time for forming the sidewall and prevent the semiconductor substrate from being scraped, it is preferable to apply a silicon oxide film having a concentration distribution in which silicon decreases from the lower layer to the upper layer.

  In addition, for example, a plug for electrically connecting the lower layer electrode of the phase change memory and the substrate can be formed on a flat substrate with no substrate shaving. That is, by applying the present invention to the sidewall of the selected MIS transistor of the phase change memory cell, the substrate can be prevented from being scraped and the substrate surface on which the plug is formed can be planarized. Thereby, the leakage current can be reduced, and the write / erase characteristics can be improved.

  The present invention is widely used in the manufacturing industry for manufacturing semiconductor devices.

It is a principal part top view of the semiconductor device which is one embodiment of this invention. It is sectional drawing of the Y1-Y1 line | wire of FIG. It is sectional drawing of the X1-X1 line | wire of FIG. It is sectional drawing of the X2-X2 line | wire of FIG. It is sectional drawing which shows typically the principal part of the flash memory at the time of operation | movement. FIGS. 2A and 2B are cross-sectional views schematically showing a main part of the semiconductor device in the manufacturing process taken along the line Y1-Y1 in FIG. 1, wherein FIG. FIG. 7 is a cross-sectional view schematically showing main parts of the semiconductor device in the manufacturing process following FIG. 6. FIG. 8 is a cross-sectional view schematically showing the main part of the semiconductor device in the manufacturing process following FIG. 7. FIG. 9 is a cross-sectional view schematically showing main parts of the semiconductor device in the manufacturing process following FIG. 8. FIG. 10 is a cross-sectional view schematically showing main parts of the semiconductor device in the manufacturing process following FIG. 9. FIG. 11 is a cross-sectional view schematically showing main parts of the semiconductor device in the manufacturing process following FIG. 10. FIG. 12 is a cross-sectional view schematically showing main parts of the semiconductor device in the manufacturing process following FIG. 11. FIG. 13 is a cross-sectional view schematically showing main parts of the semiconductor device in the manufacturing process following FIG. 12. FIG. 14 is a cross-sectional view schematically showing main parts of the semiconductor device in the manufacturing process following FIG. 13. FIG. 15 is a cross-sectional view schematically showing main parts of the semiconductor device in the manufacturing process following FIG. 14. FIG. 16 is a cross-sectional view schematically showing main parts of the semiconductor device in the manufacturing process following FIG. 15. FIG. 17 is a cross-sectional view schematically showing main parts of the semiconductor device in the manufacturing process following FIG. 16. It is explanatory drawing of the formation process of a side wall, (a) is a schematic diagram which expands and shows the principal part of FIG. 11, (b) is a density | concentration distribution map of the silicon | silicone and oxygen in a side wall. It is a characteristic view which shows the change of the detrap with respect to a film thickness monitor residual film. It is sectional drawing which shows typically the principal part of the flash memory in the manufacturing process which the present inventors examined. FIG. 21 is a cross-sectional view schematically showing main parts of the semiconductor device in the manufacturing process following FIG. 20. It is sectional drawing which shows typically the principal part of the field effect transistor which the present inventors examined.

Explanation of symbols

1S Semiconductor substrate (substrate)
2 Active region 3 Isolation region 4 Conductive film 4A, 4B Gate electrode 4G Auxiliary gate electrode 4GA Wide region 4LA, 4LB, 4LC Wiring 4LC1 Gate electrode 5, WL0, WL1 Control gate electrode (word line)
5a Conductive film 5b Conductive film 6 Conductive film 6G Floating gate electrode 7 Semiconductor region 8 Gate insulating film 10 Cap films 11, 12, 13 Insulating film 15 Tunnel insulating film 16 Side wall (insulating film)
16a Bottom layer 16b Intermediate layer 16c Top layer 17 Side wall (insulating film)
18 ONO film 21 Gate insulating film 22a Semiconductor regions 22b, 22b1, 22b2 Semiconductor regions 23a, 23b, 23c Inversion layer 25 Insulating film 26a Hard mask film 27a Antireflection film 28, 29 Grooves 32a, 32b, 33a, 33b Semiconductor region 34 Silicide Layer 109 Scraped portion 116, 117 Side wall AG, AG0 to AG3 Auxiliary gate electrode CD Common drain wiring CT Contact hole MC, MC0 Nonvolatile memory cell NISO Buried region NW1 Well PG Plug PW1 Well Qsn Select n-channel MISFET
RP photoresist pattern

Claims (9)

A gate electrode provided on the main surface of the semiconductor substrate via a gate insulating film;
A semiconductor device having a sidewall provided on a sidewall of the gate electrode,
The sidewall is formed by etching back a silicon oxide film formed on the main surface of the semiconductor substrate so as to cover the gate electrode.
2. The semiconductor device according to claim 1, wherein the silicon oxide film contains more silicon in a lower layer than an upper layer of the silicon oxide film.   2. The semiconductor device according to claim 1, wherein the silicon oxide film has a concentration distribution in which silicon decreases from a lower layer to an upper layer of the silicon oxide film. The silicon oxide film is laminated,
2. The semiconductor device according to claim 1, wherein the lowermost layer of the silicon oxide film contains more silicon than layers other than the lowermost layer. (A) forming a gate electrode on the gate insulating film after forming a gate insulating film on the main surface of the semiconductor substrate;
(B) forming a silicon oxide film on the main surface of the semiconductor substrate by a CVD method using a mixed gas containing monosilane and oxygen so as to cover the gate electrode;
(C) etching back the silicon oxide film to form a sidewall on the side wall of the gate electrode;
A method of manufacturing a semiconductor device including:
In the formation of the silicon oxide film in the step (b), the supply amount of oxygen increases with the passage of time.   5. The method of manufacturing a semiconductor device according to claim 4, wherein the step (b) is performed using the same CVD apparatus. (D) a step of implanting ions into the main surface of the semiconductor substrate exposed by the etch back in the step (c);
The method of manufacturing a semiconductor device according to claim 4, further comprising: (E) a step of performing activation annealing of the ions in an oxygen atmosphere after the step (d);
The method of manufacturing a semiconductor device according to claim 6, further comprising: A plurality of first electrodes provided on a semiconductor substrate;
A plurality of second electrodes provided on the semiconductor substrate so as to intersect the plurality of first electrodes;
A plurality of third electrodes for charge storage provided between adjacent ones of the plurality of first electrodes and at a position where the plurality of second electrodes overlap in a plane;
A first insulating film provided between the first electrode and the semiconductor substrate;
A second insulating film provided between the third electrode and the semiconductor substrate;
A third insulating film provided between the second electrode and the semiconductor substrate so as to cover the first electrode and the third electrode;
A method of manufacturing a semiconductor device comprising a plurality of nonvolatile memory elements having a sidewall of the first electrode provided between the third electrode and the first electrode,
(A) A silicon oxide film is formed on the main surface of the semiconductor substrate so as to cover the first electrode while increasing the supply amount of oxygen over time by a CVD method using a mixed gas containing monosilane and oxygen. Forming step,
(B) etching back the silicon oxide film to form the sidewall on the sidewall of the first electrode;
(C) forming the second insulating film on the main surface of the semiconductor substrate exposed by the etch back in the step (c);
A method for manufacturing a semiconductor device, comprising:   9. The method of manufacturing a semiconductor device according to claim 8, wherein the step (a) is performed using the same CVD apparatus.

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