JP2007272562A - Fifo memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a FIFO memory improved in data transmission efficiency. <P>SOLUTION: The memory comprises a dual port RAM (110) as storing means having a first access port to be operated in synchronization with a first clock signal and a second access port to be operated in synchronization with a second clock signal, a write pointer producing circuit (120) as write pointer producing means for producing a write pointer based on a write signal to be inputted to the first access port, a read pointer producing circuit (150) as read pointer producing means for producing a read pointer based on a read signal to be inputted to the second access port, and a full/empty determining circuit (140) as determining means for determining a storage area of the storing means to be full when difference between the write pointer and the read pointer becomes not larger than a predetermined margin. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a FIFO memory using a dual port RAM capable of performing read / write operations with mutually asynchronous clocks.

  In general, a FIFO memory is composed of a RAM for storing data and an address arithmetic circuit for managing a write pointer and a read pointer, and transfers data between two devices operating with asynchronous clocks. It is used as an interface when performing. For this reason, the FIFO memory is often realized by using a dual port RAM into which a write clock and a read clock can be input.

FIG. 4 shows a configuration of the FIFO memory 200 using the dual port RAM 210.
In the figure, the dual port RAM 210 includes a first access port that operates in synchronization with the clock signal CLK0 and a second access port that operates in synchronization with the clock signal CLK1. Reference numeral 220 is a wait signal generation circuit, reference numerals 230, 250, and 280 are synchronization circuits, reference numeral 240 is a write pointer generation circuit, reference numeral 260 is a full / empty determination circuit, and reference numeral 270 is a read pointer generation circuit.

  A write signal WR and write data WD15 to WD0 are input from a bus master device such as a CPU to the first access port of the dual port RAM 210, and write address signals WA7 to WA0 are transmitted from the write pointer generation circuit 240 via the synchronization circuit 250. Is entered. On the other hand, the read signal RD is input from the external peripheral device to the second access port of the dual port RAM 210, and the read address signals RA 7 to RA 0 are input from the read pointer generation circuit 270. Also, read data RD15 to RD0 are output from the second access port to the peripheral device.

Next, a write operation based on a request from the bus master device will be described with reference to a timing chart shown in FIG.
First, when the bus master device asserts the write signal WR to the low level at the rising edge of the clock signal CLK0 at time t1, the wait signal generation circuit 220 receives this, and the wait signal generation circuit 220 receives the clock signal CLK0 at the next time t2. The wait signal WAT is asserted to a high level at the rising edge. Thereafter, writing by the bus master device is prohibited until the wait signal WAT is negated.

  The wait signal generation circuit 220 outputs the asserted write signal WR to the synchronization circuit 230. The synchronization circuit 230 takes in the asserted write signal WR at the rising edge of the clock signal CLK1 at the time t3, and is synchronized with the clock signal CLK1 at the rising edge of the clock signal CLK1 at the next time t4. Write signal WRS is output. The write pointer generation circuit 240 updates and outputs the pointer Pw with the write signal WRS at the rising edge of the clock signal CLK1 at time t5.

  On the other hand, the read pointer generation circuit 270 generates the read pointer Pr from the read signal RD supplied from the peripheral device. In this example, the read signal RD is not asserted, and the read pointer Pr maintains the head address “0”. The full / empty determination circuit 260 calculates the remaining storage area of the dual port RAM 210 from the updated write pointer Pw and read pointer Pr described above, and determines whether the storage area is full from the calculation result. To do. In this example, it is determined that the clock signal CLK1 is not full at the rising edge of the clock signal CLK1 at time t5.

  If it is determined that the storage area is not full, the full / empty determination circuit 260 asserts the acknowledge signal Ack1 representing the determination result to a high level at the rising edge of the clock signal CLK1 at time t6 to synchronize the circuit 280. Output to. The synchronization circuit 280 synchronizes the acknowledge signal Ack1 with the clock signal CLK0 at the rising edge of the clock signal CLK0 at time 7, and outputs the acknowledge signal Ack0.

The wait signal generation circuit 220 to which the acknowledge signal Ack0 is input negates the wait signal to the low level at the rising edge of the clock signal CLK0 at the next time t8. Upon receiving this wait signal, the bus master device negates the write signal WR to the high level at the rising edge of the clock signal CLK0 at the next time t9, thereby completing a series of write operations.
JP-A-8-17180

  By the way, according to the above-described prior art, it is necessary to synchronize the update of both the write pointer Pw and the read pointer Pr with the read clock signal CLK1. This is because, in order to correctly determine whether or not the storage area of the dual port RAM 210 is full in the full / empty determination circuit 140, the write pointer and the read pointer are updated at the same timing, and the positional relationship between the two pointers is updated. This is because it is necessary to grasp.

  However, synchronizing the update of both the write pointer Pw and the read pointer Pr with the read clock signal CLK1 means delaying the write signal WR for obtaining the write pointer Pw, and therefore full / empty. There is a problem that a predetermined latency is required before the determination circuit 260 outputs the determination result.

  Specifically, when updating both pointers with the read clock signal CLK1, there is a time lag in updating the write pointer Pw. This is because it is necessary to synchronize the write signal WR with the read clock signal CLK1 by the synchronization circuit 230 when the write pointer Pw is updated. The time lag generated at the time of synchronization brings about a latency in determining the full / empty state, and causes a decrease in data transfer efficiency. In the example shown in FIG. 5 described above, eight cycles are required from when the wait signal WAT is asserted to when it is negated, that is, until data is transferred from the first access port to the second access port.

  The present invention has been made in view of the above circumstances, and an object thereof is to provide a FIFO memory capable of improving data transfer efficiency.

  A FIFO memory according to the present invention comprises a storage means having a first access port that operates in synchronization with a first clock signal and a second access port that operates in synchronization with a second clock signal; Write pointer generating means for generating a write pointer based on an input write signal, read pointer generating means for generating a read pointer based on a read signal input to the second access port, and the write pointer and the read pointer Determination means for determining that the storage area of the storage means is full when the difference is equal to or less than a preset margin.

In the FIFO memory, for example, the write pointer generation unit synchronizes the write pointer with the second clock signal and outputs the result to the determination unit.
In the FIFO memory, for example, the read pointer generation unit synchronizes the read pointer with the first clock signal and outputs the result to the determination unit.

In the FIFO memory, for example, the margin is a change amount of the write pointer in a period from when the write pointer generation unit generates a write pointer to when the determination result of the determination unit based on the write pointer is output. It is characterized by being set accordingly.
In the FIFO memory, for example, the storage means is a dual port RAM.

  According to the present invention, a fixed margin is provided between the write pointer and the read pointer, and it is determined whether or not the storage area is full based on the write pointer and the read pointer. It is possible to effectively suppress the occurrence of latency when determining whether or not it is full, and to improve data transfer efficiency.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 shows a configuration of a FIFO memory 100 according to an embodiment of the present invention.
In the figure, reference numeral 110 denotes a dual port RAM. The dual port RAM 110 includes a first access port 1100 that operates in synchronization with a clock signal CLK0 of a bus master device such as a CPU, and a second access port 1101 that operates in synchronization with a clock signal CLK1 of a peripheral device.

  Here, in addition to the clock signal CLK0, the first access port 1100 receives a write signal WR and write data WD15 to WD0 from a bus master device (not shown), and a write address signal WA7 from a write pointer generation circuit 120 described later. ~ WA0 is input. On the other hand, in addition to the clock signal CLK1, a read signal RD is input from a peripheral device (not shown) to the second access port 1101, and read address signals RA7 to RA0 are input from a read pointer generation circuit 150 described later. Further, read data RD15 to RD0 are output from the second access port 1101 to the peripheral devices.

  Reference numeral 120 denotes a write pointer generation circuit for generating a write pointer Pw indicating the write position of the dual port RAM 110. A write signal WR is input to the write pointer generation circuit 120. The write pointer generation circuit 120 supplies the write pointer Pw to the first access port 1100 of the dual port RAM 110 as the write addresses WA7 to WA0.

Reference numeral 130 denotes a synchronization circuit, which is composed of two cascaded D flip-flops. Among them, the write pointer Pw is input to the first stage D flip-flop, and the write pointer Pws synchronized with the clock signal CLK1 is output from the second stage D flip-flop. The clock signal CLK1 is input to each of the clock terminals.
Reference numeral 150 denotes a read pointer generation circuit for generating a read pointer Pr indicating the read position of the dual port RAM 110. A read signal RD is input to the read pointer generation circuit 150.

  Reference numeral 140 denotes a full / empty determination circuit that determines whether or not the storage area of the dual port RAM is full from the synchronized write pointer Pws and read pointer Pr. The full / empty determination circuit 140 forms one of the main features of the present invention, and provides a certain margin between the write pointer Pws and the read pointer Pr, and based on these pointers, the dual port RAM It is determined whether or not the storage area is full. This determination result is output as a determination signal JUD to the peripheral device, and also output as a wait signal WAT1 to a synchronization circuit 160 described later. Note that the above-described certain margin provided between the write pointer Pws and the read pointer Pr in this determination will be described later.

  Reference numeral 160 denotes a synchronization circuit, which is configured by two stages of D flip-flops connected in cascade as in the above-described synchronization circuit 130. However, the clock signal CLK0 is input to each clock terminal of these two-stage D flip-flops, and among these, the wait signal WAT1 is input to the first-stage D flip-flop, and the second-stage D flip-flops The wait signal WAT synchronized with the clock signal CLK0 is output to the external bus master device.

Next, referring to FIG. 2, the determination method in the full / empty determination circuit 140 and the above-described fixed margin M provided between the write pointer Pws and the read pointer Pr at the time of the determination are as follows. The comparison will be described.
FIG. 2 shows an example of the relationship between the storage area of the dual port RAM 110 and each pointer when full determination is made. In the example shown in the figure, the storage area of the dual port RAM 110 constitutes a storage area of a total of N stages of FIFO memories from the 0th stage to the (N-1) th stage.

  Here, FIG. 2A is a diagram for explaining the above-described constant margin according to the present embodiment. When the write pointer Pws indicates the NM-1 stage, the read pointer Pr is This represents a state indicating the 0th stage (first stage). FIG. 4B is a diagram for explaining the relationship between the write pointer Pw and the read pointer Pr in the prior art. When the write pointer Pw indicates the (N−1) th stage, the read pointer Pr is The state showing the 0th stage is shown.

  First, according to the prior art, in the case of Pw> Pr as shown in FIG. 2B, when the relationship Pw−Pr = N−1 is satisfied, the storage area of the FIFO memory becomes full and full. A decision is made. Although not shown, when Pw <Pr, if the relationship of Pr−Pw = 1 is satisfied, the storage area of the FIFO memory is full and a full determination is made. That is, in the conventional technique, the full determination is made when the write pointer Pw has completely caught up after the read pointer Pr (there is no empty storage area).

  On the other hand, in this embodiment, as shown in FIG. 2A, when the relationship Pw−Pr ≧ NM is satisfied when Pws> Pr, the storage area of the FIFO memory is actually full. Even if it is not, full judgment is made. Although not shown, if the relationship of Pr−Pw ≦ M is satisfied when Pws <Pr, the full determination is similarly made even if the storage area of the FIFO memory is not full.

That is, in the present embodiment, the full determination is made when the difference between the read pointer Pr and the write pointer Pws chasing the read pointer Pr becomes equal to or less than a predetermined margin M. How to set the margin M will be described later.
The full determination method and the margin M in the present embodiment have been described above.

Next, with reference to the timing chart shown in FIG. 3, the operation of this embodiment will be described by taking a write operation based on a request from the bus master device as an example.
As will be described below, according to the present embodiment, the bus master device does not have to wait for a full determination for each write operation, and thus can perform a write operation in the burst mode. Therefore, here, a case where the bus master device writes data to the dual port RAM 110 in the burst mode will be described.

  First, in FIG. 3, when the bus master device asserts the write signal WR to the low level and starts the write operation in the burst mode at the rising edge of the clock signal CLK0 at the time t1, the write pointer generation circuit 120 thereafter The write pointer Pw is counted up and updated every cycle of the clock signal CLK0, and “1”, “2”,..., “17” are sequentially output as the value of the write pointer Pw. The write pointer generation circuit 120 supplies write address signals WA7 to WA0 to the first access port of the dual port RAM 110 as the write pointer Pw.

  The dual port RAM 110 receives write data WD15 to WD0 from the bus master device in each cycle of the clock signal CLK0, and stores it in the storage area specified by the write address signals WA7 to WA0 supplied from the write pointer generation circuit 120 as the write pointer Pw. Store sequentially.

  The synchronization circuit 130 synchronizes the write pointer Pw with the clock signal CLK1, and outputs the write pointer Pws to the full / empty determination circuit 140 at a timing synchronized with the clock signal CLK1. Specifically, the synchronization circuit 130 captures the value “2” of the write pointer Pw at the rising edge of the clock signal CLK1 at time t2, and uses it as the write pointer Pws at the rising edge of the clock signal CLK1 at the next time t3. The value “2” is output.

  Thereafter, similarly, the synchronization circuit 130 captures each value of the write pointer Pw at the rising edge of the clock signal CLK1, and “3”, “5”, “7” are written as the write pointer Pws synchronized with the clock signal CLK1. , “8”, “10”, “11”, “12”, “14”, “15”, “17” are sequentially output to the full / empty determination circuit 140.

  On the other hand, the read pointer generation circuit 150 generates a read pointer Pr based on the read signal RD supplied from the peripheral device and outputs the read pointer Pr to the full / empty determination circuit 140. Further, the read pointer generation circuit 150 supplies read address signals RA7 to RA0 to the second access port 1101 of the dual port RAM 110 as the read pointer Pr. The dual port RAM 110 outputs the data stored in the storage area specified by the write address signals WA7 to WA0 supplied from the write pointer generation circuit 120 to the peripheral device as read data RD15 to RD0.

  As the write operation by the bus master device on the first access port side proceeds, the value of the write pointer Pw increases, and as the read operation by the peripheral device on the second access port side proceeds, the value of the read pointer Pr Increases to track the write pointer Pw.

  Here, in this embodiment, when the value of the write pointer Pw reaches “10”, it is assumed that the relationship between the write pointer Pw and the read pointer Pr becomes the relationship shown in FIG. That is, when the write pointer Pw becomes “10”, there is only a vacant area corresponding to the margin M between the read pointer Pr and the condition Pw−Pr ≧ NM is satisfied. And However, in this embodiment, full determination is not made at this point.

  From this state, at the rising edge of the clock CLK1 at time t5, the synchronization circuit 130 captures the value “11” of the write pointer Pw and outputs it as the write pointer Pws at time t6. The full / empty determination circuit 140 determines whether the storage area is full from the value “11” of the write pointer Pws and the value of the read pointer Pr. In this case, since the number of FIFO stages between the write pointer Pw and the read pointer Pr is equal to or less than the number of stages to be applied to the margin M, the full / empty determination circuit 140 makes a full determination and the rising edge of the clock signal CLK1 at time t7. At the edge, a determination signal JUD representing this determination result is output.

  The synchronization circuit 160 takes in the wait signal WAT1 at the rising edge of the clock signal CLK0 at time t8, and asserts the wait signal WAT to the high level at the rising edge of the clock signal CLK0 at the next time t9. In response, the external bus master device negates the write signal WR to the high level at the rising edge of the clock signal CLK0 at time t10, thereby completing the write operation in a series of burst modes.

  In the above-described series of ride operations in the burst mode, the condition (Pw−Pr ≧ NM) for making a full determination at time t4 before the full / empty determination circuit 140 outputs a full determination at time t7 is as follows. Satisfied. Moreover, the write signal WR is negated at time t10 after the full determination is made. Therefore, in this example, the value of the write pointer Pw has advanced to “17” even though the value of the write pointer Pw must be kept at “10”.

  However, according to the present embodiment, since the margin M described above is provided, the storage area of the dual port RAM 110 corresponds to the margin M even if the actual value of the write pointer Pw is advanced at the time of full determination. Since there is a free area to be overflowed, overflow does not occur. Therefore, the margin M represents a time lag for synchronizing the write pointer Pw with the clock signal CLK1, a time lag until the full decision is made from the synchronized write pointer Pws and the read pointer Pr, and a full decision. It is determined in consideration of a time lag for synchronizing the signal with the clock signal CLK0 and asserting the wait signal WAT, and a time lag until the external bus master device receiving the wait signal WAT negates the write signal WR. That is, the number of FIFO stages corresponding to the margin M is set so that all write data corresponding to this change can be stored in consideration of the change in the write pointer Pw during the time lag summing period as described above. In other words, the margin M is set according to the change amount of the write pointer in the period from when the write pointer is generated until the determination result is output.

  As described above, in this embodiment, the write pointer Pw is supplied to the dual port RAM 110 without being synchronized with the read clock signal CLK1, thereby enabling the write operation for each cycle of the write clock signal CLK0. Realizes high-speed write operation in burst mode. Therefore, the data transfer efficiency is improved. On the other hand, since the full determination is performed using the write pointer Pws obtained by synchronizing the write pointer Pw with the read clock signal CLK1, the value of the write pointer Pws input by the full / empty determination circuit 140 is different from the actual value. Although an error occurs in full determination, overflow is avoided by providing full margin with the margin M described above. As a result, a high-speed write operation is realized without causing an overflow.

  In this example, since the cycle of the clock signal CLK1 is larger than that of the clock signal CLK0, the value of the write pointer Pws obtained by synchronizing the write pointer Pw with the clock signal CLK1 does not become a continuous value. This also causes a full determination error in the full / empty determination circuit 140. Even if this error exists, the margin M does not cause an overflow.

  As described above, in this embodiment, the write pointer Pw is generated in synchronization with the write clock signal CLK0, and the read pointer Pr is generated in synchronization with the read clock signal CLK1, thereby performing the write operation and the read operation. In addition to speeding up, the full determination error associated therewith is absorbed by the margin M.

  As mentioned above, although embodiment of this invention was explained in full detail, the concrete structure is not restricted to this embodiment, The design change etc. of the range which does not deviate from the summary of this invention are included. For example, in the above-described embodiment, the generation of the write pointer is synchronized with the clock signal CLK0, and the generation of the read pointer Pr and the full determination are synchronized with the clock signal CLK1 for read. May be synchronized with the clock signal CLK0, and the generation of the read pointer Pr may be synchronized with the read clock signal CLK1.

It is a block diagram which shows the structure of the FIFO memory which concerns on embodiment of this invention. It is explanatory drawing for demonstrating the margin in the case of full determination which concerns on embodiment of this invention. 3 is a timing chart for explaining the operation of the FIFO memory according to the embodiment of the present invention. It is a figure which shows the structural example of the FIFO memory which concerns on a prior art. 6 is a timing chart for explaining the operation of the FIFO memory according to the prior art.

Explanation of symbols

100; FIFO memory, 110; dual port RAM, 120; write pointer generation circuit, 130, 160; synchronization circuit, 140; full / empty determination circuit, 150; read pointer generation circuit.

Claims (5)

Storage means having a first access port that operates in synchronization with the first clock signal and a second access port that operates in synchronization with the second clock signal;
Write pointer generating means for generating a write pointer based on a write signal input to the first access port;
Read pointer generating means for generating a read pointer based on a read signal input to the second access port;
A FIFO memory comprising: a determination unit that determines that the storage area of the storage unit is full when a difference between the write pointer and the read pointer is equal to or less than a preset margin.   2. The FIFO memory according to claim 1, wherein the write pointer generation means synchronizes the write pointer with the second clock signal and outputs it to the determination means.   2. The FIFO memory according to claim 1, wherein the read pointer generation means synchronizes the read pointer with the first clock signal and outputs the result to the determination means.   The margin is set according to a change amount of the write pointer in a period from when the write pointer generation unit generates a write pointer to when a determination result of the determination unit based on the write pointer is output. 4. The FIFO memory according to claim 1, wherein the FIFO memory is characterized in that: 5. The FIFO memory according to claim 1, wherein the storage means is a dual port RAM.

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