JP2007134001A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a semiconductor integrated circuit device capable of greatly reducing a test time of a memory cell portion with a small number of additional circuits.
A semiconductor integrated circuit device according to the present invention includes an SRAM type memory cell 11a, a memory cell array in which the memory cells 11a are repeatedly arranged in the row and column directions, and a common connection for each column of the memory cell array. A pair of bit lines 12a and 12b for writing a typical data signal to the memory cell 11a or reading from the memory cell 11a, a word line WK commonly connected to each row of the memory cell array, and all the memory cell arrays during the test. A row decoder 13 that drives the word line WK to select a row, and is connected between the main power supply line and the power supply of the memory cell 11a, and is controlled to supply a smaller current to the memory cell 11a during a test read than during normal operation. Current limiting circuit 14 is provided.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor integrated circuit device having a memory circuit, and more particularly to a test of a memory cell portion in a liquid crystal display device having a display RAM.

  In a conventional #semiconductor integrated circuit device # having a large-scale memory cell unit, for example, a display RAM in a liquid crystal display device, a leakage current failure between adjacent memory cells in the memory cell unit is determined in an operation test during manufacturing. A test is performed. In general, this test includes an All “0” test for writing “0” to all memory cells, an All “1” test for writing “1” to all memory cells, and “0” and “1” for each row or column. And a checker test that writes “0” and “1” in a checkered pattern. In these tests, since it is necessary to determine whether the data written for each memory cell matches the read data, the test time tends to increase as the memory cell portion becomes larger. In particular, in the #semiconductor integrated circuit device # for liquid crystal displays equipped with a display RAM, the impact of this increase in the test time of the memory cell portion on the cost cannot be ignored as the definition and screen size have increased in recent years. There was a problem that.

In order to cope with such a problem, a means for writing data of all rows for each column at once, a built-in test circuit for determining data of all rows by one reading, and the like have been proposed. For example, in “Patent Document 1”, it is determined by a test circuit constituted by a plurality of EXOR (exclusive OR) circuits whether the data of all the rows read for each column coincide with each other. However, the method using such a test circuit is different from a DRAM type memory cell in that an SRAM type memory cell having no latch circuit for each row is used in addition to the problem that the chip size increases due to the test circuit. There was a problem that it was not applicable.
JP 2002-245798 A

  The present invention provides a semiconductor integrated circuit device that can significantly reduce the test time of a memory cell portion with a small number of additional circuits.

  According to one aspect of the present invention, a memory cell composed of a flip-flop circuit composed of two inverters and a pair of transfer gates connected to the flip-flop circuit, and the memory cell are repeatedly arranged in the row and column directions A memory cell array, a bit line pair that is connected to the transfer gate in common for each column of the memory cell array, and writes a complementary data signal to or from the memory cell, and for each row of the memory cell array A word line commonly connected to the control terminal of the transfer gate, a row decoder for driving the word line to select all the rows of the memory cell array at the time of testing, a main power supply line, and a power supply for the flip-flop circuit During normal operation during test readout The semiconductor integrated circuit device is provided which is characterized by having a current limiting means being controlled to provide less current Ri to the flip-flop circuit.

  According to another aspect of the present invention, a memory cell composed of a flip-flop circuit composed of two inverters and a pair of transfer gates connected to the flip-flop circuit, and the memory cells are repeatedly arranged in the row and column directions A memory cell array, a bit line pair connected to the transfer gate in common for each column of the memory cell array, for writing a complementary data signal to or reading from the memory cell, and the memory cell array A word line commonly connected to the control terminal of the transfer gate for each row; a row decoder for driving the word line to select an even row or an odd row of the memory cell array during a test; a main power supply line; Connected between the flip-flop circuit power supply and test reading The semiconductor integrated circuit device is provided which is characterized in that less current than during normal operation has a current limiting means is controlled to supply to the flip-flop circuit at the time to.

  According to the present invention, since memory cell defects in all rows can be determined with a small number of write and read operations for each column, the test time of the memory cell portion can be greatly shortened.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a circuit diagram showing a semiconductor integrated circuit device according to Embodiment 1 of the present invention. Here, a part of the Mth column in the memory cell array (FIG. 1 shows the Kth to (K + 2) th rows) and the part related to the data writing and data reading are mainly shown.

  The memory cell array is composed of memory cells arranged repeatedly in the row and column directions, and a plurality of word lines commonly connected to the memory cells for each row and a plurality of bits commonly connected to the memory cells for each column. Includes line pairs.

  The semiconductor integrated circuit device according to the first embodiment of the present invention includes SRAM type memory cells 11a to 11c and a pair of bit lines 12a and 12b for writing or reading data signals to / from the memory cells 11a to 11c for each column of the memory cell array. From the word line WK for selecting the memory cell 11a for each row of the memory cell array, the row decoder 13 for driving the word line WK, the current limiting circuit 14 for controlling the current to the memory cells 11a to 11c during the test, and the bus line 15 A write circuit 16 that writes data signals to the bit lines 12 a and 12 b and a read circuit 17 that outputs data signals from the bit lines 12 a or 12 b to the bus line 15 are provided.

  The first input / output of the memory cell 11a is connected to the bit line 12a, the second input / output is connected to the bit line 12b, the control input is connected to the word line WK, and the first power supply of the memory cell 11a is a current Connected to the output of the limiting circuit 14, the second power source is connected to a ground line (not shown in FIG. 1) for supplying a ground voltage (0V).

  A test signal (hereinafter referred to as “Test”) that is activated during a test is input to the first input of the row decoder 13, and an address signal for selecting a row of the memory cell array is input to the second input. The output of the row decoder 13 is connected to the word line WK. The input of the current limiting circuit 14 is connected to a main power supply line (not shown in FIG. 1) that supplies a high voltage (Vcc).

  The first and second inputs of the write circuit 16 are connected to the bus line 15, the first output of the write circuit 16 is connected to the bit line 12a, and the second output is connected to the bit line 12b. The first input of the read circuit 17 is connected to the bit line 12 a, the second input is connected to the bit line 12 b, and the first and second outputs of the read circuit 17 are connected to the bus line 15.

  Although not explicitly shown in FIG. 1, the memory cell 11b and the memory cell 11c are connected in the same manner as the memory cell 11a. The difference from the memory cell 11a is that the control inputs of the memory cells 11b and 11c are connected to different word lines, respectively, and are connected to dedicated row decoders.

  As shown in FIG. 1, the memory cell 11a is an SRAM cell including a flip-flop circuit composed of two inverters and two transfer gates. That is, the memory cell 11a includes two p-type MOS-FETs (hereinafter referred to as “MP11 and MP12”), two n-type MOS-FETs (hereinafter referred to as “MN11 and MN12”), and an n-type MOS−. It has two transfer gates (hereinafter referred to as “MNK1 and MNK2”) made of FETs.

  The source terminal of MP11 is connected to the output of the current limiting circuit 14 via the first power supply of the memory cell 11a, the drain terminal is connected to the gate terminal of MP12, and the source terminal of MP12 is the first power supply of the memory cell 11a. And the drain terminal is connected to the gate terminal of MP11.

  The source terminal of MN11 is connected to the ground line via the second power supply of the memory cell 11a, the drain terminal is connected to the drain terminal of MP11 and the gate terminal of MN12, and the source terminal of MN12 is the memory cell 11a. The drain terminal is connected to the drain terminal of MP12 and to the gate terminal of MN11.

  The drain terminal of MNK1 is connected to the bit line 12a, the source terminal is connected to the drain terminal of MP11, and the gate terminal is connected to the word line WK via the control input of the memory cell 11a. The drain terminal of MNK2 is connected to the bit line 12b, the source terminal is connected to the drain terminal of MP12, and the gate terminal is connected to the word line WK via the control input of the memory cell 11a.

  Memory cells 11b and 11c have the same configuration as memory cell 11a described above.

  Bit lines 12a and 12b are used complementarily as bit line pairs for writing or reading data signals to / from memory cells 11a to 11c. Although not shown in FIG. 1, all (N, K = 1 to N) memory cells arranged in the M columns of the memory cell array are connected to this bit line pair in the same manner as the memory cell 11a.

  The row decoder 13 includes a decoding unit (indicated by “AND21” in FIG. 1) to which a row address is input, and an OR 22 to which the output of the decoding unit and Test are input. During normal operation, Test = “L”, the output of the decoding unit is output as it is to the word line WK, and the word line is selectively driven based on the row address. On the other hand, Test = “H” during the test, and the word line WK is selectively driven regardless of the row address input to the decoding unit.

  Although not shown in FIG. 1, a row decoder similar to this is connected to the word line of each row of the memory cell array. The difference from the row decoder 13 is that the outputs of the decoding units based on the inputted row addresses are different. Therefore, at the time of the test, in the row decoders corresponding to all the rows, similarly, the word lines are selectively driven by the test, and as a result, the memory cells in all the rows are selected.

  The current limiting circuit 14 is inserted between the first power supply and the main power supply line of the memory cells 11a to 11c, and controls the cell current to the memory cells 11a to 11c during the test. That is, as shown in FIG. 1, in the current limiting circuit 14, a resistor R11 and a p-type MOS-FET (hereinafter referred to as “MP61”) are connected in parallel, and a read signal at the time of testing is connected to the gate terminal of the MP61. (Hereinafter referred to as “ΦRt”).

  As shown in FIG. 1, the writing circuit 16 includes one inverter 23 (hereinafter referred to as “INV23”) and two switch elements (hereinafter referred to as “MN31 and MN32”) including n-type MOS-FETs. Have.

  The drain terminal of MN31 is connected to the bus line 15 via the first input of the write circuit 16, the source terminal is connected to the bit line 12a via the first output of the write circuit 16, and the gate terminal of MN31 is A write signal ΦW is input. The input of INV23 is connected to the bus line 15 via the second input of the write circuit 16, and the output of INV23 is connected to the drain terminal of MN32. The source terminal of MN32 is connected to the bit line 12b via the second output of the write circuit 16, and ΦW is input to the gate terminal of MN31.

  With such a configuration, when ΦW is “H”, the write circuit 16 converts the data signal from the bus line 15 into two complementary signals and outputs them to the bit lines 12a and 12b, respectively.

  As shown in FIG. 1, the read circuit 17 includes two inverters 24 and 25 (hereinafter referred to as “INV 24 and 25”) that constitute a normal rotation buffer, and an inverter 26 that is an inverting buffer (hereinafter referred to as “INV 26”). And two switch elements (hereinafter referred to as “MN51 and MN52”) made of n-type MOS-FETs.

  The bit line 12a is connected to the input of the INV 24 via the first input of the readout circuit 17, the output of the INV 24 is connected to the input of the INV 25, the output of the INV 25 is connected to the drain terminal of the MN 51, and the source terminal of the MN 51 Is connected to the bus line 15 via the first output of the read circuit 17, and the first read signal ΦR1 is input to the gate terminal of the MN51.

  The bit line 12 b is connected to the input of the INV 26 via the second input of the readout circuit 17, the output of the INV 26 is connected to the drain terminal of the MN 52, and the source terminal of the MN 52 is connected to the second output of the readout circuit 17. The second read signal ΦR2 is input to the gate line of the MN26.

  With such a configuration, the read circuit 17 selectively outputs the data signal of the bit line 12a or the bit line 12b to the bus line 15 based on ΦR1 or ΦR2. Details of ΦR1 and ΦR2 will be described later with reference to FIG.

Next, a test operation of the semiconductor integrated circuit device having the above configuration will be described.
FIG. 2 is a waveform diagram showing a test operation of the semiconductor integrated circuit device according to the first embodiment of the present invention. Here, signal waveforms related to the All “1” test and the All “0” test of the Mth column shown in FIG. 1 are mainly shown.

  That is, in order to test a leak relationship between adjacent memory cells between columns, an address signal, a data signal (bus) when an All “1” test is performed in a period t1 and an All “0” test is performed in a period t2. Line 15 and bit line 12a) and control signals (Test, T1, T2, ΦW, ΦR1, and ΦR2) are shown.

ΦR1 and ΦR2 are generated by a logical operation of a read signal ΦR similar to that during normal operation and a control signal T1 indicating a period t1,
ΦR1 = T1 ・ ΦR
ΦR2 = / T1 ・ ΦR (1)
It is. Here, “/” represents logical negation, and “·” represents logical product.

Although not shown in FIG. 2, ΦRt input to the current limiting circuit 14 is
ΦRt = (T1 + T2) · ΦR (2)
It is. Here, T2 is a control signal indicating the period t2, and “+” represents a logical sum. Since ΦRt is input to the MP61 of the current limiting circuit 14, equation (2) means that the MP61 is turned OFF and the current limiting circuit 14 limits the current to the memory cell at the time of test reading.

  As shown in FIG. 2, in the test operation of the semiconductor integrated circuit device according to the first embodiment of the present invention, in order to write the data “1” to the memory cells in all the rows, first, the row decoder 13 at the beginning of the period t1. Test = “H” is input to the OR 22 of the memory to activate the word line WK, and MNK1 and MNK2 which are transfer gates of the memory cell 11a are turned on. In writing at the time of test, similarly, all the word lines are activated by Test, and the transfer gates of all the memory cells (K = 1 to N) including the memory cells 11b and 11c are turned on.

  Next, when ΦW is set to “H”, MN31 and MN32 of the write circuit 16 are turned ON, and data “1” of the bus line 15 is transmitted to the bit lines 12a and 12b. Then, data “1” is written to all the memory cells via MNK1 and MNK2 (K = 1 to N).

  By this writing, the internal node QN + of the memory cell 11a shown in FIG. 1 becomes “H” and QN− becomes “L”. Even when ΦW becomes “L”, the memory cell 11a holds the state until the next write operation unless the memory cell 11a has an abnormality.

  Next, when ΦR1 is set to “H”, the MN51 of the read circuit 17 is turned on, and the data “1” of the bit line 12a is output to the bus line 15 via the MN51 by the INVs 24 and 25.

  By the way, in the n-type MOS-FET, no current flows between the drain and the source unless the drain voltage or the source voltage is structurally lower than the gate voltage by a threshold value. Therefore, at the time of reading, the bit line 12a becomes Vcc-Vth by MNK1. The ON resistance value RV of MNK1 is generally a high value due to transistor size restrictions and the like.

Therefore, as shown in FIG. 1, the resistance value of R11 of the current limiting circuit 14 connected to the first power supply of the memory cell 11a is
R11> RV / (N-1) -R0 (3)
It is set to become. Here, R0 is the ON resistance value of MNK2, and N is the total number of memory cells connected to the bit lines 12a and 12b.

  If R11 is set as in the equation (3), it is possible to determine the malfunction of the memory cell by the INV 24 of the read circuit 17 connected to the bit line 12a. That is, even if one of the N memory cells malfunctions and QN + becomes 0 V and the bit line 12a is driven to the “L” side, the other (N−1) memory cells set the bit line 12a to “ Even if it is driven to the “H” side, the drive capability on the “L” side is superior by the expression (3), and as a result, the voltage of the bit line 12a is lowered to the level determined to be “L” by the INV 24.

  Therefore, the data signal output to the bus line 15 by the read circuit 17 is the reverse of the write operation, and the malfunction of the memory cell can be easily detected by one read.

  The All “0” test in the period t2 is executed in the same manner. The difference from the All “1” test is that the data to be written is “0”, the MN 52 is turned ON by ΦR 2 at the time of reading, and the data of the bit line 12 b determined by the INV 26 is output to the bus line 15 via the MN 52. It is to be done.

  In the All “0” test, “L” is written to QN + and “H” is written to QN−. Therefore, when the memory cell malfunctions, the voltage drop caused by the expression (3) occurs on the bit line 12b. become. For this reason, both MNK1 and MNK2 are set to satisfy (3).

  Here, the memory cell 11a has been described as an example, but the transfer gates of other memory cells are similarly set to satisfy the expression (3).

  FIG. 3 is a conceptual diagram showing the state of memory cell data in the stripe test of the semiconductor integrated circuit device according to the first embodiment of the present invention. Here, a part of the memory cell array, that is, K to (K + 3) rows of M to (M + 3) columns is shown.

  In the stripe test, as shown in FIG. 3, all “1” writing and all “0” writing are repeated for each column, and after all the columns have been written, reading is repeated for each column. Determine malfunction.

  By doing so, when there is a leakage current between memory cells in adjacent columns, for example, between the M column and the (M + 1) column in FIG. 3, it is possible to easily detect a leakage current failure of the memory cell. .

  According to the first embodiment, the malfunction of the memory cells in all the rows can be determined by reading once for each column of the memory cell array. Therefore, the All “1” test, the All “0” test, and the stripe test of the memory cell portion. Test time can be significantly reduced.

  FIG. 4 is a circuit diagram showing a semiconductor integrated circuit device according to Embodiment 2 of the present invention. Here, as in the first embodiment, a part of the Mth column in the memory cell array and a portion related to data writing and data reading are mainly shown. The configuration of the memory cell array is the same as that of the first embodiment.

  The semiconductor integrated circuit device according to the second embodiment of the present invention includes SRAM type memory cells 41a to 41d and a pair of bit lines 42a and 42b for writing / reading data signals to / from the memory cells 41a to 41d for each column of the memory cell array. The row decoder 43a for driving the word lines W (2k-1) to W (2k + 2) and the word lines W (2k-1) to W (2k + 2) for selecting the memory cells 41a to 41d for each row of the memory cell array, respectively. To 43d, a current limiting circuit 44 for controlling the current to the memory cells 41a to 41d during a test, a write circuit 46 for writing a data signal from the bus line 45 to the bit lines 42a and 42b, and a data signal from the bit line 42a or 42b. Read circuit 47 for outputting to bus line 45 and read circuit 4 And a read signal generating circuit 48 for generating a read signal ΦR1 and ΦR2 to control.

  The first input / output of the memory cell 41a is connected to the bit line 42a, the second input / output is connected to the bit line 42b, the control input is connected to the word line W (2k−1), and the first input / output of the memory cell 41a is connected. The first power source is connected to the output of the current limiting circuit 44, and the second power source is connected to a ground line (not shown in FIG. 4) for supplying a ground voltage (0V).

  A test signal (hereinafter referred to as “Ch1”) that is activated during a test is input to the first input of the row decoder 43a, and an address signal for selecting a row of the memory cell array is input to the second input. The output of the row decoder 43a is connected to the word line W (2k-1). The input of the current limiting circuit 44 is connected to a main power supply line (not shown in FIG. 4) that supplies a high voltage (Vcc).

  The memory cells 41b to 41d are connected similarly to the memory cell 41a. The difference from the memory cell 41a is that control inputs are respectively connected to word lines W (2k) to W (2k + 2) driven by row decoders 43b to 43d.

  The row decoders 43b to 43d are connected in the same manner as the row decoder 43a. The difference from the row decoder 43a is that the test signal Ch2 is input instead of Ch1 to the inputs of the row decoders 43b and 43d for selectively driving the even-numbered word lines W (2k) and W (2k + 2).

  The first and second inputs of the write circuit 46 are connected to the bus line 45, the first output of the write circuit 46 is connected to the bit line 42a, and the second output is connected to the bit line 42b. The first input of the read circuit 47 is connected to the bit line 42 a, the second input is connected to the bit line 42 b, and the first and second outputs of the read circuit 47 are connected to the bus line 45.

  The first control input of the readout circuit 47 is connected to the first output of the readout signal generation circuit 48, and the second control input is connected to the second output of the readout signal generation circuit 48, and The input is connected to the bus line 45.

  Since the configurations, functions, and operations of the memory cells 41a to 41d, the bit lines 42a and 42b, the current limiting circuit 44, the writing circuit, and the reading circuit 47 are the same as those in the first embodiment, detailed description thereof is omitted. In the following description, the same reference numerals as those in the first embodiment are used for the components of these circuits such as transistors and inverters.

  Similarly to the first embodiment, the row decoders 43a to 43d each include a decoding unit and an OR circuit to which Ch1 or Ch2 is input. During normal operation, Ch1 = Ch2 = “L”, and the output of the decoding unit is output to the word lines W (2k−1) to W (2k + 2) as they are, and the word lines are selectively driven based on the row address. . On the other hand, during the test, Ch1 = "H" or Ch2 = "H", and odd-numbered word lines W (2k-1) and W (2k + 1), or even-numbered word lines W (2k) and W (2k + 2). Are selectively driven.

  Although not explicitly shown in FIG. 4, Ch1 is input to all odd-numbered row decoders, and Ch2 is input to all even-numbered row decoders. Therefore, during the test, by controlling Ch1 and Ch2, the odd-numbered word lines and the even-numbered word lines can be selectively driven independently.

  The read signal generation circuit 48 generates the control signals ΦR1 and ΦR2 of the read circuit 47 based on the data signal at the time of writing in order to enable a checker test.

  FIG. 5 is a circuit diagram showing an example of the read signal generation circuit 48 of the semiconductor integrated circuit device according to the second embodiment of the present invention.

  The read signal generation circuit 48 of the semiconductor integrated circuit device according to the second embodiment of the present invention includes two data latch circuits 51 and 52 (hereinafter referred to as “LAT 51 and 52”) and eight NAND circuits 53 to 60 (hereinafter referred to as “LAT 51 and 52”). "NAND 53-60") and two inverters 61 and 62 (hereinafter referred to as "INV 61 and 62").

  The data signal from the bus line 45 is input to the data input of the LAT 51, the write signal ΦW1 at the time of test is input to the control input of the LAT 51, the first output of the LAT 51 is connected to the first input of the NAND 53, The second output is connected to the first input of NAND54.

  The data signal from the bus line 45 is input to the data input of the LAT 52, the write signal ΦW2 at the time of test is input to the control input of the LAT 52, the first output of the LAT 52 is connected to the first input of the NAND 55, The second output is connected to the first input of NAND 56.

  Ch1 is input to the second input of NAND53, the output of NAND53 is connected to the first input of NAND57, Ch1 is input to the second input of NAND54, and the output of NAND54 is the first input of NAND58. It is connected to the.

  Ch2 is input to the second input of NAND55, the output of NAND55 is connected to the second input of NAND57, Ch2 is input to the second input of NAND56, and the output of NAND56 is the second input of NAND58. It is connected to the.

  The output of the NAND 57 is connected to the first input of the NAND 59, the output of the NAND 58 is connected to the first input of the NAND 60, and the read signal ΦR is input to the second inputs of the NAND 59 and NAND 60.

  The output of the NAND 59 is connected to the input of the INV 61, and the output of the INV 61 is connected as ΦR 1 to the gate terminal of the MN 51 in the read circuit 47 via the first output of the read signal generation circuit 48.

The output of the NAND 60 is connected to the input of the INV 62, and the output of the INV 62 is connected as ΦR2 to the gate terminal of the MN 52 in the read circuit 47 via the second output of the read signal generation circuit 48.
ΦW1 and ΦW2 will be described later with reference to FIG.

  The read signal generation circuit 48 configured as described above captures the data signal of the bus line 45 into the LAT 51 or the LAT 52 at the timing of the write operation at the time of the test, that is, ΦW, and captures it at the timing of the next read operation, that is, ΦR. ΦR1 or ΦR2 is generated based on the data signal.

ΦW1 and ΦW2 shown in FIG. 4 are generated by a logical operation of ΦW and Ch1 or Ch2.
ΦW1 = Ch1 ・ ΦW
ΦW2 = Ch2 ・ ΦW (4)
It is.

  For example, if the data signal on the bus line 45 is “1” at the timing of ΦW, the read signal generation circuit 48 outputs ΦR1 = “H” and ΦR2 = “L” at the next timing of ΦR, The read circuit 47 is controlled so that the MN 52 is turned ON and the data of the bit line 42 a is output to the bus line 45.

  Similarly, if the data signal on the bus line 45 is “0” at the timing of ΦW, the read signal generation circuit 48 outputs ΦR1 = “L” and ΦR2 = “H” at the next timing of ΦR, and MN51 Is turned OFF, MN52 is set to 0N, and the read circuit 47 is controlled to output the data of the bit line 42b to the bus line 45.

By using the row decoders 43a to 43d and the read signal generation circuit 48 as described above, it is possible to perform memory cell tests with various patterns shown in FIG.
FIG. 8 is a table showing an example of signal control in various test operations of the semiconductor integrated circuit device according to the second embodiment of the present invention.

  As shown in FIG. 8, for example, when testing with checkered pattern data, a data signal “1” is written to an odd row at the timing of ΦW1, and a data signal “0” is written at the timing of ΦW2. For writing to and reading from even-numbered rows, odd-numbered rows may be read by ΦR1 and even-numbered rows may be read by ΦR2.

Next, a test operation of the semiconductor integrated circuit device having the above configuration will be described.
FIG. 6 is a waveform diagram showing a test operation of the semiconductor integrated circuit device according to the second embodiment of the present invention. Here, signal waveforms mainly related to the M-th column checker test shown in FIG. 4 are shown.

  That is, in order to test a leak relationship between adjacent memory cells between rows, a data signal “1” is written to an odd row in a period t1, a data signal “0” is written to an even row in a period t2, and a data signal “0” is written in a period t3. Address signal, data signal (bus line 45 and node QN +), and control signal (Test, Ch1, Ch2, ΦW1, ΦW2, ΦR1, and ΦR2) when reading from odd-numbered rows with ΦR1 and reading with ΦR2 from even-numbered rows in period t4 )showed that.

  As shown in FIG. 6, in the test operation of the semiconductor integrated circuit device according to the second embodiment of the present invention, data “1” is written to the odd-numbered memory cells and data “0” is written to the even-numbered memory cells. Therefore, first, Ch1 = "H" is input to the OR 22 of the row decoders 43a and 43c in the period t1, and the word lines W (2k-1) and W (2k + 1) are activated to transfer the memory cells 41a and 41c. The gates MNK1 and MNK2 are turned on. In writing at the time of test, similarly, the word lines of all odd-numbered rows are activated by Ch1, and the transfer gates of the memory cells of all odd-numbered rows are turned on.

  Next, when ΦW1 is set to “H”, MN31 and MN32 of the write circuit 46 are turned ON, and data “1” of the bus line 45 is transmitted to the bit lines 42a and 42b. Then, data “1” is written into all the memory cells in the odd-numbered rows via MNK1 and MNK2.

  Next, in the period t2, data “0” is similarly written to all the memory cells in the even-numbered rows using Ch2 and ΦW2.

  Next, in the period t3, the data of the bit line 42a is output to the bus line 45 by the read circuit 47 using Ch1 and ΦR1 as in the first embodiment. At this time, since the memory cells connected to the bit line 42a are only odd-numbered rows, if the resistance value of the transfer gate is set to satisfy the expression (3), a malfunction in one memory cell can be easily detected. .

  Finally, in the period t4, similarly, all the memory cells in the even-numbered rows are simultaneously read using Ch2 and ΦR2 to complete the test.

  FIG. 7 is an image diagram showing the state of memory cell data in the checker test of the semiconductor integrated circuit device according to the second embodiment of the present invention. Here, a part of the memory cell array, that is, K to (K + 3) rows of M to (M + 3) columns is shown.

  In the checker test, as shown in FIG. 7, a leak current failure can be detected simultaneously between adjacent rows and between columns by performing a checkered pattern and an inverted checkered pattern for each column. Although not shown in the drawing, the checkered pattern or reverse checkered pattern shown in FIG. 8 can be applied to all the columns to perform a stripe test for each row.

  According to the second embodiment, since odd and even rows can be read independently for each column of the memory cell array, the test time for the memory cell checker test, row stripe test, etc. can be greatly shortened.

  Further, according to the second embodiment, since malfunctions of the memory cells in all rows can be detected by writing twice and reading twice for each column of the memory cell array, the memory cell checker test, row stripe test, etc. Test time can be greatly reduced.

1 is a circuit diagram showing a semiconductor integrated circuit device according to Embodiment 1 of the present invention. FIG. 3 is a waveform diagram showing a test operation of the semiconductor integrated circuit device according to the first embodiment of the present invention. FIG. 3 is an image diagram showing a state of memory cell data in a stripe test of the semiconductor integrated circuit device according to the first embodiment of the invention. FIG. 5 is a circuit diagram showing a semiconductor integrated circuit device according to Embodiment 2 of the present invention. FIG. 6 is a circuit diagram showing an example of a read signal generation circuit of a semiconductor integrated circuit device according to Embodiment 2 of the present invention. FIG. 9 is a waveform diagram showing a test operation of the semiconductor integrated circuit device according to the second embodiment of the present invention. FIG. 6 is an image diagram showing a state of memory cell data in a checker test of a semiconductor integrated circuit device according to a second embodiment of the invention. 7 is a table showing an example of signal control in various test operations of the semiconductor integrated circuit device according to the second embodiment of the present invention.

Explanation of symbols

11a to 11c, 41a to 41d Memory cells 12a, 12b, 42a, 42b Bit line 13, 43a to 43d Row decoder 14, 44 Current limit circuit 15, 45 Bus line 16, 46 Write circuit 17, 47 Read circuit 48 Read signal generation circuit

Claims (5)

A memory cell comprising a flip-flop circuit comprising two inverters and a pair of transfer gates connected to the flip-flop circuit;
A memory cell array in which the memory cells are repeatedly arranged in the row and column directions;
A bit line pair connected to the transfer gate in common for each column of the memory cell array, for writing a complementary data signal to or reading from the memory cell;
A word line commonly connected to a control terminal of the transfer gate for each row of the memory cell array;
A row decoder that drives the word lines to select all rows of the memory cell array during testing;
A semiconductor integrated circuit comprising current limiting means connected between a main power supply line and the power supply of the flip-flop circuit, and controlled to supply less current to the flip-flop circuit during test reading than in normal operation. Circuit device.   The current control means includes a resistance element and a switch element connected in parallel between the external power supply terminal and the power supply terminal of the flip-flop circuit, and the switch element is controlled to be turned off at the time of test reading. The semiconductor integrated circuit device according to claim 1.   2. The data reading means connected to the bit line pair and further comprising a data reading means for selecting a bit line for reading from the bit line pair based on data written in the memory cell during testing. The semiconductor integrated circuit device described. The data reading means includes
A normal buffer and a first switch element connected in series to one bit line of the bit line pair;
An inverting buffer and a second switch element connected in series to the other bit line of the bit line pair;
4. The semiconductor integrated circuit device according to claim 3, wherein the first or second switch element is selectively turned on based on data written in the memory cell during a test. A memory cell comprising a flip-flop circuit comprising two inverters and a pair of transfer gates connected to the flip-flop circuit;
A memory cell array in which the memory cells are repeatedly arranged in the row and column directions;
A bit line pair connected to the transfer gate in common for each column of the memory cell array, for writing a complementary data signal to or reading from the memory cell;
A word line commonly connected to a control terminal of the transfer gate for each row of the memory cell array;
A row decoder that drives the word lines to select even or odd rows of the memory cell array during testing;
A semiconductor integrated circuit comprising current limiting means connected between a main power supply line and the power supply of the flip-flop circuit, and controlled to supply less current to the flip-flop circuit during test reading than in normal operation. Circuit device.

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