JP2007129024A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To make it possible to form CMOS on one and the same chip in a semiconductor device for photo detection which has a PIN photo diode in a light receiver. <P>SOLUTION: In a semiconductor substrate wherein an epitaxial layer 82 is stacked on a P-sub layer 80, the light receiver 62 and a signal processing circuit 66 are formed. The PIN photo diode is comprised of the P-sub layer 80 as an anode and the epitaxial layer 82 between a cathode region 72 and the P-sub layer 80 as an i-layer. In the signal processing circuit 66, a p-well 84 is formed on the boundary between an n-well 86 forming the CMOS and the epitaxial layer 82. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device that has a light receiving portion using a depletion layer extending in a high resistivity semiconductor region and generates a signal by photoelectric conversion.

  In recent years, optical disks such as CD (Compact Disk) and DVD (Digital Versatile Disk) have come to occupy a large position as information recording media. These optical disk reproducing devices irradiate laser light along a track of the optical disk by an optical pickup mechanism and detect the reflected light. Then, the recorded data is reproduced based on the change in the reflected light intensity.

  The optical disk reproducing apparatus servo-controls the positional relationship between the optical pickup mechanism and the optical disk while detecting data based on the reflected light. Specifically, tracking servo for irradiating the laser beam along the center line of the track and focus servo for keeping the distance between the optical disc and the optical pickup mechanism constant are performed. For example, in focus servo control, the position of the optical pickup mechanism is variably controlled by an actuator based on an output signal of a photodetector that detects reflected laser light, and the distance d from the optical disk is kept constant. Thereby, the fluctuation | variation of the reflected light amount according to the shift | offset | difference of the focus of the irradiation light on the surface of an optical disk is suppressed, and the noise superimposed on a received light signal is suppressed.

  In order to obtain such information for servo control, an optical detector that receives a reflected light image divided into a plurality of sections is used. FIG. 9 is a schematic diagram illustrating a light receiving unit of a photodetector and a reflected light image on the light receiving unit. The laser reflected light is incident on the photodetector through a cylindrical lens. Due to the principle of the astigmatism method, the image of the reflected light that has entered the cylindrical lens with a circular cross section after passing through the cylindrical lens has a dimensional ratio in two orthogonal directions according to the distance d between the optical pickup mechanism and the optical disk. Change. Specifically, when the distance d is a target value, the reflected light image is set to be a perfect circle 30 as shown in FIG. On the other hand, for example, when the distance d is over, the reflected light image becomes a vertically long ellipse 32 as shown in FIG. 9A, and when the distance d is under, as shown in FIG. 9C, The reflected light image becomes a horizontally long ellipse 34.

  The photodetector includes, for example, a light receiving unit divided into four 2 × 2 sections 36, and each section constitutes a light receiving element that outputs a light reception signal. The photodetectors are arranged so that the diagonal directions of the 2 × 2 square array of light receiving elements coincide with the axes of the vertically long ellipse 32 and the horizontally long ellipse 34, respectively. With this arrangement, each reflection is based on the difference between the sum of the output signals of the two light receiving elements arranged on the diagonal line in the vertical direction and the sum of the output signals of the two light receiving elements arranged on the diagonal line in the horizontal direction in FIG. The shape of the optical image can be determined and used to control the distance d. On the other hand, the reflected light intensity corresponding to the data is obtained by the sum of the output signals of the four light receiving elements.

Since the data rate read from the optical disk is very high, the photodetector is composed of a semiconductor element using a PIN photodiode having a high response speed. FIG. 10 is a schematic cross-sectional view of one light receiving element constituting a conventional photodetector. This figure shows a vertical sectional structure of a PIN photodiode as a light receiving element. In this semiconductor element, the p-type semiconductor substrate 40 becomes the anode region 42 of the photodiode, and an i layer 44 having a low impurity concentration and a high specific resistance is formed thereon by epitaxial growth. The impurity concentration of the i layer 44 is extremely low, and its specific resistance is on the order of 100 Ω · cm. This specific resistance is much higher than that of a semiconductor substrate used for other general semiconductor elements. An n ⁺ region that becomes the cathode region 48 is formed on the surface of the i layer 44. By arranging the low-concentration i layer 44 between the anode region 42 and the cathode region 48, a depletion layer is formed in the i layer 44 even if the reverse bias voltage applied between the anode and the cathode is lowered. Therefore, the photodetector can be driven at a low voltage.

  The anode region 42, the i layer 44, and the cathode region 48 constitute a PIN photodiode that serves as a light receiving element of the photodetector. In this PIN photodiode, an anode region 42 and a cathode region 48 are connected to voltage terminals, respectively, and a reverse bias voltage is applied between them. A depletion layer is formed in the i layer 44 between the anode region 42 and the cathode region 48 in the reverse bias state, and electrons generated by absorption of incident light in the depletion layer are generated in the cathode region by an electric field in the depletion layer. 48 and output as a light reception signal.

  The thickness of the i layer 44 is set to be equal to or greater than the absorption length of the light to be detected in the semiconductor. For example, the absorption length of silicon for light in the 780 nm band and 650 nm band used for CDs and DVDs is about 10 to 20 μm.

  The weak photoelectric conversion signal generated in the light receiving unit is amplified by the amplifier and output to the signal processing circuit at the subsequent stage. Here, from the viewpoint of suppressing the attenuation of the photoelectric conversion signal and the superposition of noise, the wiring length between the light receiving unit and the amplifier is configured to be as short as possible. From this viewpoint and from the viewpoint of reducing the manufacturing cost of the photodetector, it is preferable that the light receiving portion of the PIN photodiode structure and a circuit such as an amplifier are formed on the same semiconductor chip. In this case, as shown in the schematic cross-sectional view of FIG. 11, an N-well 50 that is an n-type impurity region is formed on the surface of the i layer 44 formed in the low-concentration p-type region. For example, a p-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor) 52 and an n-channel MOSFET 54 can be formed to constitute a CMOS (Complementary Metal Oxide Semiconductor). However, this configuration has a problem that the leakage current at the pn junction between the i layer 44 and the N well 50 increases due to the extremely low impurity concentration of the i layer 44.

  The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor element for photodetection that can be driven at a high speed with a low voltage and can be reduced in cost.

  A semiconductor device according to the present invention has a light receiving portion and a circuit portion formed on a common semiconductor substrate, and is provided on the main surface of the semiconductor substrate and is formed to have a high specific resistance with a low impurity concentration. A first resistance type semiconductor region having a specific resistance region, wherein the light receiving portion is disposed in contact with the high specific resistance region, and has a higher impurity concentration than the high specific resistance region; A first electrode region, a second electrode region disposed in contact with the high specific resistance region and having a higher impurity concentration than the high specific resistance region, to which a second voltage is applied; The first electrode region and the second electrode region are reversely biased by the first voltage and the second voltage to form a depletion layer in the high resistivity region, Are provided on the main surface, and circuit elements are formed inside. A circuit element region that is a first conductivity type semiconductor region, a boundary between the high resistivity region and the circuit element region, and a second conductivity type semiconductor region having a higher impurity concentration than the high resistivity region And a certain joint boundary region.

  According to the present invention, a junction boundary region having a conductivity type opposite to the circuit element region and having a higher concentration than the high resistivity region is provided at the boundary between the high specific resistance region and the circuit element region. In the pn junction portion formed by the junction boundary region and the circuit element region, expansion of a depletion layer that can generate charges due to thermal excitation or the like is suppressed, and leakage current is suppressed. As a result, a circuit portion including circuit elements such as CMOS can be formed on the same substrate along with the light receiving portion, and a low-voltage and high-speed photodetection semiconductor element can be realized while suppressing cost. .

  Hereinafter, embodiments of the present invention (hereinafter referred to as embodiments) will be described with reference to the drawings.

[Embodiment 1]
FIG. 1 is a schematic plan view of a photodetector which is a semiconductor element of the embodiment. The photodetector 60 is formed on a semiconductor substrate made of silicon, and a light receiving portion 62 is disposed in an opening (not shown) provided in a protective film laminated on the surface of the semiconductor substrate. The light receiving unit 62 includes, for example, four PIN photodiodes (PD) 64 arranged in 2 × 2, and receives light incident on the substrate surface from the optical system by dividing it into 4 × 2 sections. On the semiconductor substrate, not only the light receiving unit 62 but also a signal processing circuit unit 66 is formed. For example, the signal processing circuit unit 66 is disposed around the light receiving unit 62. The signal processing circuit unit 66 includes, for example, circuit elements such as CMOS 68, and an amplifier circuit for the output signal from the light receiving unit 62 and other signal processing circuits are formed on the same semiconductor chip as the light receiving unit 62 using these circuit elements. be able to.

FIG. 2 is a more detailed plan view of the light receiving unit 62. Each PD 64 is delimited by a separation region 70 formed on the surface of the surrounding semiconductor substrate. The isolation region 70 is formed, for example, as a p ⁺ region in which a high concentration p-type impurity is diffused. In the portion corresponding to the light receiving portion of the silicon substrate, electrons and holes are generated by absorption of light. Each PD 64 has a cathode region 72 that collects electrons out of the generated charges as its cathode. The cathode region 72 is formed, for example, as an n ⁺ region in which a high concentration n-type impurity is diffused.

  The isolation region 70 and each cathode region 72 are connected to wirings formed of, for example, an aluminum (Al) layer through contacts. For example, a ground potential is applied to the isolation region 70 through the wiring 74. Further, the signal charges collected in each cathode region 72 are read out via the wiring 76.

  FIG. 3 is a schematic cross-sectional view showing the structure of the light receiving unit 62 and the signal processing circuit unit 66 in a cross section passing through the straight line A-A ′ shown in FIGS. 1 and 2 and perpendicular to the semiconductor substrate. In this section, two PDs 64 of the light receiving unit 62 and a CMOS 68 of the signal processing circuit unit 66 appear.

  In the photodetector 60, a semiconductor layer having an impurity concentration lower than that of the P-sub layer 80 and having a high specific resistance is stacked on one main surface of the P-sub layer 80 which is a p-type silicon substrate into which a p-type impurity is introduced. The semiconductor substrate is formed. The P-sub layer 80 constitutes an anode common to the PDs 64 and is applied with a ground potential from the back surface of the substrate, for example. The high resistivity semiconductor layer stacked on the P-sub layer 80 is formed by, for example, epitaxial growth. The epitaxial layer 82 (high specific resistance region) forms an i layer of the PD 64 in the light receiving portion 62. The low concentration impurity introduced into the epitaxial layer 82 is, for example, a p-type impurity. In addition, the specific resistance ρ of the epitaxial layer 82 is at least 200 Ω · cm, and ρ is about 500 Ω · cm here. The thickness of the epitaxial layer 82 constituting the i layer is set to be equal to or greater than the absorption length of the light to be detected in the semiconductor. For example, the absorption length of silicon for light in the 780 nm band and 650 nm band used for CDs and DVDs is about 10 to 20 μm. Therefore, here, the thickness of the epitaxial layer 82 is set to 10 to 20 μm.

  In the light receiving portion 62, the above-described isolation region 70 and cathode region 72 are formed on the surface of the epitaxial layer 82. Impurities are introduced into the isolation region 70 and the cathode region 72 by forming a mask formed by a photolithography technique on the surface of the silicon substrate on which the epitaxial layer 82 is formed, and ion implantation is performed using the mask. This is realized by selectively performing.

  Incidentally, the impurities introduced by ion implantation at the positions where the separation region 70 and the cathode region 72 are formed are further pushed into the substrate depth direction by performing a thermal diffusion process as necessary. The pushing amount can be controlled separately for each of the separation region 70 and the cathode region 72. For example, the separation region 70 has a function of suppressing crosstalk between the PDs 64 of signal charges collected in each cathode region 72, as will be described later. Therefore, the depth of the separation region 70 can be set deeper than that of the cathode region 72, for example. On the other hand, by reducing the depth of the cathode region 72, the depletion layer formed in the underlying i layer spreads from near the substrate surface, and an improvement in photoelectric conversion efficiency in the PD 64 can be expected. When the cathode region 72 is formed shallower than the separation region 70 as described above, it is preferable to perform ion implantation and thermal diffusion of impurities into the separation region 70 prior to ion implantation into the cathode region 72.

  In the configuration of the photodetector 60, the isolation region 70 does not reach the P-sub layer 80, and the high-resistivity epitaxial layer 82 is i between the isolation region 70 and the P-sub layer 80. Present as a layer. The isolation region 70 is applied with a ground potential by the wiring 74 provided on the substrate surface side as described above, and constitutes an anode together with the P-sub layer 80.

  On the other hand, in the signal processing circuit portion 66, a P well 84 and an N well 86 are formed in the surface layer portion of the epitaxial layer 82 corresponding to the formation region of the CMOS 68. Here, the N well 86 is a circuit element region in which circuit elements are formed as described later, and the P well 84 is a junction boundary region that forms a boundary between the N well 86 and the epitaxial layer 82. For example, the P well 84 and the N well 86 are each formed by ion implantation. Specifically, ion implantation for forming the P well 84 is performed first, and then the N well 86 is formed shallower than the P well 84 by ion implantation, and the N well 86 is formed inside the P well 84. The depths of the P well 84 and the N well 86 can be made different from each other by adjusting the energy of ion implantation and selecting the ion species. The concentration of the N well 86 can be determined according to the relationship with the CMOS 68 formed in the region. P well 84 is set at a higher concentration than epitaxial layer 82, and suppresses junction leakage current between epitaxial layer 82 and N well 86.

In the N well 86, a p-channel MOSFET 88 and an n-channel MOSFET 90 constituting the CMOS 68 are formed. In the p-channel MOSFET 88, for example, an N well 92 is further formed in the N well 86, and a source region 94 and a drain region 96 which are p ⁺ regions are formed on the surface thereof. A gate electrode 100 is disposed on a channel region between the source region 94 and the drain region 96 with a gate oxide film 98 interposed. In the n-channel MOSFET 90, a P well 102 is further formed in an N well 86, and a source region 104 and a drain region 106 which are n ⁺ regions are formed on the surface thereof. A gate electrode 110 is disposed on the channel region between the source region 104 and the drain region 106 via a gate oxide film 98. The gate electrodes 100 and 110 are formed using, for example, polysilicon or tungsten (W).

  On the surface of the epitaxial layer 82, a LOCOS (local oxide film) 112 is formed at the boundary between the formation region of the CMOS 68 and the epitaxial layer 82 for separation between the regions. A LOCOS 114 is also formed at the boundary between the p-channel MOSFET 88 and the n-channel MOSFET 90 for element isolation.

  As described above, the antireflection film 116 is laminated on the substrate surface on which the light receiving unit 62 and the signal processing circuit unit 66 are formed. The antireflection film 116 is made of, for example, a silicon nitride film. Further, a planarizing film, a wiring layer, and a light shielding layer are formed thereon, but the illustration is omitted in FIG. 3 for simplification.

  FIG. 4 is a schematic diagram illustrating a circuit configuration during the operation of the photodetector 60 and a potential distribution in a cross section of the light receiving unit 62. The cross section of the light receiving section 62 shown in FIG. 4 is along the straight line A-A ′ shown in FIGS. A reverse bias voltage is applied between the cathode region 72 and the isolation region 70 and the P-sub layer 80 by the voltage source 120. Specifically, the wiring from each cathode region 72 (wiring 76 in FIG. 2) is connected to one input terminal of the operational amplifier 122, and the positive voltage Vb from the voltage source 120 is input to the other input terminal of the operational amplifier 122. The The operational amplifier 122 has an output terminal connected to the cathode region 72 via a resistor, and constitutes a current detector. With this configuration, the cathode region 72 is applied with a positive voltage Vb with reference to the potentials of the isolation region 70 and the P-sub layer 80, and a voltage corresponding to the cathode current is taken out to the output terminal of the operational amplifier 122. Incidentally, the current detector including the operational amplifier 122 can be formed in the signal processing circuit unit 66.

  In the sectional view, several equipotential lines are indicated by dotted lines. This sectional view shows that a depletion layer spreads in the epitaxial layer 82 constituting the i layer by applying a reverse bias voltage to the anode and the cathode of the PIN photodiode. The closer to the cathode region 72, the deeper, that is, the potential potential becomes, and a potential well for electrons is formed around each cathode region 72.

  By applying a ground potential that is a reverse bias to the cathode region 66 using the isolation region 70 and the P-sub layer 80 as an anode, the boundary region 124 between the isolation region 70 of the epitaxial layer 82 and the P-sub layer 80 is applied. The potential potential becomes shallower. That is, by setting the isolation region 70 as an anode in addition to the P-sub layer 80 to a ground potential, the potential potential of the boundary region 124 under the isolation region 70 is pulled in a direction of decreasing. Thereby, a potential barrier against electron movement is formed between potential wells corresponding to the PDs 64 adjacent to each other with the isolation region 70 interposed therebetween.

  For example, in FIG. 4, electrons generated in the i layer under the left cathode region 72-1 by the incident light on the left PD 64 easily move to the cathode region 72-1 along the electric field of the left potential well. However, it is difficult to move to the cathode region 72-2 on the right side because a potential barrier exists in the region 124. Therefore, signal charges corresponding to the incident light on the left PD 64 are collected exclusively in the cathode region 72-1. Similarly, the signal charges corresponding to the light incident on the right PD 64 are less likely to move to the cathode region 72-1 due to the presence of the potential barrier, and are collected exclusively in the cathode region 72-2. The amount of electrons collected in each cathode region 72 is detected via the operational amplifier 122 as a cathode current.

  Thus, by using the isolation region 70 as the anode in addition to the P-sub layer 80, element isolation between the PDs 64 is realized even though the i layer of the adjacent PD 64 is connected under the isolation region 70, A light reception signal in which crosstalk is suppressed is obtained.

  In the configuration of the photodetector, the P-sub layer 80 is an anode, and the P-sub layer 80 extends under the signal processing circuit unit 66. Here, the impurity concentration of the epitaxial layer 82 is extremely low. Therefore, in the configuration in which the epitaxial layer 82 is in contact with the N well 86, the depletion layer tends to spread in the epitaxial layer 82 at the junction with the N well 86 as the potential of the P-sub layer 80 is lower. In the depletion layer, charges due to thermal excitation or the like are likely to be generated, and a leak current may be generated due to this. That is, a common P-sub layer 80 is arranged under the light receiving unit 62 and the signal processing circuit unit 66, and this P-sub layer 80 serves as an anode of the light receiving unit 62 and is applied with a ground potential. If the N well 86 of the signal processing circuit unit 66 is in direct contact with the epitaxial layer 82, a leak current can easily occur. Therefore, in the photodetector 60, a P well 84 having an impurity concentration higher than that of the epitaxial layer 82 is provided at the boundary between the N well 86 and the epitaxial layer 82, thereby reducing the spread of the depletion layer at the pn junction portion. We are trying to suppress this.

  Further, the depletion layer of the epitaxial layer 82 at the boundary with the N well 86 can extend not only on the lower surface side of the N well 86 but also on the side surface. In particular, at the boundary portion between the light receiving unit 62 and the signal processing circuit unit 66, the isolation region 70, which is an anode, is grounded to a low potential, so that the depletion layer is likely to expand and a leak current is likely to occur. However, by adopting a structure in which the P well 84 is also arranged on the side of the N well 86, a depletion layer in the lateral direction as in the boundary portion between the light receiving unit 62 and the signal processing circuit unit 66 is also suppressed. Leakage current can be reduced.

In the light receiving unit 62 described above, a plurality of PDs 64 are arranged adjacent to each other with a separation region 70 interposed therebetween. Here, a LOCOS method is known as one conventional technique for element isolation. According to the technique, for example, a thick oxide film that grows into the substrate such as the LOCOSs 112 and 114 formed in the signal processing circuit unit 66 is grown selectively in the p ⁺ region as formed in the isolation region 70. While the technology can be applied to the light receiving unit 62 as well, the technology is not adopted in the present embodiment. By not forming the LOCOS oxide film on the isolation region 70 in this way, incident light from above the isolation region 70 is not attenuated by the LOCOS oxide film. Here, under the isolation region 70 is an i layer, which can be depleted. Therefore, the light that has been suppressed from being attenuated and has entered from above the separation region 70 can reach the i layer below the separation region 70 to generate a signal charge, and the detection efficiency for the light incident on the light receiving unit 62 is improved. improves.

  In addition, the separation region 70 can be an insensitive region for incident light detection. Here, by not forming the LOCOS oxide film, lateral diffusion of the isolation region 70 in the formation process is avoided. As a result, since the ratio of the separation region 70 occupying the light receiving unit is suppressed, the detection efficiency for the light incident on the light receiving unit can be improved also in this respect.

The structure of the light receiving unit 62 of the photodetector 60 is not limited to the above. FIG. 5 is a schematic cross-sectional view showing another structure of the light receiving portion 62, and shows a cross section passing through the straight line AA ′ shown in FIGS. 1 and 2 and perpendicular to the semiconductor substrate. The plan view of the light receiving portion 62 is the same as that shown in FIG. The feature of the light receiving unit 62 shown in FIG. 5 is that it has a lower isolation region 150 that is a p ⁺ region protruding from the P-sub layer 80 at a position facing the isolation region 70. The lower isolation region 150 receives a voltage applied to the P-sub layer 80 and functions as an anode on the substrate side together with the P-sub layer 80. The lower separation region 150 narrows the distance between the anode formed by the separation region 70 and the substrate-side anode at the boundary of the PD 64. As a result, a potential barrier against electrons is more suitably formed in the epitaxial layer 82 at the boundary of the PD 64, and the element isolation performance between the PDs 64 is improved.

  For example, the lower isolation region 150 is a p-type impurity formed by ion implantation or the like at a position corresponding to the boundary of the PD 64 of the epitaxial layer 82 at the stage where the epitaxial layer 82 is partially stacked on the P-sub layer 80. It is formed by introducing. After the lower isolation region 150 is thus formed, the remaining thickness of the epitaxial layer 82 is grown. Thereafter, the structure of the substrate surface such as the separation region 70 and the cathode region 72 is formed in the same manner as the light receiving unit 62 whose sectional structure is shown in FIG.

  In the case of the structure of the light receiving section 62 shown in FIG. 5 instead of the structure of the light receiving section 62 shown in FIG. 3, the epitaxial layer is formed from the boundary of the N well 86 by providing the P well 84 in the signal processing circuit section 66. The depletion layer extending to 82 can be suppressed. As a result, the photodetector 60 in which the junction leakage current between the epitaxial layer 82 and the N well 86 is suppressed is realized.

[Embodiment 2]
The photodetector 60 according to the second embodiment described below basically has the same configuration as that of the first embodiment except that the structure of the light receiving unit 62 is different from that of the first embodiment. In the present embodiment, the same reference numerals as those in the first embodiment indicate components having the same functions and properties. A schematic plan view of the photodetector 60 of the present embodiment is the same as FIG. 1, and this is used.

  FIG. 6 is a schematic plan view of the light receiving unit 62 of the photodetector 60. Similar to the photodetector of the first embodiment, the photodetector 60 is formed on a semiconductor substrate made of silicon and is received by an opening (not shown) provided in a protective film stacked on the surface of the semiconductor substrate. A part 62 is arranged. The light receiving unit 62 divides the light incident on the substrate surface into 2 × 2 four sections and receives the light.

  Cathode regions 200 are arranged on the surface of the semiconductor substrate on the outer periphery of the light receiving unit 62 so as to correspond to the respective PDs 64. In addition, an anode region 202 is disposed on the surface of the semiconductor substrate between the PDs 64, and this performs element isolation between the PDs 64.

The cathode region 200 is formed as an n ⁺ region by diffusing high-concentration n-type impurities from the surface of the trench 204 having, for example, an L-shaped planar shape along the outer periphery of the light receiving portion. On the other hand, the anode region 202 is formed as a p ⁺ region by diffusing high-concentration p-type impurities between the PDs 64 from the surface of the trench 206 having a cross-shaped planar shape, for example. Each cathode region 200 is connected to a wiring (not shown) formed of, for example, an Al layer through a contact, and functions as a cathode of each PD 64 that is a PIN photodiode. On the other hand, the anode region 202 is connected to a wiring (not shown) through a contact, and functions as an anode common to each PIN photodiode.

  FIG. 7 is a schematic cross-sectional view showing the structure of the light receiving unit 62 and the signal processing circuit unit 66 in a cross section perpendicular to the semiconductor substrate through the straight line A-A ′ shown in FIGS. 1 and 6, respectively. In this section, two PDs 64 of the light receiving unit 62 and a CMOS 68 of the signal processing circuit unit 66 appear. High resistivity epitaxial layer 82 laminated on one main surface of P-sub layer 80, which is a p-type silicon substrate, constitutes the i layer of a PIN photodiode. On the surface of the epitaxial layer 82, the trenches 204 and 206, the cathode region 200, and the anode region 202 are formed. The trenches 204 and 206 are formed by etching the surface of the semiconductor substrate. After the trenches 204 and 206 are formed, a resist is applied to the surface of the semiconductor substrate, and the resist is patterned to form an opening surrounding the trench 204. Using this resist as a mask, n-type impurity ions are implanted. By making the implantation direction oblique, ion implantation is performed also on the wall surface of the trench 204, and the cathode region 200 is formed on the surface of the trench 204, that is, on the wall surface and bottom surface of the trench 204. Similarly, a mask having an opening corresponding to the trench 206 is formed using a resist, and ion implantation of p-type impurities is performed to form the anode region 202 on the surface of the trench 206, that is, on the wall surface and bottom surface of the trench 206. To do.

  In addition, the formation process of the cathode area | region 200 and the anode area | region 202 may include the thermal diffusion process performed after the above-mentioned ion implantation as needed. Further, after the cathode region 200 and the anode region 202 are formed, an insulating film is buried in the trenches 204 and 206 so that the surface of the light receiving portion is planarized.

  As described above, the cathode region 200 and the anode region 202 formed by using the trenches 204 and 206 constitute the cathode and the anode of the PIN photodiode, and surround each PD 64 and separate each PD 64 from the outside. Also have. Incidentally, such a configuration is known as an STI (Shallow Trench Isolation) technique.

  An epitaxial layer 82 appears on the inner surface of each PD 64 surrounded by the cathode region 200 and the anode region 202. As will be described later, this portion becomes a semiconductor region (light receiving semiconductor region 208) having sensitivity to light incident on the light receiving portion.

  FIG. 8 is a schematic diagram illustrating a circuit configuration during the operation of the photodetector 60 and a potential distribution in a cross section of the light receiving unit 62. The cross section of the light receiving portion 62 shown in FIG. 8 is along the straight line A-A ′ shown in FIGS. The cathode region 200 is reverse-biased by the voltage source 120 with respect to the anode region 202 and the P-sub layer 80 which are set to the ground potential. Specifically, the wiring from each cathode region 200 is connected to one input terminal of the operational amplifier 122, and the positive voltage Vb from the voltage source 120 is input to the other input terminal of the operational amplifier 122. The operational amplifier 122 has an output terminal connected to the cathode region 200 via a resistor, and constitutes a current detector. With this configuration, Vb is applied to the cathode region 200 and a voltage corresponding to the cathode current is extracted to the output terminal of the operational amplifier 92. Incidentally, the current detector including the operational amplifier 122 can be formed in the signal processing circuit unit 66.

  In the sectional view, several equipotential lines are indicated by dotted lines. This sectional view shows that a depletion layer spreads in the epitaxial layer 82 constituting the i layer by applying a reverse bias voltage to the cathode and the anode of the PIN photodiode. The cathode region 200 and the anode region 202 are both disposed on the surface of the semiconductor substrate, and the light receiving semiconductor region 208 located between the surface of the semiconductor substrate and between them constitutes an i layer. With this configuration, when a reverse bias voltage is applied, a depletion layer also extends near the surface of the semiconductor substrate corresponding to the light receiving semiconductor region 208.

  The potential potential in the depletion layer becomes deeper from the anode region 202 toward the cathode region 200. That is, a potential well is formed at a position corresponding to each cathode region 200. In addition, the potential potential at the boundary between the PDs 64 corresponding to the position of the anode region 202 becomes shallow, forming a potential barrier against the movement of electrons, thereby realizing element isolation between the PDs 64.

  The light incident on each PD 64 is absorbed in the depletion layer to generate electron-hole pairs as signal charges, and electrons among them are collected in the nearby cathode region 200. The amount of electrons collected in each cathode region 200 is detected via the operational amplifier 122 as a cathode current. In the PD 64 of the photodetector 60, signal charges are also generated by light absorbed near the surface of the light receiving semiconductor region 208, and the signal charges can be detected from the cathode region 200. As a result, signal charges generated by light having a short wavelength absorbed in the vicinity of the surface of the semiconductor substrate can be extracted as a light reception signal, and sensitivity to short wavelength light can be obtained.

  Incidentally, as an etching method for forming the trenches 204 and 206, for example, by using an anisotropic etching technique such as RIE (Reactive Ion Etching), the trenches 204 and 206 can be formed thinly, and the surface of the semiconductor substrate of each PD 64 It is possible to increase the proportion of the light receiving semiconductor region 208 in the area. As a result, the sensitivity of each PD 64 can be improved.

  Further, since the junction area between the cathode region 200 and the anode region 202 and the epitaxial layer 82 can be reduced, the inter-terminal capacitance between the cathode and the anode of the PIN photodiode can be suppressed, and good responsiveness can be ensured. It becomes possible.

  In the configuration of the photodetector 60, an N well 86 in which circuit elements are formed in the signal processing circuit section 66 is formed in an epitaxial layer 82 having a very low impurity concentration. Therefore, a depletion layer is likely to spread in the epitaxial layer 82 at the boundary with the N well 86, and a leak current is likely to occur due to this. In particular, the PIN photodiode is used in a reverse bias state, and the P-sub layer 80 serving as the anode extends under the signal processing circuit section 66. If the potential difference between the N well 86 and the P-sub layer 80 is small (or reverse biased), the epitaxial layer 82 is more likely to be depleted. However, in the photodetector 60, the boundary between the N well 86 and the epitaxial layer 82 is present. A P well 84 having an impurity concentration higher than that of the epitaxial layer 82 is provided to reduce the spread of the depletion layer at the pn junction with the N well 86, thereby suppressing leakage current.

  Further, by adopting a structure in which the P well 84 also covers the side surface of the N well 86, a depletion layer in the lateral direction from the N well 86 is suppressed, and leakage current is reduced. In particular, the PD 64 may have a layout in which the anode region 202 is adjacent to the N well 86, and in this case, a depletion layer extending in the lateral direction is easily formed in the epitaxial layer 82 therebetween. However, in the present photo detector 60, the P well 84 is also disposed on the side of the N well 86 as described above, and in this case as well, the depletion layer is suitably suppressed and the leakage current is suppressed. It becomes possible.

1 is a schematic plan view of a photodetector that is an embodiment of the present invention. It is a top view of the light-receiving part of the photodetector which concerns on 1st Embodiment. It is sectional drawing of the photodetector which concerns on 1st Embodiment. It is a schematic diagram which shows the circuit structure at the time of operation | movement of the photodetector which concerns on 1st Embodiment, and the potential distribution in the cross section of a light-receiving part. It is sectional drawing of the other light-receiving part of the photodetector which concerns on 1st Embodiment. It is a top view of the light-receiving part of the photodetector which concerns on 2nd Embodiment. It is sectional drawing of the light-receiving part of the photodetector which concerns on 2nd Embodiment. It is a schematic diagram which shows the circuit structure at the time of operation | movement of the photodetector which concerns on 2nd Embodiment, and the potential distribution in the cross section of a light-receiving part. It is a schematic diagram which shows the light-receiving part of a photodetector, and the reflected light image on the said light-receiving part. It is typical sectional drawing of one light receiving element which comprises the conventional photodetector. It is an element sectional view explaining a problem of a photodetector in which a light receiving part of a PIN photodiode structure and a circuit such as an amplifier are formed on the same semiconductor chip.

Explanation of symbols

  Reference Signs List 60 photo detector, 62 light receiving unit, 64 PIN photodiode (PD), 66 signal processing circuit unit, 68 CMOS, 70 isolation region, 72,200 cathode region, 74,76 wiring, 80 P-sub layer, 82 epitaxial layer , 84 P well, 86, 92 N well, 88, 102 p channel MOSFET, 90 n channel MOSFET, 94, 104 source region, 96, 106 drain region, 98 gate oxide film, 100, 110 gate electrode, 112 LOCOS, 116 Antireflection film, 120 voltage source, 122 operational amplifier, 202 anode region, 204, 206 trench, 208 light receiving semiconductor region.

Claims (7)

A semiconductor device having a light receiving portion and a circuit portion formed on a common semiconductor substrate,
A high resistivity region provided on a main surface of the semiconductor substrate and formed to have a high resistivity by a low impurity concentration;
The light receiving unit is
A first electrode region that is disposed in contact with the high specific resistance region and has a higher impurity concentration than the high specific resistance region and to which a first voltage is applied;
A second electrode region that is disposed in contact with the high resistivity region and is a second conductivity type semiconductor region having a higher impurity concentration than the high resistivity region and to which a second voltage is applied;
Have
The first electrode region and the second electrode region are reversely biased by the first voltage and the second voltage to form a depletion layer in the high specific resistance region,
The circuit section is
A circuit element region which is a first conductivity type semiconductor region provided on the main surface and in which a circuit element is formed;
Forming a boundary between the high resistivity region and the circuit element region, and a junction boundary region which is a second conductivity type semiconductor region having a higher impurity concentration than the high resistivity region;
A semiconductor device comprising: The semiconductor device according to claim 1,
The semiconductor device according to claim 1, wherein the high specific resistance region is a second conductivity type semiconductor region. The semiconductor device according to claim 1 or 2,
The high specific resistance region has a specific resistance of 200 Ω · cm or more. The semiconductor device according to claim 1, wherein:
The semiconductor device, wherein the high specific resistance region is an epitaxial growth layer. 5. The semiconductor device according to claim 1, wherein:
The second electrode region is a base layer of the high resistivity region;
Each of the first electrode region and the circuit element region is formed in a surface layer portion of the high resistivity region;
A semiconductor device characterized by the above. 5. The semiconductor device according to claim 1, wherein:
Each of the first electrode region, the second electrode region, and the circuit element region is formed in a surface layer portion of the high resistivity region;
A semiconductor device characterized by the above. The semiconductor device according to claim 6.
Another said 2nd electrode area | region is a base layer of the said high specific resistance area | region, The semiconductor device characterized by the above-mentioned.

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