JP2007124021A - Level shifter circuit and display panel incorporating the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a level shifter circuit whose manufacturing costs are restrained, and to provide a display panel having the level shifter circuit. <P>SOLUTION: The level shifter circuit C1 is provided on the display panel DP to level-shift an input signal. The level shifter circuit C1 comprises a pair of power terminals to which a supply voltage is applied that is larger than the voltage amplitude of the input signal; a switching element W2 connected between the pair of power terminals; and an input terminal IT that is set to bias potential corresponding to a threshold Vth of the switching element W2, and superimposes the bias potential on the input signal when the input signal is inputted by capacity coupling for supplying to the gate of the switching element W2. The switching element W2 is the same conductivity-type level shifter circuit as a pixel switching element W1 on the display panel DP. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a level shifter circuit and a display panel using the level shifter circuit, and more particularly to a display panel which is driven by an active matrix method.

  In general, a display panel has an effective display unit in which a plurality of display pixels are arranged in a matrix, a plurality of scanning lines arranged along a row in which the plurality of display pixels are arranged, and a plurality of display pixels are arranged. And a plurality of signal lines arranged along the column.

  The plurality of scanning lines are connected to a scanning line driving circuit. The scanning line driving circuit selects a display pixel for each row through each scanning line. The plurality of signal lines are connected to a signal line driving circuit. The signal line driver circuit supplies an image signal to the display pixels in the row selected by the scanning line driver circuit via each signal line.

  Each display pixel has a pixel switch, and an image signal is applied by a signal line corresponding to the pixel switch selected by the scanning line.

On the other hand, a switch element is conventionally used in a level shifter circuit that shifts the potential level of a logic signal to a different potential level. In a configuration using switch elements, a circuit configuration in which switch elements of different conductivity types are combined is generally used (see Patent Document 1).
JP-A-9-172367

  However, when a level shifter circuit having a circuit configuration in which switch elements of different conductivity types are combined is used for a display panel, the manufacturing process of a switch different from the conductivity type of the pixel switch increases, so it may be difficult to reduce the manufacturing cost. It was.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a level shifter circuit with reduced manufacturing cost and a display panel including the level shifter circuit.

  A level shifter circuit according to a first aspect of the present invention is a level shifter circuit provided on a display panel for level shifting an input signal, and a pair of power supply terminals to which a power supply voltage larger than the voltage amplitude of the input signal is applied. A level shift field effect transistor connected between the pair of power supply terminals, and a bias potential corresponding to a threshold value of the level shift field effect transistor, and when the input signal is input by capacitive coupling An input terminal that supplies a potential changed from the bias potential to the gate of the level shift field effect transistor in response to the input signal, and the level shift field transistor is the same as the pixel switching field effect transistor Conductive type.

  A display panel according to a second aspect of the present invention includes a display panel including a plurality of display pixels arranged in a matrix and a plurality of pixel switching field effect transistors respectively connected to the plurality of display pixels, and the plurality of displays. A drive circuit for driving a plurality of pixel switching field effect transistors corresponding to each row of pixels, the drive circuit having a level shifter circuit provided on a display panel for level shifting an input signal, and the level shifter circuit Is a pair of power supply terminals to which a power supply voltage larger than the voltage amplitude of the input signal is applied, a level shift field effect transistor connected between the pair of power supply terminals, and a threshold of the level shift field effect transistor The corresponding bias potential is set and the input signal is input by capacitive coupling. And an input terminal for supplying a potential changed from the bias potential to the gate of the level shift field effect transistor corresponding to the input signal, and the level shift field transistor is the same as the pixel switching field effect transistor. Of the conductivity type.

  According to the present invention, it is possible to provide a level shifter circuit with reduced manufacturing costs and a display panel including the level shifter circuit.

  A display panel according to an embodiment of the present invention will be described below with reference to the drawings. The display panel according to the present embodiment is a liquid crystal display panel DP as shown in FIG. The liquid crystal display panel DP includes a pair of electrode substrates, an array substrate 12, a counter substrate 14, and a liquid crystal layer 3 sandwiched between the array substrate 12 and the counter substrate 14.

  The array substrate 12 includes a plurality of pixel electrodes PE arranged in a substantially matrix on a transparent insulating substrate such as glass, and a plurality of gate lines G (G1 to Gm) arranged along a row of the plurality of pixel electrodes PE. , A plurality of source lines SL (SL1 to SLn) arranged along a column of the plurality of pixel electrodes PE, and arranged near the intersection position of these gate lines G and source lines SL, and driven through corresponding gate lines G, respectively. A plurality of pixel switching elements W1 that are electrically connected between the corresponding source line SL and the corresponding pixel electrode PE.

  Each pixel switching element W1 is a pixel switching field effect transistor, and is a P-channel type thin film transistor in this embodiment. The gate electrode of the pixel switching element W1 is connected to the gate line G, and the source-drain path is connected between the source line SL and the pixel electrode PE.

  The counter substrate 14 includes a common electrode CE and the like disposed to face the plurality of pixel electrodes PE. Each pixel electrode PE and common electrode CE are made of a transparent electrode material such as ITO, and are covered with an alignment film (not shown). Each pixel electrode PE and common electrode CE constitute a display pixel PX together with a pixel region which is a part of the liquid crystal layer 3 controlled by the liquid crystal molecular arrangement corresponding to the electric field from the pixel electrode PE and common electrode CE.

  Around the effective display portion 10A, a gate driver GD that sequentially drives the plurality of gate lines G1 to Gm so that the plurality of pixel switching elements W1 are conducted in units of rows, and the pixel switching elements W1 in each row correspond to the corresponding gate lines. A source driver SD that outputs a pixel voltage to each of the plurality of source lines SL1 to SLn in a period of conduction by driving G is disposed. In the present embodiment, the liquid crystal display panel DP has two gate drivers GD and GD. Each gate driver GD is connected to each of the gate lines G1 to Gm, and drive signals are input to the gate lines G1 to Gm from both ends by the two gate drivers GD and GD.

  The array substrate 12 has an extending portion 12 </ b> A extending from the edge 14 </ b> E of the counter substrate 14. The circuit board 5 is connected to the extending portion 12A via the flexible board FC. The circuit board 5 is provided with a control circuit CC that controls the gate drivers GD and GD and the source driver SD.

  The control circuit CC has a power supply circuit C2. The power supply circuit C2 includes a first capacitor CP1 and a bias circuit BC. A logic signal is input to the first capacitor CP1 from the external signal source SS via the second bus line BW2. In the present embodiment, the logic signal input to the first capacitor CP1 is a signal having a voltage amplitude of C-MOS level. That is, as shown in FIGS. 2 and 3, a signal having a voltage amplitude of about 3.3 V is input to the first capacitor CP1 via the second bus line BW2.

  The logic signal input to the first capacitor CP1 is capacitively coupled by the first capacitor CP1 and input to the bias circuit BC. The bias circuit BC has resistors R3, R4, R5 and a second capacitor CP2 arranged as shown in FIG. A power supply terminal to which a power supply voltage VDD is applied is connected in series to the resistors R3 and R4. One end of the resistor R3 is connected between the first capacitor CP1 and the output terminal of the power supply circuit C2. One end of each of the resistor R5 and the second capacitor CP2 is connected between the other end of the resistor R3 and one end of the resistor R4, and the other end is grounded.

  In this embodiment, the voltage source VDD is about 15.5 V, the resistance value of the resistor R3 is 330 KΩ, the resistance value of the resistor R4 is 18 KΩ, the resistance value of the resistor R5 is 82Ω, and the capacitance of the second capacitor CP2 is 0. .1 μF. Therefore, the bias potential Vth of the signal via the bias circuit BC is obtained by VDD × R5 / (R4 + R5), and is set to about 12.7 V in the present embodiment. The voltage signal set to the bias potential by the bias circuit BC is output to the level shifter circuit C1 of the gate driver GD via the first bus wiring BW1 as an output signal of the power supply circuit C2.

  The level shifter circuit C1 has an input terminal IT connected to the first bus line BW1, and is connected to the power supply circuit C2 of the control circuit CC by the bus line BW1. The signal output from the power supply circuit C2 is input as an input signal INP to the input terminal IT of the level shifter circuit C1 via the bus line BW1.

  The level shifter circuit C1 further includes a switching element W2 as a field shift transistor for level shift. In the present embodiment, the switching element W2 is a P-channel thin film transistor.

  The gate electrode of the switching element W2 is connected to the input terminal IT. That is, the input terminal IT is set to the bias potential Vth, and when the logic signal is input by capacitive coupling, a potential changed from the bias potential is supplied to the logic signal, and falls below the threshold voltage Vth of the switching element W2. Occasionally, the switching element W2 is controlled to be in an on state, and conduction between the source and the drain is established.

  The source electrode and the drain electrode of the switching element W2 are connected to a pair of power supply terminals to which a power supply voltage larger than the voltage amplitude (3.3 V) of the logic signal input to the power supply circuit C2 is applied. That is, the drain voltage VSS is applied to the drain electrode of the switching element W2 via the resistor R1, and the source voltage VDD is applied to the source electrode. In the present embodiment, the drain voltage VSS is about −6 V, and the resistance value of the resistor R1 is 10 kΩ.

  From the above, when the switching element W2 is conductive between the source and the drain, negative charge with respect to the drain electrode VSS is applied to the gate electrode, and when non-conductive, positive charge with respect to the source voltage VDD is applied to the gate electrode. The threshold voltage Vth of the switching element W2 is a value between a high level (H) and a low level (L) of a signal applied from the power supply circuit C2 to the gate electrode of the switching element W2.

  At this time, as shown in FIG. 3, when the logic signal input to the first capacitor CP1 is at a high level, the voltage applied to the gate electrode becomes a value equal to or higher than the threshold voltage Vth with respect to the source voltage VSS, and the switching element W2 Does not conduct between the source and drain. When the logic signal input to the first capacitor CP1 is at a low level, the voltage applied to the gate electrode of the switching element W2 becomes a value equal to or lower than the threshold voltage Vth with respect to the source voltage VDD, so that the source-drain of the switching element W2 There is conduction between them.

  That is, when the source-drain of the switching element W2 is conductive, the output signal OUTP of the level shifter circuit C1 is equal to the source voltage VDD. When the source-drain is not conductive, the output signal OUTP of the level shifter circuit C1 is the drain voltage VSS. Is equal to The output signal OUTP is used for driving the gate line G as a clock signal, a start pulse, and a polarity inversion control pulse.

  Further, the control circuit CC outputs a control signal CTX generated based on a synchronization signal input from the external signal source SS and a video signal Sp input from the external signal source SS to the source driver XD, and further, a common electrode The common voltage Vcom applied to CE is output to the common electrode CE of the counter substrate 14. In the control circuit CC, a period for writing the video signal is set based on the synchronization signal input from the external signal source SS.

  The gate driver GD sequentially drives the plurality of gate lines G1 to Gm so that the level shifter circuit C1 sequentially selects the rows of the plurality of display pixels PX at a predetermined timing. On the other hand, the source driver XD outputs a video signal for one row as a video level pixel voltage while each of the gate lines G1 to Gm is driven. The pixel voltage for one row is applied to the display pixel PX in the selected row via the corresponding pixel switching element W1.

  As described above, in this embodiment, the pixel switching element W1 and the switching element W2 of the level shifter circuit C1 have the same conductivity type. Therefore, according to the liquid crystal display panel DP according to the present embodiment, as described above, the gate driver GD includes the level shifter circuit C1, so that the manufacturing process is not increased. That is, it is possible to provide a level shifter circuit with reduced manufacturing costs and a flat display panel including the level shifter circuit.

  Next, a second embodiment of the present invention will be described. The display panel according to the second embodiment is the same as the first embodiment except that the pixel switching element W1 and the switching element W2 of the level shifter circuit C1 are N-channel type, the configuration of the level shifter circuit C1, and the configuration of the bias circuit BC. Since the liquid crystal display panel DP is the same as the liquid crystal display panel DP, the same components are denoted by the same reference numerals and description thereof is omitted.

  As in the case of the first embodiment, the control circuit CC has a power supply circuit C2, and the power supply circuit C2 has a first capacitor CP1 and a bias circuit BC. The first capacitor CP1 receives a logic signal having a voltage of C-MOS level, that is, a signal of about 3.3V as shown in FIGS.

  The signal capacitively coupled by the first capacitor CP1 is biased to a predetermined potential by the bias circuit BC. The bias circuit BC has a configuration in which a voltage source for applying the voltage VSS and a resistor R8 are connected in series as shown in FIG. In this embodiment, the voltage source VSS is about −6 V, the resistance value of the resistor R8 is 330 KΩ, and the bias potential of the signal via the bias circuit BC is set to about −6 V (VSS).

  As for the signal set to the bias potential by the bias circuit BC, the output signal of the power supply circuit C2 is output to the level shifter circuit C1 of the gate driver GD via the bus wiring BW1. The level shifter circuit C1 has an input terminal IT connected to the first bus line BW1, and an output signal of the power supply circuit C2 is input from the input terminal IT as an input signal INN. The level shifter circuit C1 further includes a switching element W2. The gate electrode of the switching element W2 is connected to the bus line BW1, the source voltage VSS is applied to the source electrode, and the drain voltage VDD is applied to the drain electrode via the resistor R6.

  In this embodiment, the drain voltage VDD is 15.5V. The switching element W2 is a field effect transistor, and is an N-channel type thin film transistor in this embodiment. Therefore, when a positive charge with respect to the source voltage VSS is applied to the gate electrode, conduction between the source and the drain is established. In the present embodiment, the bias potential of the gate electrode of the switching element W2 is also about −6V of VSS. The threshold voltage Vth of the switching element W2 is a value between a high level (H) and a low level (L) of a signal applied from the power supply circuit C2 to the gate electrode of the switching element W2.

  At this time, as shown in FIG. 5, when the logic signal input to the first capacitor CP1 is at a high level (H), the voltage applied to the gate electrode of the switching element W2 becomes a value equal to or higher than the threshold voltage Vth. Conduction is established between the source and drain of W2. When the logic signal input to the first capacitor CP1 is at a low level (L), the voltage applied to the gate electrode of the switching element W2 becomes a value equal to or lower than the threshold voltage Vth, so that the source and drain of the switching element W2 are conductive. do not do.

  That is, when the source-drain of the switching element W2 is conductive, the output signal OUTN of the level shifter circuit C1 is equal to the source voltage VSS. When the source-drain is not conductive, the output signal OUTN of the level shifter circuit C1 is the drain voltage VDD. Is equal to

  In the present embodiment, the pixel switching element W1 and the switching element W2 of the level shifter circuit C1 have the same conductivity type. Therefore, the liquid crystal display panel according to the present embodiment can provide the same effects as those of the first embodiment. That is, it is possible to provide a level shifter circuit with reduced manufacturing costs and a flat display panel including the level shifter circuit.

  Note that the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage.

  In addition, various inventions can be formed by appropriately combining a plurality of constituent elements disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, you may combine suitably the component covering different embodiment.

1 schematically shows a liquid crystal display panel as a display panel according to an embodiment of the present invention. FIG. FIG. 3 is a diagram illustrating a configuration example of a level shifter circuit of a gate driver and a power supply circuit of a control circuit shown in FIG. 1. FIG. 3 is a diagram illustrating an operation example of the level shifter circuit and the power supply circuit illustrated in FIG. 2. FIG. 6 is a diagram illustrating another configuration example of the level shifter circuit of the gate driver and the power supply circuit of the control circuit shown in FIG. 1. FIG. 5 is a diagram illustrating another operation example of the level shifter circuit and the power supply circuit illustrated in FIG. 4.

Explanation of symbols

  DP ... Liquid crystal display panel, W1 ... Pixel switching element, PX ... Display pixel, GD ... Gate driver, SD ... Source driver, C2 ... Power supply circuit, BC ... Bias circuit, VDD ... Voltage source, C1 ... Level shifter circuit, IT ... Input Terminal, W2 ... Switching element, Vth ... Threshold voltage, VSS ... Voltage source, CP1 ... First capacitor

Claims (8)

A level shifter circuit provided on a display panel for level shifting an input signal,
A pair of power supply terminals to which a power supply voltage larger than the voltage amplitude of the input signal is applied;
A level-shifting field effect transistor connected between the pair of power supply terminals;
A bias potential that is set to a bias potential corresponding to a threshold value of the level shift field effect transistor and that changes from the bias potential in response to the input signal when the input signal is input by capacitive coupling is used as the level shift electric field. An input terminal for supplying to the gate of the effect transistor;
The level shifter circuit is the same conductivity type as the pixel switching field effect transistor.   2. The level shifter circuit according to claim 1, wherein the input voltage is a logic signal at a CMOS level.   2. The level shifter circuit according to claim 1, wherein the level shift field effect transistor is made of the same semiconductor material as the pixel switching field effect transistor.   2. The level shifter circuit according to claim 1, wherein the level shift field effect transistor is a low temperature polysilicon thin film transistor. A display panel including a plurality of display pixels arranged in a matrix and a plurality of pixel switching field effect transistors respectively connected to the plurality of display pixels;
A drive circuit for driving a plurality of pixel switching field effect transistors corresponding to each row of the plurality of display pixels,
The drive circuit has a level shifter circuit provided on the display panel for level shifting the input signal,
The level shifter circuit includes:
A pair of power supply terminals to which a power supply voltage larger than the voltage amplitude of the input signal is applied;
A level shift field effect transistor connected between the pair of power supply terminals, and a bias potential corresponding to a threshold value of the level shift field effect transistor, and the input when the input signal is input by capacitive coupling An input terminal that supplies a potential changed from the bias potential in response to a signal to the gate of the level shift field effect transistor;
The level shift field transistor is the same conductivity type as the pixel switching field effect transistor.   The display panel according to claim 5, wherein the drive circuit further includes a bias circuit that sets the input terminal to the bias potential and a capacitor that supplies the input signal to the input terminal outside the display panel.   The display panel according to claim 5, wherein the input signal is a logic signal at a CMOS level.   6. The display panel according to claim 5, wherein the level shift field effect transistor and the pixel switching field effect transistor are low-temperature polysilicon thin film transistors.

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