JP2007199350A - ELECTRO-OPTICAL DEVICE, MANUFACTURING METHOD THEREOF, AND ELECTRONIC DEVICE - Google Patents

Abstract

In an electro-optical device such as a liquid crystal, a laminated structure and a manufacturing process are simplified, and high-quality display is enabled.
A liquid crystal device is disposed on a TFT array substrate on a TFT array substrate, a scanning line extending along the X direction, a TFT having a gate connected to the scanning line, and an upper layer than the TFT. A storage capacitor 70 in which a lower electrode 71, a dielectric film 75, and an upper electrode 300a are laminated in order from the lower layer side. Further, the pixel electrode 9a is disposed on the upper layer side of the storage capacitor 70, is connected to the storage capacitor 70 and the drain of the TFT 30, and is disposed on the lower layer side of the TFT 30, and is connected to the source of the TFT 30. A data line 6a extending along the Y direction so as to at least partially include a region facing the channel region 1a 'of the TFT 30 when viewed in plan on the TFT array substrate 10, and including a conductive light-shielding film; Is provided.
[Selection] Figure 5

Description

  The present invention relates to an electro-optical device such as a liquid crystal device and a manufacturing method thereof, and a technical field of an electronic apparatus such as a liquid crystal projector including the electro-optical device.

  This type of electro-optical device includes, on a substrate, a pixel electrode, a scanning line for selectively driving the pixel electrode, a data line, and a TFT (Thin Film Transistor) as a pixel switching element. The active matrix driving is possible. In addition, a storage capacitor may be provided between the TFT and the pixel electrode for the purpose of increasing the contrast. The above components are formed on the substrate at a high density, so that the pixel aperture ratio can be improved and the device can be downsized (see, for example, Patent Document 1).

  As described above, the electro-optical device is required to have higher display quality, smaller size, and higher definition, and various measures other than the above are taken. For example, when light is incident on the semiconductor layer of the TFT, a light leakage current is generated and the display quality is deteriorated. Therefore, a light shielding layer is provided around the semiconductor layer in order to improve the light resistance of the electro-optical device. . The storage capacity is preferably as large as possible, but on the other hand, it is desirable to design so as not to sacrifice the pixel aperture ratio.

JP 2002-156652 A

  However, according to the technique described above, the layered structure on the substrate is basically complicated and sophisticated as the functions and performance become higher. This further leads to an increase in complexity of the manufacturing method and a decrease in manufacturing yield. On the other hand, if the laminated structure on the substrate and the manufacturing process are to be simplified, there is a technical problem that the display quality may be deteriorated due to insufficient storage capacity or light shielding performance.

  The present invention has been made in view of the above-mentioned problems, for example, and is suitable for simplifying a laminated structure and a manufacturing process, and capable of high-quality display, a manufacturing method thereof, and a method thereof It is an object to provide an electronic apparatus including such an electro-optical device.

  In order to solve the above problems, an electro-optical device of the present invention includes a scanning line extending along a first direction on a substrate, a thin film transistor having a gate electrically connected to the scanning line, and the thin film transistor. Is disposed on the upper layer side, a storage capacitor in which a lower electrode, a dielectric film, and an upper electrode are stacked in order from the lower layer side, and is disposed on an upper layer side than the storage capacitor, and the storage capacitor and the A pixel electrode electrically connected to a drain of the thin film transistor, and disposed on a lower layer side than the thin film transistor, electrically connected to a source of the thin film transistor, and viewed in plan on the substrate, It extends along a second direction intersecting the first direction so as to at least partially include a region facing the channel region, and does not include a conductive light shielding film. And a data line.

  According to the electro-optical device of the present invention, during the operation, the scanning signal is sequentially supplied to the gate of the thin film transistor through the scanning line, the image signal is supplied to the source of the thin film transistor through the data line, and the image signal is supplied to the pixel electrode. And written to the storage capacity. Accordingly, a predetermined type of operation such as active matrix driving in a plurality of pixels can be performed. At this time, due to the presence of the storage capacitor, the potential holding characteristic of the pixel electrode is improved, and display characteristics such as contrast and flicker can be improved.

  Here, for example, the scanning line, the data line, the storage capacitor, and the thin film transistor are the light that actually contributes to the display in each pixel corresponding to the pixel electrode in plan view on the substrate (that is, in each pixel). Is disposed in a non-opening region surrounding a region where light is transmitted or reflected. That is, these scanning lines, data lines, storage capacitors, and thin film transistors are arranged not in the opening area of each pixel but in the non-opening area so as not to hinder display.

  In the present invention, in particular, the data line is arranged on the lower layer side than the thin film transistor, and each scan line extends so as to at least partially include a region facing the channel region of the thin film transistor when viewed in plan on the substrate. It extends along a second direction (that is, for example, the column direction or the Y direction) that intersects the existing first direction (that is, for example, the row direction or the X direction) and includes a conductive light shielding film. Therefore, the data line causes the thin film transistor channel region to return to the return light, such as back-surface reflection on the substrate or light emitted from another electro-optical device by a multi-plate projector or the like, and penetrating the composite optical system. Can be shielded from light. In other words, the data line can function as a wiring for supplying an image signal and can also function as a light-shielding film of the thin film transistor for the return light. Therefore, during the operation as described above, the light leakage current in the thin film transistor is reduced, the contrast ratio can be improved, and high-quality image display is possible. If the data line is arranged on the upper layer side than the thin film transistor, the light shielding film of the thin film transistor for the return light needs to be formed as a layer different from the data line (that is, a lower layer side than the thin film transistor). However, according to the present invention, since the data line also functions as a light shielding film for the return light, it is not necessary to form the light shielding film for the return light as a layer different from the data line. That is, the laminated structure can be simplified as compared with the case where the data line is arranged on the upper layer side than the thin film transistor. In addition, with such a data line, for example, the edge part of the opening area in each pixel extending in the direction along the data line, in other words, the outline part of the non-opening area along the data line is partially defined. Is also possible. Accordingly, the light shielding film formed on the upper side of the thin film transistor and the black matrix or black mask formed on the counter substrate side can be partially omitted. From this point of view, the laminated structure on the substrate and the overall structure of the electro-optical device can be simplified.

  Furthermore, in the present invention, since the data line is disposed on the lower layer side than the thin film transistor, a contact hole for electrically connecting the data line and the source of the thin film transistor can be provided on the lower layer side than the thin film transistor. It is not necessary to provide it on the upper layer side than the thin film transistor. Therefore, the storage capacitor disposed on the upper layer side of the thin film transistor can be formed so as to overlap with the contact hole that electrically connects the data line and the source of the thin film transistor when viewed in plan on the substrate. The storage capacitor can be formed in a wider area. Therefore, the capacity of the storage capacity can be increased. As a result, display characteristics such as contrast and flicker, that is, display quality can be improved. In addition, since it is not necessary to provide a contact hole for electrically connecting the data line and the source of the thin film transistor on the upper layer side of the thin film transistor in this way, for example, an upper electrode disposed on the upper layer side of the thin film transistor is electrically connected. It is possible to relatively freely lay out a plane layout of the connected capacitance lines and the like. Therefore, for example, a layout in which the opening area is expanded, that is, the opening ratio of each pixel (that is, the ratio of the opening area to the entire area in each pixel) is improved, for example, the wiring width is narrowed.

  As a result, it is possible to reduce the light leakage current or increase the capacity of the storage capacitor while simplifying the laminated structure on the substrate, thereby enabling high-quality image display. Furthermore, simplification of the laminated structure on the substrate leads to simplification of the manufacturing process and improvement of yield, and the reliability of the device itself is enhanced. Note that simplification of the laminated structure on the substrate also leads to a reduction in manufacturing cost.

  In one aspect of the electro-optical device of the present invention, the data line includes a refractory metal film as the conductive light shielding film.

  According to this aspect, since the data line includes a refractory metal film such as tungsten (W), titanium (Ti), titanium nitride (TiN), etc., the light shielding performance of the data line can be improved. Furthermore, it is possible to perform a high temperature process after forming the data lines. That is, for example, when forming a thin film transistor after forming a data line, a layer made of a semiconductor film of the thin film transistor may be formed by a process performed in a relatively high temperature environment such as a low pressure CVD (Chemical Vapor Deposition) method. Is possible.

  In the aspect in which the data line includes the refractory metal film, the refractory metal film may include at least one of tungsten, titanium nitride, and titanium.

  In this case, the channel region of the thin film transistor can be more reliably shielded from the return light from the lower layer side by the data line. As a result, light leakage current in the thin film transistor is reduced, and high-quality image display is possible.

  In another aspect of the electro-optical device of the present invention, the data line and the source are connected to each other through a contact hole, and a plug is formed of a conductive material in the contact hole.

  According to this aspect, the data line and the source of the thin film transistor can be electrically interconnected satisfactorily through the contact hole.

  In another aspect of the electro-optical device of the present invention, the electro-optical device includes an interlayer insulating film that is stacked between the data line and the thin film transistor and subjected to a planarization process.

  According to this aspect, the data line and the thin film transistor are stacked on the substrate via the interlayer insulating film. On the surface of the interlayer insulating film immediately after the lamination, irregularities due to the lower data line occur. Therefore, if the unevenness thus formed is removed by a planarization process such as a chemical polishing process (Chemical Mechanical Polishing: CMP), a polishing process, a spin coat process, or a recess embedding process, the surface of the interlayer insulating layer becomes Flattened. Therefore, the resistance of the data line can be reduced by increasing the thickness of the data line. That is, even if the thickness of the data line is increased, the surface of the interlayer insulating film is flattened. For example, a liquid crystal or the like is provided between the substrate having the laminated structure as described above and the opposite substrate facing the substrate. When the electro-optical material is sandwiched, since the substrate surface is flat, the possibility of causing disturbance in the orientation state of the electro-optical material can be reduced, and a higher-quality display can be achieved.

  In another aspect of the electro-optical device according to the aspect of the invention, a concave portion that is recessed toward the data line is formed on a surface of the substrate facing the data line in at least a part of a region facing the data line. Is formed.

  According to this aspect, the data line is formed in the concave portion formed on the upper layer side surface of the substrate. Therefore, the unevenness on the substrate that may be caused by the thickness of the data line can be reduced, and the occurrence of disturbance in the alignment state of the electro-optical material such as liquid crystal can be reduced or prevented.

  In another aspect of the electro-optical device according to the aspect of the invention, the data line includes a main line portion extending along the second direction and an extension portion extending along the first direction from the main line portion. .

  According to this aspect, the extension portion extending along the second direction can reduce the return light from both sides of the data line toward the first direction when viewed in plan on the substrate, and the light in the thin film transistor Leakage current can be further reduced. In addition, by such an extended portion, for example, the edge portion of the opening region in each pixel extending in the direction along the scanning line, in other words, the contour portion of the non-opening region along the scanning line is partially defined. Is also possible.

  In another aspect of the electro-optical device of the present invention, the lower electrode is made of a polysilicon film, and the upper electrode is made of a metal film.

  According to this aspect, the storage capacitor is formed by sequentially laminating the lower electrode made of the polysilicon film, the upper electrode made of the dielectric film and the metal film from the lower layer side. That is, the storage capacitor has a MIS (Metal-Insulator-Semiconductor) structure in which a semiconductor film, an insulator film, and a metal film are sequentially stacked. Therefore, a dielectric film is formed by forming a high temperature oxide film, that is, an HTO (High Temperature Oxide) film by oxidizing the upper surface of the lower electrode, or after laminating a dielectric film on the lower electrode. By improving the density of the dielectric film by performing a baking process for baking the body film, the breakdown voltage of the storage capacitor can be increased, and the occurrence of leakage current can be suppressed or prevented. That is, since the lower electrode is made of a polysilicon film, it is compared with a case where the lower electrode is made of a metal film such as aluminum (Al), for example, by a relatively high temperature heat treatment that can be performed during oxidation treatment or baking treatment. Thus, it is possible to suppress or prevent the lower electrode from melting.

  In another aspect of the electro-optical device according to the aspect of the invention, the lower electrode is electrically connected to the drain and the pixel electrode, and the upper electrode is electrically connected to a capacitor line that supplies a fixed potential. .

  According to this aspect, the lower electrode functions as a pixel potential side electrode to which a pixel potential is supplied, and the upper electrode functions as a fixed potential side electrode to which a fixed potential is supplied. Here, the “fixed potential” means a potential that is fixed at least for a predetermined period regardless of the content of the image data, and may be a fixed potential that is completely fixed at a constant potential with respect to the time axis. The fixed potential may be fixed at a constant potential for a certain period of time with respect to the time axis. Therefore, since it is not necessary to flow a large current at the lower electrode at a higher speed than the upper electrode, the lower electrode can be formed from impurity-doped polysilicon having a relatively high resistance. Note that “the upper electrode is electrically connected to the capacitor line” means that the capacitor line and the upper electrode are made of different conductive films, and these are directly laminated or via a contact hole or the like. This includes the case where the capacitor line and the upper electrode are integrated as well as the case where they are electrically connected. In other words, this means that a part of the capacitor line also functions as the upper electrode.

  Note that the upper electrode may be electrically connected to the drain and the pixel electrode, and the lower electrode may be electrically connected to a capacitor line that supplies a fixed potential.

  In the above-described aspect in which the upper electrode is made of a metal film, the storage capacitor may be arranged in a region including a region facing the channel region when viewed in plan on the substrate.

  In this case, the storage capacitor is disposed in a region including a region facing the channel region of the thin film transistor when viewed in plan on the substrate and is disposed on the upper layer side of the thin film transistor. It consists of a metal film such as a film. Therefore, the channel region of the thin film transistor can be shielded by the upper electrode with respect to incident light from the upper layer side.

  In the aspect in which the upper electrode is made of a metal film and the storage capacitor is disposed in a region including a region facing the channel region, the upper electrode may be configured to include a light-shielding metal.

  In this case, the upper electrode is made of a single-layer film or a multilayer film of a light-shielding metal such as titanium (Ti), titanium nitride (TiN), tungsten (W) or the like having a higher light-shielding property in addition to aluminum. For this reason, the channel region of the thin film transistor can be more reliably shielded from incident light from the upper layer side by the upper electrode that can be disposed close to the channel region. As a result, light leakage current in the thin film transistor is reduced, and high-quality image display is possible.

  In order to solve the above-described problems, an electronic apparatus according to the present invention includes the above-described electro-optical device according to the present invention (including various aspects thereof).

  According to the electronic apparatus of the present invention, the above-described electro-optical device of the present invention is provided, so that a high-quality image can be displayed, such as a television, a mobile phone, an electronic notebook, a word processor, a viewfinder type, or a monitor direct view type. Various electronic devices such as a video tape recorder, a workstation, a videophone, a POS terminal, a touch panel, and an image forming apparatus such as a printer, a copy, and a facsimile using an electro-optical device as an exposure head can be realized. In addition, as the electronic apparatus of the present invention, for example, an electrophoretic device such as electronic paper, an electron emission device (Field Emission Display and Conduction Electron-Emitter Display), and the like can be realized.

  In order to solve the above problems, a method of manufacturing an electro-optical device according to the present invention includes a scanning line extending along a first direction on a substrate, a thin film transistor electrically connected to the scanning line, and a lower side. A storage capacitor in which an electrode, a dielectric film, and an upper electrode are stacked in order from the lower layer side, a pixel electrode disposed on the upper layer side of the storage capacitor, and a second direction that intersects the first direction An electro-optical device manufacturing method for manufacturing an electro-optical device including a data line that includes at least partially a region facing a region to be a channel region of the thin film transistor when viewed in plan on the substrate And a data line forming step of forming the data line from a conductive light-shielding film along the second direction, and the source is electrically connected to the data line via the interlayer insulating film from the data line. Connect The step of forming the thin film transistor, the step of forming the scanning line along the first direction so as to be electrically connected to the gate of the thin film transistor, and the lower side above the thin film transistor Forming the storage capacitor so that the electrode, the dielectric film, and the upper electrode are sequentially stacked from the lower layer side and electrically connected to the thin film transistor; and on the upper layer side of the storage capacitor And sequentially forming a pixel electrode so as to be electrically connected to the storage capacitor and the drain of the thin film transistor.

  According to the electro-optical device manufacturing method of the present invention, the above-described electro-optical device of the present invention can be manufactured. In particular, since the laminated structure on the substrate is relatively simple, the manufacturing process can be simplified and the yield can be improved. Note that simplification of the manufacturing process leads to a reduction in manufacturing cost.

  An aspect of the method for manufacturing an electro-optical device according to the invention includes a planarization step of performing a planarization process on the interlayer insulating film.

  According to this aspect, since the interlayer insulating film on the upper layer side of the data line is planarized by the planarization process, the resistance of the data line is reduced by increasing the thickness of the data line by the data line formation process. be able to. That is, even if the thickness of the data line is increased by the data line formation process, the surface of the interlayer insulating film is planarized by the subsequent planarization process. When an electro-optic material such as liquid crystal is sandwiched between a counter substrate facing the substrate, since the substrate surface is flat, the possibility of causing disturbance in the alignment state of the electro-optic material can be reduced. Higher quality display is possible.

  In another aspect of the method for manufacturing an electro-optical device according to the aspect of the invention, before the data line forming step, at least a part of the region facing the data line on the surface of the substrate facing the data line. And a recess forming step of forming a recess recessed toward the data line by etching.

  According to this aspect, the recess can be formed on the substrate relatively easily by the recess forming step. Therefore, unevenness on the substrate that can be caused by the thickness of the data line formed in the subsequent data line forming step can be reduced. Therefore, it is possible to reduce or prevent the disturbance of the alignment state of the electro-optical material such as liquid crystal.

  The operation and other advantages of the present invention will become apparent from the best mode for carrying out the invention described below.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, a driving circuit built-in type TFT active matrix driving type liquid crystal device, which is an example of the electro-optical device of the present invention, is taken as an example.
<First Embodiment>
The liquid crystal device according to the first embodiment will be described with reference to FIGS.

  First, the overall configuration of the liquid crystal device according to the present embodiment will be described with reference to FIGS. 1 and 2. FIG. 1 is a plan view showing the configuration of the liquid crystal device according to this embodiment, and FIG. 2 is a cross-sectional view taken along the line H-H 'in FIG.

  1 and 2, in the liquid crystal device according to the present embodiment, a TFT array substrate 10 and a counter substrate 20 are arranged to face each other. A liquid crystal layer 50 is sealed between the TFT array substrate 10 and the counter substrate 20, and the TFT array substrate 10 and the counter substrate 20 are provided with a sealing material 52 provided in a seal region positioned around the image display region 10a. Are bonded to each other.

  In FIG. 1, a light-shielding frame light-shielding film 53 that defines the frame area of the image display region 10a is provided on the counter substrate 20 side in parallel with the inside of the seal region where the sealing material 52 is disposed. A data line driving circuit 101 and an external circuit connection terminal 102 are provided along one side of the TFT array substrate 10 in a region located outside the sealing region in which the sealing material 52 is disposed in the peripheral region. The sampling circuit 7 is provided so as to be covered with the frame light shielding film 53 on the inner side of the seal region along the one side. Further, the scanning line driving circuit 104 is provided so as to be covered with the frame light-shielding film 53 inside the seal region along two sides adjacent to the one side. On the TFT array substrate 10, vertical conduction terminals 106 for connecting the two substrates with the vertical conduction material 107 are arranged in regions facing the four corner portions of the counter substrate 20. Thus, electrical conduction can be established between the TFT array substrate 10 and the counter substrate 20.

  On the TFT array substrate 10, a lead wiring 90 is formed for electrically connecting the external circuit connection terminal 102 to the data line driving circuit 101, the scanning line driving circuit 104, the vertical conduction terminal 106, and the like. .

  In FIG. 2, on the TFT array substrate 10, a laminated structure in which pixel switching TFTs as drive elements, wiring lines such as scanning lines and data lines are formed is formed. In the image display area 10a, a pixel electrode 9a made of a transparent material such as ITO (Indium Tin Oxide) is provided on the upper layer of a pixel switching TFT, a scanning line, a data line or the like. On the other hand, a light shielding film 23 is formed on the surface of the counter substrate 20 facing the TFT array substrate 10. A counter electrode 21 made of a transparent material such as ITO is formed on the light shielding film 23 so as to face the plurality of pixel electrodes 9a. Further, the liquid crystal layer 50 is made of, for example, a liquid crystal in which one or several types of nematic liquid crystals are mixed, and takes a predetermined alignment state between the pair of alignment films.

  Although not shown here, in addition to the data line driving circuit 101 and the scanning line driving circuit 104, the TFT array substrate 10 is used for inspecting the quality, defects, etc. of the liquid crystal device during manufacturing or at the time of shipment. An inspection circuit, an inspection pattern, or the like may be formed.

  Next, an electrical configuration of the pixel portion of the liquid crystal device according to the present embodiment will be described with reference to FIG. FIG. 3 is an equivalent circuit diagram of various elements, wirings, and the like in a plurality of pixels formed in a matrix forming the image display area of the liquid crystal device according to this embodiment.

  In FIG. 3, a plurality of pixel portions formed in a matrix in the image display region 10a (see FIG. 1) of the liquid crystal device according to the present embodiment are used for switching control of the pixel electrode 9a and the pixel electrode 9a, respectively. , And a data line 6a to which image signals S1, S2,..., Sn (where n is a natural number) is supplied is electrically connected to the source of the TFT 30. The TFT 30 is an example of the “thin film transistor” according to the present invention.

  Further, the scanning line 3a is electrically connected to the gate of the TFT 30, and the scanning signals G1, G2,..., Gm are applied to the scanning line 3a in a pulse-sequential manner in this order at a predetermined timing. It is configured. The pixel electrode 9a is electrically connected to the drain of the TFT 30, and the image signal S1, S2,..., Sn supplied from the data line 6a is obtained by closing the switch of the TFT 30 as a switching element for a certain period. Write at a predetermined timing.

  Image signals S1, S2,..., Sn written at a predetermined level on the liquid crystal of the liquid crystal layer 50 (see FIG. 2) via the pixel electrode 9a are held for a certain period with the counter electrode 21 formed on the counter substrate. Is done. The liquid crystal modulates light and enables gradation display by changing the orientation and order of the molecular assembly depending on the applied voltage level. In the normally white mode, the transmittance for incident light is reduced according to the voltage applied in units of each pixel, and in the normally black mode, the light is incident according to the voltage applied in units of each pixel. The light transmittance is increased, and light having a contrast corresponding to an image signal is emitted from the liquid crystal device as a whole.

  In order to prevent the image signal held here from leaking, a storage capacitor 70 is added in parallel with the liquid crystal capacitor formed between the pixel electrode 9a and the counter electrode 21 (see FIGS. 1 and 2). . The storage capacitor 70 is provided side by side with the scanning line 3a, and includes a fixed potential side capacitor electrode and a capacitor line 300 having a predetermined potential. The storage capacitor 70 improves the charge retention characteristics of each pixel electrode. Note that the potential of the capacitor line 300 may be constantly fixed to one voltage value, or may be fixed while being swung to a plurality of voltage values at a predetermined period.

  Next, a specific configuration of the pixel portion that realizes the above-described operation will be described with reference to FIGS. FIG. 4 is a plan view of a plurality of pixel groups adjacent to each other on the TFT array substrate on which the data lines, scanning lines, pixel electrodes and the like are formed in the liquid crystal device according to this embodiment. FIG. It is sectional drawing in the AA 'line. In FIG. 5, the scale of each layer / member is different for each layer / member to have a size that can be recognized on the drawing.

  4 and 5, each circuit element of the pixel portion described above with reference to FIG. 3 is structured on the TFT array substrate 10 as a patterned conductive film. The TFT array substrate 10 is made of, for example, a glass substrate, a quartz substrate, an SOI substrate, a semiconductor substrate, and the like, and is disposed to face the counter substrate 20 made of, for example, a glass substrate or a quartz substrate. Each circuit element includes, in order from the bottom, a first layer including the data line 6a and the like, a second layer including the TFT 30 and the like, a third layer including the storage capacitor 70 and the like, and a fourth layer including the pixel electrode 9a and the like. . Also, the base insulating film 12 is provided between the first layer and the second layer, the first interlayer insulating film 41 is provided between the second layer and the third layer, and the second interlayer insulating film 42 is provided between the third layer and the fourth layer. It is provided and prevents the above-described elements from being short-circuited.

  As shown in FIG. 4, the data line 6a, the scanning line 3a, the TFT 30, the capacitor line 300, and the lower electrode 71 are open areas of each pixel corresponding to the pixel electrode 9a when viewed in plan on the TFT array substrate 10. In other words, each pixel is disposed in a non-opening region surrounding a region where light that actually contributes to display is transmitted or reflected. That is, the data line 6a, the scanning line 3a, the TFT 30, the capacitor line 300, and the lower electrode 71 are arranged not in the opening area of each pixel but in the non-opening area so as not to hinder display.

(Structure of the first layer-data lines, etc.)
4 and 5, the first layer is constituted by data lines 6a. The data line 6a extends along the Y direction in FIG. The data line 6a is an example of the “conductive light shielding film” according to the present invention. For example, the data line 6a is made of refractory metal such as tungsten (W), titanium (Ti), chromium (Cr), tantalum (Ta), and molybdenum (Mo). It can be formed of a metal simple substance including at least one of them, an alloy, a metal nitride, a metal silicide, a polysilicide, or a laminate thereof.

  Particularly in the present embodiment, the data line 6a is arranged on the lower layer side of the TFT 30 (see FIG. 5) so as to include a region facing the channel region 1a (see FIG. 4), and includes a conductive light shielding film. Yes. Therefore, the channel region 1a of the TFT 30 with respect to the return light such as light reflected from the back surface of the TFT array substrate 10 by the data line 6a or light emitted from another liquid crystal device by a multi-plate projector or the like and penetrating through the composite optical system. ′ Can be shielded almost or preferably completely. That is, the data line 6a functions as a wiring for supplying the image signals S1, S2,... Sn, and functions as a light shielding film for the TFT 30 with respect to the return light. Therefore, during the operation of the liquid crystal device, the light leakage current in the TFT 30 is reduced, the contrast ratio can be improved, and high-quality image display is possible. If the data line is arranged on the upper layer side than the TFT 30, it is necessary to form the light shielding film of the TFT 30 for returning light as a layer different from the data line (that is, a layer on the lower side of the TFT 30). However, in particular, in this embodiment, the data line 6a also functions as a light-shielding film for the return light. Therefore, it is not necessary to form the light-shielding film for the return light as a layer different from the data line 6a. That is, the laminated structure can be simplified as compared with the case where the data line 6a is arranged on the upper layer side than the TFT 30.

  Here, a first modification of the present embodiment will be described with reference to FIG. FIG. 6 is a plan view showing a planar layout of data lines according to the first modification. In FIG. 6, components such as the storage capacitor 70 and the pixel electrode 9a are not shown.

  As shown in FIG. 6, the data line 6a may include a main line portion 60 extending along the Y direction and an extending portion 61 extending from the main line portion 60 along the X direction. In this way, the extension portion 61 extending along the X direction can reduce the return light from both sides of the data line 6a in the Y direction as viewed in plan on the TFT array substrate 10, The light leakage current in the TFT 30 can be further reduced. Furthermore, the extended portion 61 can partially define the edge portion of the opening region in each pixel extending in the X direction, in other words, the contour portion of the non-opening region along the scanning line 3a.

(Second layer configuration-TFT, etc.)
4 and 5, the second layer is composed of the TFT 30. The TFT 30 has an LDD (Lightly Doped Drain) structure, for example, and as described above, the scanning line 3a functioning as a gate electrode, the semiconductor layer 1a, and the insulating film 2 including the gate insulating film that insulates the scanning line 3a from the semiconductor layer 1a. It has. The scanning line 3a extends along the X direction in FIG. The scanning line 3a is made of, for example, conductive polysilicon. The semiconductor layer 1a is made of, for example, polysilicon, and includes a channel region 1a ′, a low concentration source region 1b and a low concentration drain region 1c, and a high concentration source region 1d and a high concentration drain region 1e. The TFT 30 preferably has an LDD structure. However, the TFT 30 may have an offset structure in which impurities are not implanted into the low-concentration source region 1b and the low-concentration drain region 1c. It may be a self-aligned type in which a high concentration source region and a high concentration drain region are formed by implanting the film.

  The high concentration source region 1 d of the TFT 30 is electrically connected to the data line 6 a via a contact hole 81 formed in the base insulating film 12. The contact hole 81 is plugged with a conductive material, and the high concentration source region 1d and the data line 6a are electrically connected to each other well. The base insulating film 12 is made of, for example, a silicon oxide film, and insulates the first layer and the second layer. The base insulating film 12 is an example of the “interlayer insulating film” according to the present invention.

  In particular, in the present embodiment, the surface of the base insulating film 12 is planarized by a planarization process such as CMP, polishing process, or spin coat process. Therefore, the resistance of the data line 6a can be reduced by increasing the thickness of the data line 6a. That is, even if the thickness of the data line 6a is increased, the surface of the base insulating film 12 is flattened by the flattening process, so that the liquid crystal molecules of the liquid crystal layer 50 are formed by the unevenness caused by the thickness of the data line 6a. The possibility of causing disturbance in the orientation state of the film can be reduced.

  The TFT 30 according to the present embodiment is a top gate type, but may be a bottom gate type. Further, the semiconductor layer 1a constituting the TFT 30 may be a non-single crystal layer or a single crystal layer. A known method such as a bonding method can be used for forming the single crystal layer. By making the semiconductor layer 1a a single crystal layer, it is possible to improve the performance of peripheral circuits in particular.

  Here, a second modification of the present embodiment will be described with reference to FIG. FIG. 7 is a sectional view having the same concept as in FIG. 5 according to the second modification.

  As shown in FIG. 7, the upper surface of the TFT array substrate 10 has a recess 6d that is recessed upward, and the data line 6a is formed in the recess 6d. That is, the recess 6d is formed by digging the upper surface of the TFT array substrate 10 so as to include a region where the data line 6a is to be formed when viewed in plan on the TFT array substrate 10. The data line 6a is embedded in such a recess 6d. Therefore, it is possible to reduce or prevent the surface of the base insulating film 12 from being uneven due to the thickness of the data line 6a. In other words, the surface of the base insulating film 12 can be planarized by embedding the data line 6a in the recess 6d. Accordingly, it is possible to reduce the possibility of causing disturbance in the alignment state of the liquid crystal molecules in the liquid crystal layer 50 due to the unevenness caused by the thickness of the data line 6a. Further, by increasing the thickness of the data line 6a and increasing the depth of the recess 6d according to the thickness of the data line 6a, the resistance of the data line 6a can be reduced while the surface of the base insulating film 12 is flattened. Can be achieved. In addition to the process of filling the data line 6a into the recess 6d, the surface of the base insulating film 12 may be subjected to a planarization process such as the above-described CMP, polishing process, or spin coat process.

  Furthermore, a third modification of the present embodiment will be described with reference to FIG. FIG. 8 is a sectional view showing a contact hole for electrically connecting the pixel switching TFT and the data line according to the third modification.

  As shown in FIG. 8, the plug formed in the contact hole 81 that electrically connects the high concentration source region 1d of the TFT 30 and the data line 6a is a first made of a refractory metal such as tungsten (W). The plug layer 91 and the second plug layer 92 made of impurity-doped polysilicon may be stacked in order. In this way, the high concentration source region 1d and the data line 6a can be electrically connected satisfactorily even when a high temperature treatment of about 1000 ° C. is performed when forming the TFT 30.

(3rd layer configuration-storage capacity, etc.)
4 and 5, the fourth layer includes a storage capacitor 70. The storage capacitor 70 is provided on the upper layer side of the TFT 30 via the first interlayer insulating film 41, and the lower electrode 71 connected to the high-concentration drain region 1 e of the TFT 30 and the pixel electrode 9 a and one capacitor line 300. The upper electrode 300a is formed by opposingly disposing the upper electrode 300a with a dielectric film 75 therebetween.

  The lower electrode 71 is made of a conductive polysilicon film, and is electrically connected to the high-concentration drain region 1 e of the TFT 30 through a contact hole 83 opened in the first interlayer insulating film 41. That is, the lower electrode 71 functions as a pixel potential side capacitance electrode that is set to the pixel potential. The extending portion of the lower electrode 71 is electrically connected to the pixel electrode 9 a through a contact hole 85 that is opened through the second interlayer insulating film 42. That is, the lower electrode 71 has a function of electrically connecting the pixel electrode 9a and the high-concentration drain region 1e of the TFT 30 via the contact holes 83 and 85 in addition to the function as a pixel potential side capacitor electrode. . As will be described later, an HTO film is formed on the upper layer side of the lower electrode 71.

  The first interlayer insulating film 41 and the second interlayer insulating film 42 are each formed of, for example, NSG (non-silicate glass). In addition, the first interlayer insulating film 41 and the second interlayer insulating film 42 are silicate glasses such as PSG (phosphorus silicate glass), BSG (boron silicate glass), and BPSG (boron phosphorus silicate glass), silicon nitride, and silicon oxide, respectively. Etc. can be used.

  The dielectric film 75 is made of a relatively thin silicon nitride (SiN) film having a thickness of about 5 to 300 nm, for example. From the viewpoint of increasing the storage capacitor 70, the thinner the dielectric film 75 is, the better as long as the reliability of the film is sufficiently obtained. As will be described later, the dielectric film 75 is fired to increase its density.

  The upper electrode 300a is formed as a part of the capacitor line 300, and functions as a fixed potential side capacitor electrode disposed to face the lower electrode 71. As viewed in a plan view, the capacitor line 300 is formed so as to overlap the formation region of the data line 6a as shown in FIG. More specifically, the capacitor line 300 includes a main line portion that extends along the data 6a, and protruding portions that respectively protrude in the left-right direction along the scanning line 3a from each portion that intersects the scanning line 3a in the drawing. Yes. The protruding portion contributes to an increase in the formation region of the storage capacitor 70 using the region on the scanning line 3a. The capacitor line 300 extends from the image display region 10a in which the pixel electrode 9a is disposed to the periphery thereof, and is electrically connected to a constant potential source to be a fixed potential. As such a constant potential source, for example, a constant potential source such as a positive power source or a negative power source supplied to the data line driving circuit 101 or a counter electrode potential supplied to the counter electrode 21 of the counter substrate 20 may be used. .

  Here, the storage capacitor according to the present embodiment will be described in detail with reference to FIG. FIG. 9 is a partially enlarged sectional view of the portion C1 in FIG.

  As shown in FIG. 9, the storage capacitor 70 is formed by laminating a lower electrode 71, a dielectric film 75, and an upper electrode 300a in order from the lower layer side. An HTO film 72 is formed on the upper layer side of the lower electrode 71 as will be described later.

  In FIG. 9, the lower electrode 71 is made of a conductive polysilicon film, and the upper electrode 300a is made of aluminum or the like. That is, the storage capacitor 70 has a MIS structure in which a semiconductor film, an insulator film, and a metal film are sequentially stacked. On the upper layer side of the lower electrode 71, an HTO film 72 is formed. The HTO film 72 is made of a high-temperature silicon oxide film formed by an oxidation process for oxidizing the upper surface of the lower electrode 71 made of a polysilicon film, or a film formed by LP (Low Pressure) -CVD. Thus, the withstand voltage of the storage capacitor 70 is increased by the HTO film 72 formed between the lower electrode 71 and the dielectric film 75. Here, since the lower electrode 71 is made of a polysilicon film, it is assumed that the lower electrode 71 is oxidized by a heat treatment at a relatively high temperature as compared with the case where the lower electrode 71 is made of a metal film such as aluminum. 71 hardly melts.

  In FIG. 9, the dielectric film 75 is increased in density by being fired, that is, the breakdown voltage of the storage capacitor 70 is increased. Therefore, the occurrence of leakage current in the storage capacitor 70 can be suppressed or prevented. Here, since the lower electrode 71 is made of a polysilicon film, the lower electrode 71 is subjected to a baking process involving a heat treatment at a relatively high temperature as compared with the case where the lower electrode 71 is made of a metal film such as aluminum. 71 hardly melts. The dielectric film 75 is a single layer film or a multilayer film of a high dielectric constant material such as silicon oxide (SiO 2), tantalum oxide (Ta 2 O 5), hafnium oxide (HfO 2), alumina (Al 2 O 3), in addition to SiN. Also good. Or it is good also as a multilayer film with the low dielectric constant material whose dielectric constant is lower than these high dielectric constant materials.

  In FIG. 9, the upper electrode 300a (in other words, the capacitor line 300) is formed of a multilayer film having a laminated structure in which a first light shielding layer 311, a conductive layer 320, and a second light shielding layer 312 are sequentially laminated from the lower layer side. Both the first light shielding layer 311 and the second light shielding layer 312 are formed of a titanium nitride (TiN) film, and the conductive layer 320 is formed of an aluminum (Al) film.

  As shown in FIG. 4 again, the storage capacitor 70 is disposed in a region including a region facing the channel region 1a of the TFT 30 when viewed in plan on the TFT array substrate 10, and is disposed on the upper layer side of the TFT 30. Yes. Therefore, the channel region 1a ′ of the TFT 30 can be shielded against incident light from the upper layer side by the upper electrode 300a made of a metal film. The first light shielding layer 311 and the second light shielding layer 312 may be formed of a refractory metal film such as a titanium (Ti) film or a tungsten (W) film in addition to the TiN film.

(Fourth layer configuration-pixel electrode, etc.)
4 and 5, a second interlayer insulating film 42 is formed on the entire surface of the third layer, and further, a pixel electrode 9a is formed thereon as a fourth layer. The surface of the second interlayer insulating film 42 is subjected to a planarization process such as CMP similarly to the base insulating film 12.

  The pixel electrode 9a (indicated by the broken line 9a 'in FIG. 4) is arranged in each of the pixel areas partitioned vertically and horizontally, and the data lines 6a and the scanning lines 3a are arranged in a grid at the boundaries. (See FIGS. 4 and 5). The pixel electrode 9a is made of a transparent conductive film such as ITO.

  The pixel electrode 9 a is electrically connected to the extending portion of the lower electrode 71 through a contact hole 85 that penetrates the second interlayer insulating film 42. Further, as described above, the lower electrode 71 is electrically connected to the high concentration drain region 1e of the TFT 30. That is, the pixel electrode 9a and the high concentration drain region 1e of the TFT 30 are relay-connected through the extending portion of the lower electrode 71. Therefore, it is possible to avoid a situation in which the interlayer distance between the pixel electrode 9a and the high-concentration drain region 1e is long and it is difficult to connect the two with a single contact hole.

  An alignment film 16 that has been subjected to a predetermined alignment process such as a rubbing process is provided above the pixel electrode 9a.

  The above is the configuration of the pixel portion on the TFT array substrate 10 side.

  On the other hand, the counter substrate 20 is provided with a counter electrode 21 on the entire surface of the counter substrate 20, and an alignment film 22 is further provided thereon (under the counter electrode 21 in FIG. 5). As with the pixel electrode 9a, the counter electrode 21 is made of a transparent conductive film such as an ITO film. A light-shielding film 23 is provided between the counter substrate 20 and the counter electrode 21 so as to cover at least a region facing the TFT 30 in order to prevent generation of light leakage current in the TFT 30.

  A liquid crystal layer 50 is provided between the TFT array substrate 10 thus configured and the counter substrate 20. The liquid crystal layer 50 is formed by sealing liquid crystal in a space formed by sealing the peripheral portions of the substrates 10 and 20 with a sealing material 52 (see FIGS. 1 and 2). The liquid crystal layer 50 takes a predetermined alignment state by the alignment film 16 and the alignment film 22 that have been subjected to an alignment process such as a rubbing process in a state where an electric field is not applied between the pixel electrode 9 a and the counter electrode 21. It is like that.

  The configuration of the pixel portion described above is common to each pixel portion as shown in FIGS. Such pixel portions are periodically formed in the image display area 10a (see FIG. 1). On the other hand, in such a liquid crystal device, as described with reference to FIGS. 1 and 2, the scanning line driving circuit 104, the data line driving circuit 101, and the like are driven in the peripheral area located around the image display area 10a. A circuit is formed.

  Next, the arrangement of the capacitive lines of the liquid crystal device according to this embodiment will be described in detail with reference to FIGS. 10 is a plan view of a plurality of adjacent pixel groups of the liquid crystal device according to the present embodiment, FIG. 11 is a cross-sectional view taken along line BB ′ of FIG. 10, and FIG. FIG. 11 is a cross-sectional view taken along the line CC ′ of FIG. 13 is a plan view having the same concept as in FIG. 10 in the comparative example, FIG. 14 is a cross-sectional view taken along line DD ′ in FIG. 13, and FIG. 15 is taken along line EE ′ in FIG. FIG. 10 and 13, the data line 6a and the pixel electrode 9a are not shown. In FIGS. 12 and 15, the elements on the alignment film 16, the liquid crystal layer 50, and the counter substrate 20 side are not shown.

  In the present embodiment, the data line 6 a extends in the Y direction when viewed in plan on the TFT array substrate 10. Particularly in the present embodiment, the data line 6a is disposed on the lower layer side of the TFT 30 as described above with reference to FIGS. Therefore, as shown in FIGS. 10 and 11, the capacitor line 300 disposed on the upper layer side of the TFT 30 is viewed in plan on the TFT array substrate 10 along the Y direction so as to overlap with the data line 6a. Wiring can be done without disconnection. Therefore, as shown in FIGS. 10 and 12, the capacitor line 300 can be wired so as to be divided in the X direction. In other words, it is not necessary to electrically connect the upper electrode 300 a provided in each pixel adjacent to each other along the X direction by the capacitor line 300.

  As shown as a comparative example in FIGS. 13 and 14, if the data line 6 a is arranged on the upper layer side of the storage capacitor 70, the data to be arranged on the opposite side to the capacitor line 300. In order to form the contact hole 810 that electrically connects the line 6a and the high-concentration source region 1d, it is difficult to wire the capacitor line 300 without dividing it along the Y direction. Above, it must be divided in the Y direction. For this reason, as shown in FIG. 13, the capacitor line 300 needs to be wired along the X direction without being divided. In other words, the wiring is performed so as to connect the upper electrodes 300a provided in the pixels adjacent to each other along the X direction. Further, as shown in FIG. 13 and FIG. 15, the capacitor line 300 does not overlap with the contact hole 85 that electrically connects the pixel electrode 9 a and the lower electrode 71 on the TFT array substrate 10 in plan view. It is necessary to wire as follows. That is, it is necessary to dispose both the contact hole 85 and the capacitor line 300 within the light shielding width d2 in the X direction (that is, the direction along the scanning line 3a) when viewed in plan on the TFT array substrate 10. . Therefore, it is difficult to reduce the light shielding width d2, that is, to improve the aperture ratio of the pixel. As shown in FIG. 14, in the comparative example described above, a light shielding film 11 a for return light is provided on the lower layer side than the TFT 30. Further, a third interlayer insulating film 43 is provided for interlayer insulation between the data line 6 a and the pixel electrode 9 a provided on the upper layer side of the storage capacitor 70.

  However, in this embodiment, in particular, as described above, since the data line 6a is disposed on the lower layer side of the TFT 30, the capacitor line 300 can be wired so as to be divided in the X direction. That is, it is not necessary to wire the upper electrodes 300a provided in the pixels adjacent to each other along the X direction. Therefore, as shown in FIG. 10, when viewed in plan on the TFT array substrate 10, only the contact hole 85 can be disposed within the light shielding width d1 in the X direction, that is, the contact hole 85 within the light shielding width d1. It is not necessary to dispose both the capacitor line 300 and the capacitor line 300. Therefore, the light shielding width d1 can be reduced, that is, the aperture ratio of the pixel can be improved.

In the comparative example described above with reference to FIGS. 13 to 15, if the capacitor line is formed from a conductive film different from the upper electrode, which is disposed on the upper layer side than the data line, in the Y direction. Capacitance lines can be wired without being divided along the line, but the laminated structure may be complicated and the cost may be increased.
Second Embodiment
Next, a liquid crystal device according to a second embodiment will be described with reference to FIGS. FIG. 16 is a plan view having the same concept as in FIG. 4 in the second embodiment, and FIG. 17 is a cross-sectional view taken along line FF ′ in FIG. 16 and 17, the same reference numerals are given to the same components as the components according to the first embodiment shown in FIGS. 1 to 15, and the description thereof will be omitted as appropriate.

  As shown in FIGS. 16 and 17, in the present embodiment, in particular, the plurality of TFTs 30 are TFT arrays in a pair of TFTs 30 arranged adjacent to each other in the Y direction (that is, the direction along the data line 6a). As viewed in plan on the substrate 10, the high-concentration source region 1d and the high-concentration drain region 1e are arranged so as to be mirror-symmetric with respect to the Y direction. Further, a contact hole 820 for electrically connecting the high-concentration drain region 1e of the i-th TFT 30 (i) in the Y direction (where i is an even number or an odd number) to the data line 6a, and a Y direction The contact hole 820 that electrically connects the high-concentration drain region 1e of the (i + 1) th TFT 30 (i + 1) to the data line 6a is common. Other configurations are substantially the same as those of the liquid crystal device according to the first embodiment described above.

  As shown in FIGS. 16 and 17, in the present embodiment, in particular, the plurality of TFTs 30 are respectively a high concentration source region 1 d and a high concentration drain region in the pair of TFTs 30 arranged adjacent to each other in the Y direction. They are arranged so that the directions of 1e are mirror-symmetric with each other. For example, if the vertical direction is the Y direction, the pair of TFTs 30 are TFTs 30 that are vertically inverted or mirrored vertically. The plurality of TFTs 30 arranged in mirror symmetry in this way include a contact hole 820 that connects the i-th TFT 30 (i) and the data line 6a in the Y direction, and an i + 1-th TFT 30 (i + 1) in the Y direction. And the contact hole 820 connecting the data line 6a are common.

  Therefore, the high-concentration drain region 1e and the data line 6a for both the pair of TFTs (TFT 30 (i) and TFT 30 (i + 1) in the figure) can be electrically connected only by one contact hole 820. It becomes possible.

  That is, according to the present embodiment, as compared with the case where the storage capacitor 70 is provided separately for each pixel and the TFT 30 and the data line 6a are electrically connected via the contact hole 820 for each pixel. The number of contact holes can be drastically reduced. As a pair of TFTs, preferably, all TFTs are paired with adjacent TFTs, and the contact hole 820 is common to each pair. Thereby, the effect of reducing the number of contact holes as described above can be obtained to the maximum. However, if there is only one pair of TFTs with a common contact hole 820, the effect of reducing the number of contact holes as described above can be obtained accordingly.

As a result, according to the liquid crystal device of the present embodiment, it is possible to achieve downsizing and high definition by narrowing the pitch while improving the display characteristics by the storage capacitor 70.
<Manufacturing method>
Next, a method for manufacturing the liquid crystal device according to the first embodiment will be described with reference to FIGS. 18 to 22 are process cross-sectional views showing a series of manufacturing steps for manufacturing the liquid crystal device according to the present embodiment. 18, 19, 21, and 22 are shown corresponding to the cross-sectional view of the pixel portion shown in FIG. 5, and FIG. 20 is a partially enlarged cross-sectional view of the storage capacitor shown in FIG. 9. Correspondingly shown. Here, in the liquid crystal device according to the first embodiment, the process of forming the scanning lines, TFTs, data lines, storage capacitors, and pixel electrodes, which are main parts, will be mainly described.

  First, as shown in FIG. 18, in the data line forming step, a conductive light-shielding film such as tungsten (W) or titanium (Ti) is laminated on the TFT array substrate 10 in a predetermined pattern, and the data line is formed. 6a is formed. Thereafter, a precursor film 12 a of the base insulating film 12 is formed on the entire surface of the TFT array substrate 10. On the surface of the precursor film 12a, unevenness due to the lower data line 6a occurs. Therefore, the precursor film 12a is formed thick, and is ground to the position of the dotted line in the drawing by, for example, CMP, and the surface thereof is flattened to obtain the base insulating film 12. The base insulating film 12 is formed by, for example, TEOS (tetraethyl orthosilicate) gas, TEB (tetraethyl boatrate) gas, or TMOP (tetramethyloxyphosphate) by atmospheric pressure or low pressure CVD. Using a gas or the like, a silicate glass film such as NSG, PSG, or BSG, a nitride film, a silicon oxide film, or the like is used. The thickness of the base insulating film 12 is, for example, about 500 nm to 2000 nm, preferably about 800 nm.

  Next, as shown in FIG. 19, after etching is performed at a predetermined position on the surface of the base insulating film 12, a contact hole 81 having a depth reaching the data line 6a is formed, and then the contact hole 81 is made of a conductive material. Form a plug. Subsequently, the TFT 30 is formed in a region corresponding to the intersection of the data line 6a and the scanning line 3a as a gate electrode. Note that a normal semiconductor integration technique can be used in the process of forming the TFT 30. Further, in the process of forming the TFT 30, heat treatment such as annealing or annealing is performed, and the characteristics of the TFT 30 are improved. The annealing temperature at this time is about 900 to 1300 ° C., preferably about 1000 ° C., for example.

  Next, a first interlayer insulating film 41 is formed on the entire surface of the TFT array substrate 10. The first interlayer insulating film 41 is made of, for example, a silicate glass film such as NSG, PSG, or BSG, a nitride film, a silicon oxide film, or the like using TEOS gas, TEB gas, TMOP gas, or the like by atmospheric pressure or low pressure CVD. It is formed. The film thickness of the first interlayer insulating film 41 is, for example, about 500 nm to 2000 nm, preferably about 800 nm. Here, preferably, annealing is performed at a high temperature of about 800 ° C. to improve the film quality of the first interlayer insulating film 41. Note that after the formation of the first interlayer insulating film 41, the surface thereof may be planarized by, for example, a CMP process.

  Next, etching is performed at a predetermined position on the surface of the first interlayer insulating film 41 to form a contact hole 83 having a depth reaching the high-concentration drain region 1e. Subsequently, a conductive polysilicon film is laminated in a predetermined pattern, and the lower electrode 71 is formed. The lower electrode 71 is connected to the high-concentration drain region 1e through a contact hole 83.

  Subsequently, as shown in FIG. 20A, an upper surface of the lower electrode 71 made of a polysilicon film is oxidized, or an HTO film 72 made of a high-temperature silicon oxide film is formed by LP-CVD. Form.

  Next, as shown in FIG. 20B, an SiN film is laminated on the HTO film 72 by an atomic layer deposition method, that is, an ALD (Atomic Layer Deposition) method, thereby forming a dielectric film 75. At this time, a baking process for baking the dielectric film 75 is performed. Therefore, the density of the dielectric film 75 can be improved, and the breakdown voltage of the storage capacitor 70 can be increased. Furthermore, since the dielectric film 75 is formed by laminating dielectric materials by the ALD method, the dielectric film 75 can be formed thinner and with higher accuracy. According to the present embodiment, since the withstand voltage of the storage capacitor 70 is increased by the baking treatment on the HTO film 72 and the dielectric film 75, little or preferably no leakage current is generated even if the dielectric film 75 is formed thin. do not do. That is, it is possible to form a storage capacitor 70 having a high breakdown voltage and a large capacity. The dielectric film 75 may be formed as a single layer film or a multilayer film of a high dielectric constant material such as SiO 2, Ta 2 O 5, HfO 2, Al 2 O 3 in addition to SiN. Alternatively, it may be formed as a multilayer film together with a low dielectric constant material having a lower dielectric constant than these high dielectric constant materials.

  Next, as shown in FIG. 20C, the upper electrode 300a (in other words, the capacitor line 300) is formed in a predetermined pattern. That is, first, TiN is laminated in a predetermined pattern on the dielectric film 75 to form the first light shielding layer 311. Next, Al is laminated in a predetermined pattern on the first light shielding layer 311 to form the conductive layer 320. Next, TiN is laminated in a predetermined pattern on the conductive film 320 to form a second light shielding film 312. At this time, the upper electrode 300a is formed as a predetermined pattern in a region including a region facing the channel region 1a ′ of the TFT 30 when viewed in plan on the TFT array substrate 10. Therefore, the channel region 1a ′ of the TFT 30 can be reliably shielded by the upper electrode 300a including the first light shielding layer 311 and the second light shielding layer 312.

  Next, as shown in FIG. 21, the second surface made of a silicate glass film such as NSG, PSG, BSG or the like is formed on the entire surface of the TFT array substrate 10 by TEOS gas, for example, by plasma CVD performed at less than 500 ° C. An interlayer insulating film 42 is formed. The film thickness of the second interlayer insulating film 42 is about 400 nm, for example. Therefore, when the second interlayer insulating film 42 is formed, a process of heating to, for example, 500 ° C. or higher is not necessary. Therefore, the second interlayer insulating film 42 can be formed with little or preferably no melting of the upper electrode 300a made of a metal film (in other words, the capacitor line 300). Note that the second interlayer insulating film 42 may be formed by a high-density plasma CVD method. Note that after the formation of the second interlayer insulating film 42, the surface thereof may be planarized by CMP treatment or the like.

  Next, as shown in FIG. 22, etching is performed at a predetermined position on the surface of the second interlayer insulating film 42 to form a contact hole 85 having a depth reaching the extending portion of the lower electrode 71. Subsequently, a transparent conductive film such as ITO is laminated in a predetermined pattern to form the pixel electrode 9a. The pixel electrode 9 a is connected to the extended portion of the lower electrode 71 through a contact hole 85. Therefore, the pixel electrode 9 a is electrically connected to the high-concentration drain region 1 e by the extending portion of the lower electrode 71.

  According to the manufacturing method of the liquid crystal device described above, the liquid crystal device of the first embodiment described above can be manufactured. Particularly in this embodiment, since the laminated structure on the TFT array substrate 10 is relatively simple, the manufacturing process can be simplified and the yield can be improved. Note that simplification of the manufacturing process leads to a reduction in manufacturing cost.

  Next, a modified example of the above-described liquid crystal device manufacturing method will be described with reference to FIG. FIG. 23 is a process cross-sectional view showing a recess forming process and a data line forming process according to a modification of the manufacturing method of the liquid crystal device of this embodiment.

  As shown in FIG. 23 as a modified example, before the data line forming step for forming the data line 6a, in the region for forming the data line 6a on the surface of the TFT array substrate 10 by the recess forming step, A recessed recess 6d may be formed.

  That is, first, as shown in FIG. 23 (a), a recess 6d is formed by etching the region where the data line 6a is to be formed on the surface of the TFT array substrate 10 by the recess forming step. To do.

Next, as shown in FIG. 23B, a conductive light-shielding film such as tungsten (W) or titanium (Ti) is laminated in the recess 6d on the TFT array substrate 10 by the data line forming step. The data line 6a is formed. Thereafter, a base insulating film 12 is formed on the entire surface of the TFT array substrate 10. That is, the data line 6a is formed so as to be embedded in the recess 6d. Therefore, it is possible to reduce or prevent the surface of the base insulating film 12 from being uneven due to the thickness of the data line 6a. Note that after the formation of the base insulating film 12, the surface thereof may be planarized by CMP treatment or the like.
<Electronic equipment>
Next, the case where the liquid crystal device which is the above-described electro-optical device is applied to various electronic devices will be described.

  First, a projector using this liquid crystal device as a light valve will be described. FIG. 24 is a plan view showing a configuration example of the projector. As shown in FIG. 24, a projector 1100 includes a lamp unit 1102 made of a white light source such as a halogen lamp. The projection light emitted from the lamp unit 1102 is separated into three primary colors of RGB by four mirrors 1106 and two dichroic mirrors 1108 arranged in the light guide 1104, and serves as a light valve corresponding to each primary color. The light enters the liquid crystal panels 1110R, 1110B, and 1110G.

  The configurations of the liquid crystal panels 1110R, 1110B, and 1110G are the same as those of the liquid crystal device described above, and are driven by R, G, and B primary color signals supplied from the image signal processing circuit. The light modulated by these liquid crystal panels enters the dichroic prism 1112 from three directions. In the dichroic prism 1112, R and B light is refracted at 90 degrees, while G light travels straight. Therefore, as a result of the synthesis of the images of the respective colors, a color image is projected onto the screen or the like via the projection lens 1114.

  Here, paying attention to the display images by the liquid crystal panels 1110R, 1110B, and 1110G, the display image by the liquid crystal panel 1110G needs to be horizontally reversed with respect to the display images by the liquid crystal panels 1110R and 1110B.

  In addition, since light corresponding to each primary color of R, G, and B is incident on the liquid crystal panels 1110R, 1110B, and 1110G by the dichroic mirror 1108, it is not necessary to provide a color filter.

  In addition to the electronic device described with reference to FIG. 24, a mobile personal computer, a mobile phone, a liquid crystal television, a viewfinder type, a monitor direct view type video tape recorder, a car navigation device, a pager, and an electronic notebook , Calculators, word processors, workstations, videophones, POS terminals, devices with touch panels, and the like. Needless to say, the present invention can be applied to these various electronic devices.

  The present invention is not limited to the above-described embodiment, and can be appropriately changed without departing from the gist or concept of the invention that can be read from the claims and the entire specification. A method for manufacturing an electro-optical device and an electronic apparatus including the electro-optical device are also included in the technical scope of the present invention.

It is a top view which shows the whole structure of the liquid crystal device which concerns on 1st Embodiment. It is the HH 'sectional view taken on the line of FIG. FIG. 3 is an equivalent circuit diagram of various elements and the like in the pixel of the liquid crystal device according to the first embodiment. FIG. 3 is a plan view (No. 1) of a plurality of adjacent pixel groups of the liquid crystal device according to the first embodiment. FIG. 5 is a cross-sectional view taken along line AA ′ in FIG. 4. It is a top view which shows the plane layout of the data line which concerns on a 1st modification. It is sectional drawing of the same meaning as FIG. 5 which concerns on a 2nd modification. It is sectional drawing which shows the contact hole which electrically connects the TFT for pixel switching concerning a 3rd modification, and a data line. It is a partial expanded sectional view of the C1 part of FIG. FIG. 6 is a plan view (No. 2) of a plurality of adjacent pixel groups of the liquid crystal device according to the first embodiment. It is BB 'sectional view taken on the line of FIG. It is CC 'sectional drawing of FIG. It is a top view of the same meaning as FIG. 10 in a comparative example. FIG. 14 is a sectional view taken along line DD ′ of FIG. It is the EE 'sectional view taken on the line of FIG. It is a top view of the same meaning as FIG. 4 in 2nd Embodiment. It is the FF 'sectional view taken on the line of FIG. It is process sectional drawing (the 1) which shows a series of manufacturing processes which manufacture the liquid crystal device which concerns on 1st Embodiment. It is process sectional drawing (the 2) which shows a series of manufacturing processes which manufacture the liquid crystal device which concerns on 1st Embodiment. It is process sectional drawing (the 3) which shows a series of manufacturing processes which manufacture the liquid crystal device which concerns on 1st Embodiment. It is process sectional drawing (the 4) which shows a series of manufacturing processes which manufacture the liquid crystal device which concerns on 1st Embodiment. It is process sectional drawing (the 5) which shows a series of manufacturing processes which manufacture the liquid crystal device which concerns on 1st Embodiment. It is process sectional drawing which shows the recessed part formation process and data line formation process which concern on the modification of the manufacturing method of the liquid crystal device which concerns on 1st Embodiment. It is a top view which shows the structure of the projector which is an example of the electronic device to which the electro-optical apparatus is applied.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1a '... Channel area | region, 2 ... Insulating film, 3a ... Scan line, 6a ... Data line, 9a ... Pixel electrode, 7 ... Sampling circuit, 10 ... TFT array substrate, 10a ... Image display area, 12 ... Underlayer insulating film, 16 Alignment film, 20 counter substrate, 21 counter electrode, 23 light shielding film, 22 alignment film, 30 TFT, 41 first interlayer insulation film, 42 second interlayer insulation film, 50 liquid crystal layer, 52 ... Sealing material, 53 ... Frame light shielding film, 70 ... Storage capacitor, 71 ... Lower electrode, 72 ... HTO film, 75 ... Dielectric film, 81, 83, 85, 810, 820 ... Contact hole, 91 ... First plug Layer ... 92 Second plug layer 101 ... Data line drive circuit 102 ... External circuit connection terminal 104 ... Scanning line drive circuit 106 ... Vertical conduction terminal 107 ... Vertical conduction material 300 ... Capacitor line 300a ... Upper side Electrodes, 311 ... th Shielding layer, 312 ... second shielding layer, 320 ... conductive layer

Claims (15)

On the board
A scan line extending along a first direction;
A thin film transistor having a gate electrically connected to the scan line;
The storage capacitor is arranged on the upper layer side than the thin film transistor, and the lower electrode, the dielectric film and the upper electrode are sequentially stacked from the lower layer side, and
A pixel electrode disposed above the storage capacitor and electrically connected to the storage capacitor and the drain of the thin film transistor;
The thin film transistor is disposed on a lower layer side than the thin film transistor, is electrically connected to a source of the thin film transistor, and includes at least part of a region facing the channel region of the thin film transistor when viewed in plan on the substrate. An electro-optical device comprising: a data line extending along a second direction intersecting the first direction and including a conductive light shielding film.   2. The electro-optical device according to claim 1, wherein the data line includes a refractory metal film as the conductive light shielding film.   The electro-optical device according to claim 2, wherein the refractory metal film includes at least one of tungsten, titanium nitride, and titanium. The data line and the source are connected to each other through a contact hole,
The electro-optical device according to claim 1, wherein a plug is formed from a conductive material in the contact hole.   5. The electro-optical device according to claim 1, further comprising an interlayer insulating film stacked between the data line and the thin film transistor and subjected to a planarization process. 6.   2. A concave portion that is depressed toward the data line is formed on a surface of the substrate facing the data line in at least a part of a region facing the data line. 6. The electro-optical device according to any one of items 1 to 5.   7. The data line according to claim 1, wherein the data line includes a main line portion extending along the second direction and an extension portion extending from the main line portion along the first direction. 8. The electro-optical device according to claim 1. The lower electrode is made of a polysilicon film,
The electro-optical device according to claim 1, wherein the upper electrode is made of a metal film. The lower electrode is electrically connected to the drain and the pixel electrode;
The electro-optical device according to any one of claims 1 to 8, wherein the upper electrode is electrically connected to a capacitor line that supplies a fixed potential.   10. The electro-optical device according to claim 8, wherein the storage capacitor is disposed in a region including a region facing the channel region when viewed in plan on the substrate.   The electro-optical device according to claim 10, wherein the upper electrode includes a light shielding metal.   An electronic apparatus comprising the electro-optical device according to claim 1. A storage capacitor in which a scanning line extending in the first direction on a substrate, a thin film transistor electrically connected to the scanning line, a lower electrode, a dielectric film, and an upper electrode are sequentially stacked from the lower layer side And an electro-optical device that manufactures an electro-optical device that includes a pixel electrode that is disposed on the upper layer side of the storage capacitor and a data line that extends along a second direction intersecting the first direction. A method,
Data for forming the data line from the conductive light-shielding film so as to at least partially include a region facing the channel region of the thin film transistor when viewed in plan on the substrate and along the second direction A line forming process;
Forming the thin film transistor so that a source is electrically connected to the data line on an upper layer side than the data line via an interlayer insulating film;
Forming the scan line along the first direction so as to be electrically connected to the gate of the thin film transistor;
The storage capacitor is formed on the upper layer side of the thin film transistor so that the lower electrode, the dielectric film, and the upper electrode are sequentially stacked from the lower layer side and are electrically connected to the thin film transistor. Process,
And a step of forming the pixel electrode so as to be electrically connected to the storage capacitor and the drain of the thin film transistor on the upper layer side of the storage capacitor.   The method of manufacturing an electro-optical device according to claim 13, further comprising a planarization step of performing a planarization process on the interlayer insulating film.   Before the data line forming step, a recess recessed toward the data line is formed by etching in at least a part of a region facing the data line on the surface of the substrate facing the data line. 15. The method for manufacturing an electro-optical device according to claim 13, further comprising a recess forming step.

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