JP2007193368A - Method for manufacturing electronic device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To expedite the development and product class extension TAT (turn around time) of an electronic device and to reduce a cost for manufacturing an electronic device by expediting the manufacturing TAT of a halftone phase shift mask to reduce the cost. <P>SOLUTION: The method for manufacturing an electronic device includes formation of a light-shielding auxiliary pattern of an organic film in a halftone phase shift mask. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a method for manufacturing an electronic device such as a semiconductor device or a wiring board device having a fine pattern.

For manufacturing a semiconductor circuit, a film formation process such as chemical vapor deposition (CVD), an impurity layer formation process such as ion implantation, a lithography process for forming a resist pattern, and an etching process are repeatedly used. As a method for increasing the operation speed of a semiconductor circuit or improving the degree of integration of a device, miniaturization of a circuit pattern and improvement of its dimensional accuracy are effective. In recent years, miniaturization and improvement of dimensional accuracy have been actively promoted. Since pattern miniaturization is mainly determined by lithography, lithography occupies an extremely important position in the manufacture of semiconductor devices.
In the lithography technique, a projection exposure apparatus is mainly used, and a photomask pattern mounted on the projection exposure apparatus is transferred onto a semiconductor wafer to form a device pattern.

  In recent years, miniaturization of patterns to be formed has been advanced in order to meet the demand for higher integration of devices and improvement in device operation speed. Under such a background, an exposure method called a halftone phase shift method is used. The halftone phase shift mask is a mask in which a translucent film (referred to as a halftone film) with respect to exposure light is formed on a transparent substrate (blanks). The transmittance of the film with respect to the exposure light is usually adjusted to 1% to 25%. The exposure light passing through this film is adjusted so that the phase is reversed with respect to the case without this film. The phase difference that brings out the highest resolution performance is 180 degrees and an odd multiple thereof, but if it is within 90 degrees before and after 180 degrees, there is an effect of improving resolution. It is known that the resolution is generally improved by about 5 to 20% when a halftone phase shift mask is used. In particular, the higher the transmittance of the halftone film, the higher the resolution due to the phase enhancement effect. On the other hand, an image called a sub-peak tends to occur in a field portion that is originally a light shielding portion, and becomes a source of abnormal transfer defects. This is a phenomenon that occurs because the phases of the interference light from the adjacent pattern and the light transmitted through the field portion are aligned and emphasized. As an example, a description will be given of an example of a sub-peak when light from four surroundings called a quadrupole is generated by interference in a direction in which each other is strengthened. FIG. 20A shows an example of a plan view of a pattern arrangement at the time of quadrupole, and FIG. 20B shows a cross section taken along A and A ′ in FIG. Here, 100 is quartz glass (blanks), 101 is a halftone film, and 103 is a circuit pattern. FIG. 14 shows a transfer optical image corresponding to the range from B to B ′ shown in FIG. It can be seen that the sub-peak increases as the transmittance of the halftone mask member increases. In order to suppress this phenomenon, in the case of a high transmittance halftone phase shift mask in which the transmittance of the halftone film is relatively high, a fine light shielding pattern of Cr is formed on the halftone film corresponding to the sub-peak pattern generation site, A method of cutting the transmitted light in that portion is used. This method is called a tri-tone half-tone phase shift method because it consists of three tones of a transmission part (glass part), a halftone part, and a light-shielding part (Cr part).

For example, JP-A-11-15130, JP-A-6-308715, JP-A-9-90601, and the like are described regarding the Tri-tone halftone phase shift.
Japanese Patent Laid-Open No. 11-15130 JP-A-6-308715

  In order to provide a highly integrated and / or high-speed LSI manufacturing method, it is necessary to form a circuit pattern with a fine dimension with high dimensional accuracy. For this reason, the Tri-tone halftone phase shift method having high resolution requires high dimensional accuracy and high phase control accuracy. In the halftone phase shift exposure method, the exposure light that passes through the halftone part and the exposure light that passes through the opening interfere with each other near the boundary between the opening and the halftone part to increase the optical contrast and increase the resolution and exposure tolerance. Improve the degree. For this reason, control of the amount of exposure light transmitted through the halftone portion, that is, transmittance control of the halftone portion and phase control are extremely important. The pattern dimension accuracy of the halftone film greatly affects the pattern dimension accuracy to be transferred. In a fine pattern near the resolution limit of the projection lens, the optical contrast is greatly reduced by light diffraction, so a factor called MEF (Mask Error enhancement Factor) is added and the dimensional accuracy of the pattern transferred above the pattern dimensional accuracy on the mask. Decreases. The MEF is an index representing how much the transferred pattern dimension difference ΔLm is amplified with respect to the mask dimension difference ΔLw, and is expressed by the following equation where M is the reduction ratio of the projection lens. Here, M becomes 1/5 when, for example, a 5x lens is used.

MEF = ΔLm / (M · ΔLw)
In a fine pattern using a halftone phase shift mask, the MEF is normally 2 to 3, that is, the dimensional variation of the mask is amplified by 2M to 3M times and transferred.

  Recent Tri-tone halftone masks require fine and extremely high accuracy such as a pattern size of 320 nm on the mask and a size accuracy of 9 nm on the mask. Therefore, the dimensional yield of this class is 10% to 30%. Very low. That is, on average, it is necessary to prepare 3 to 10 masks in order to manufacture one good mask, the mask cost is high, and the mask supply TAT (Turn Around Time) is also low.

  In addition, because of factors such as resist characteristic factors and substrate level difference structure factors, the position and size of the fine light-shielding pattern (auxiliary pattern) made of Cr to prevent unnecessary image transfer due to sub-peaks cannot be accurately predicted by simulation. . For this reason, even if the halftone phase shift film is a non-defective product in terms of dimensional accuracy, if a defect is found by transfer after the mask is created, the mask is remanufactured from the beginning, which causes a reduction in the mask supply TAT. It was.

  Further, in the semiconductor device, about 30 photomasks are used in the manufacturing process. One major factor that limits the development period of the semiconductor device is the supply of the photomask. In order to shorten the development period, improvement of the photomask supply TAT is essential. In addition, the development of mask ROM and logic IC types is often performed in the wiring process, and this type of development power is largely due to the supply TAT of the photomask for the wiring process.

  An object of the present invention is to provide a method for manufacturing an electronic device using a halftone phase shift mask formed on a halftone phase shift film and capable of easily reproducing a film that reduces or blocks exposure light.

  Another object of the present invention is to provide an electronic device manufacturing method capable of shortening a development period, a product development period, and a manufacturing cost by using a mask manufactured by a method having a high mask supply TAT. .

Among the inventions disclosed in this specification, the outline of typical ones is as follows.
Halftone phase shift having a translucent phase shift pattern having an opening and an auxiliary pattern mainly composed of an organic film disposed near the opening and having a light-reducing property or a light-shielding property with respect to exposure light A method for manufacturing an electronic device in which a pattern is formed on a substrate through a mask. By using a film that has a light-reducing property or light-shielding property for exposure light as an organic film, the organic film can be easily removed and regenerated without damaging the translucent phase shift film by ashing. It becomes easy. A step of preparing a transparent substrate on which a translucent phase shift film is formed; a step of forming a pattern having an opening in the translucent phase shift film; and a translucent phase shift film pattern in which the opening is formed And a step of forming an auxiliary pattern having a desired shape and having an organic film as a main component in the vicinity of the opening of the translucent phase shift film determined to be non-defective Preparing a halftone phase shift mask manufactured by the method, attaching the halftone phase shift mask to a projection exposure apparatus so that a surface on which the translucent phase shift film is formed faces downward, and the projection exposure And a step of transferring a pattern formed on the halftone phase shift mask onto a substrate disposed on a sample stage of the apparatus. After forming a halftone phase shift film pattern with poor yield, quality determination is performed, and only a non-defective product is formed with a light-reducing or light-shielding film with respect to exposure light. it can. That is, the light shielding pattern forming process is reduced by the amount that the light shielding pattern need not be formed on the mask substrate having the defective halftone phase shift film pattern. This step is reduced by 90% if the yield of the halftone phase shift film pattern is 10%, and reduced by 70% even if 30%. Further, since the mask is arranged in the exposure apparatus so that the surface on which the halftone phase shift film pattern is formed faces downward, the exposure light reaches the organic film after passing through the phase shift film. Therefore, the light intensity of the exposure light is reduced, the organic film is hardly deteriorated by the exposure light, and the number of times the mask is used can be increased.

  According to the present invention, the mask supply TAT of the halftone phase shift mask is shortened and the mask cost is reduced. This shortens the development period and product development period of an electronic device such as a semiconductor device manufactured using the mask, and reduces the manufacturing cost.

Before describing the present invention in detail, the meaning of terms in the present application will be described as follows.
1. “Halftone area”, “halftone film”, “halftone pattern”, “semitransparent film”, and “dim” are used to transmit 1% or more and 25% or less of the exposure light applied to the area. It shows that it has the optical characteristic to make. References to “light shielding region”, “light shielding film”, and “light shielding pattern” indicate that the exposure light emitted to the region has an optical characteristic such that transmitted light is less than 1%. On the other hand, the terms “transparent” and “transparent film” indicate optical properties that allow transmission of 60% or more of the exposure light applied to the region. Generally 90% or more is used.
2. “Photoresist pattern” refers to a film pattern obtained by patterning a photosensitive organic film by a photolithography technique. This pattern includes a simple resist film having no opening at all for the portion.
3. Here, the metal means a metal (mainly Cr, W, Ti, Ta, etc.) or a metal compound (mainly WN, TiW, etc.).

(Embodiment 1)
In the first embodiment, a photomask manufacturing method of the present invention will be described with reference to FIGS. FIG. 1 shows the structure of the photomask manufactured in the first embodiment. FIG. 1 (a) is a top view of the whole from the top, and FIG. 1 (b) is a view of A in FIG. 1 (a). It is sectional drawing which showed the structure of the cross section in A '. A halftone film 101 is formed on a mask blank 100 made of quartz glass. As mask blanks 100, optical glass or calcium fluoride crystal can be used in addition to quartz glass. As the material of the halftone film 101, MoSix is used here, but in addition to this, MoSixOy, MoSixOyNz, TaSixOy, ZrSixOy, SiNx, SiOxNy, CrOxFy (x, y, z represents a component ratio of 0 or more and 1 or less) or Those composite membranes can also be used. Here, the composite film includes a film of the same type, such as ZrSixOy and ZrSix'Oy ', in which the component ratio is changed. The circuit pattern 103 is formed in the form of an opening in the halftone film. In addition, a light shielding band 105 and an auxiliary pattern 104 for preventing sub-peak transfer are formed on the halftone film 101 as in a normal Tri-tone halftone mask. The light-shielding band is a light-shielding body that is formed to prevent abnormal resolution because the step boundary portion is exposed multiple times when step-and-repeat or step-and-scan exposure is performed. What is characteristic of the present invention is that the auxiliary pattern 104 and the light shielding band 105 are formed of a resist. FIG. 2 is a cross-sectional view of each process for manufacturing the photomask. As shown in FIG. 2A, a halftone film 101 is formed on a glass substrate 100 by sputtering or CVD, and a resist 110 is formed thereon. Here, MoSiO was used as the halftone film. In the case of KrF lithography, the film thickness is 135 nm under the phase inversion condition, and if it is formed in the range of 133 nm to 137 nm, the phase accuracy is within ± 3 °, and high-accuracy transfer can be performed. A negative resist or a positive resist may be used as the resist, but in the case of a tri-tone halftone mask, a positive resist is generally used in relation to an exposure area. Then, a desired circuit pattern (including OPC: Optical Proximity effect Correction) is exposed. In this exposure, the drawing alignment mark 106 pattern shown in FIG. 1A is also exposed. Here, an electron beam (EB) 111 is used as exposure light. In addition, light such as UV light having a wavelength of 365 nm or DUV light having a wavelength of 248 nm may be used as the exposure light. An electron beam is suitable for forming a fine pattern, and light is effective in shortening the exposure time. Thereafter, as shown in FIG. 2B, normal development is performed to form a resist pattern 112 on which a circuit pattern is formed. Thereafter, as shown in FIG. 2C, the pattern formed on the resist 110 was etched and transferred to the halftone film 101. Thereafter, as shown in FIG. 2D, the resist is removed and cleaning is performed to form a mask in which the circuit pattern 103 is formed on the halftone film 101. Thereafter, as shown in FIG. 2E, a resist 113 is formed, and a light shielding band pattern and auxiliary pattern exposure 114 are performed. It is a feature that both patterns are isolated patterns. In this exposure, the exposure is performed at a desired position with reference to the position of the drawing alignment mark 106 (see FIG. 1A) already formed on the halftone film. A negative resist is used as the resist 113. By using a negative resist, there is an advantage that the exposure area is small and the exposure time is shorter when a negative resist is used. Basically, the halftone film opening (103 portion) has a thick resist and a step, but by using a negative tone, this portion can be removed only by development without exposure, so the resist remaining due to insufficient exposure. The problem does not occur. Note that the resist used here has a light-shielding property or a light-reducing property with respect to the exposure light used when the photomask is printed on the wafer. For example, when the exposure light is ArF excimer laser light having a wavelength of 193 nm, a resist having a benzene ring structure, for example, a resist based on a phenol resin or a novolac resin is preferable. In the case where the exposure light is a KrF excimer laser beam with a wavelength of 248 nm, for example, an anthracene, naphthalene, phenanthrene or a derivative-bonded resin, or a photosensitive composition in which anthracene, naphthalene, phenanthrene or a derivative thereof is mixed with a resist resin is sufficient. Have good absorption. Moreover, not only a resist but photosensitive compositions, such as a black matrix agent which added the radical generator which generate | occur | produces a radical with respect to an electron beam or light, can also be used. Further, although it is expressed here as photosensitive, it may be one that is not only light but also sensitive to an electron beam. Here, EB is used as the exposure light for the light shielding band pattern and the auxiliary pattern exposure 114. Light can also be used. When EB is used, it is effective to apply a water-soluble conductive film in order to avoid the problem of charge-up. Thereafter, development was performed as shown in FIG. 2F to manufacture a tri-tone halftone mask in which the auxiliary pattern 104 and the light shielding band 105 were formed with a resist. In FIG. 1A, a mask alignment mark (reticle alignment mark) for the stepper is formed with an opening in the halftone film. However, in some combinations of stepper and halftone material, the transmissivity of the halftone material may be too high for the mark detection wavelength of the stepper, and the mark may not be detected accurately. In this case, as shown in FIG. 11, this problem is solved by forming the reticle alignment mark 141 using a resist that absorbs the mark detection light. FIG. 11 is a view showing a cross-sectional structure of the reticle alignment mark portion. In this case, when the opening of the halftone film 101 is retracted from the opening of the resist pattern by more than the maximum misalignment at the time of writing, there is no interference with the opening of the halftone film, and the alignment accuracy is improved.

FIG. 3 shows a manufacturing process of a conventional Tri-tone halftone mask in which an auxiliary pattern and a light shielding band are made of Cr. As shown in FIG. 3A, a halftone film 101, a Cr film 130, and a resist are sequentially formed on a glass substrate 100, and exposure (EB) 132 for forming an auxiliary pattern and a light shielding band is performed. Development is performed to form a resist pattern 133 as shown in FIG. 3B, and then etching is performed as shown in FIG. 3C to transfer the resist pattern to Cr. Thereafter, the resist is removed and cleaning is performed to form an auxiliary pattern 135 and a light shielding band pattern 134 made of Cr as shown in FIG. Thereafter, as shown in FIG. 3E, a resist 136 is applied, and circuit pattern exposure (EB) 137 is performed. Development is performed to form a resist pattern as shown in FIG. 3 (f), and etching is performed as shown in FIG. 3 (g) to transfer the circuit pattern to the halftone phase shift film 101. Thereafter, the resist is removed and cleaning is performed to manufacture a tri-tone halftone mask in which the auxiliary pattern 135 made of Cr and the light shielding band pattern 134 are formed. (Fig. 3 (h))
That is, in the above conventional method, since the auxiliary pattern is formed first, if the halftone phase shift film formed thereafter is defective, the auxiliary pattern forming process is a wasteful process. The reason why the conventional auxiliary pattern process had to be preceded is that if it was preceded, Cr etching of the halftone opening and halftone film processing were performed, and then the field portions other than the auxiliary pattern portion and the light shielding band portion. This is because the Cr etching is necessary, and a part of the halftone film and the glass substrate is etched at the time of the etching, and the phase and transmittance control accuracy and in-plane uniformity are lowered.

  By using the present invention that precedes a low-yield process and performs the next process only on non-defective products, the number of manufacturing processes can be reduced compared to the conventional method, mask cost can be reduced, mask supply TAT can be accelerated, and manufacturing yield can be improved. I was able to.

(Embodiment 2)
In the second embodiment, the procedure of the photomask manufacturing method of the present invention will be described in detail with reference to FIGS.

  FIG. 4 shows a manufacturing process flow of the embodiment of the present invention. First, halftone blanks in which a halftone phase shift film is formed on a transparent substrate are prepared (201), and a resist is applied on the blanks (202). A halftone pattern (circuit pattern) is drawn (203), developed (204), and then etched (205). The resist mask is peeled off and washed (206), and the pattern appearance and dimension inspection (207) are performed to complete the base mask. For those that fail this inspection, those that can be corrected are corrected, but those that cannot be corrected are prepared again for halftone blanks (201), and the base mask is completed according to the above-described steps. After that, a light-absorbing resist is applied (208), an auxiliary pattern or a light shielding band pattern (referred to as a patch pattern) is drawn (209), and development (210) is performed to form an auxiliary pattern or a light shielding band pattern made of resist. To do. A mask that has undergone appearance and dimension inspection (211) and passed the inspection becomes a completed mask (212). The mask that fails the inspection is subjected to resist stripping and cleaning (213), and is again manufactured from the light-absorbing resist coating (208). If there is a design error in the auxiliary pattern, or if it is necessary to change the design of the auxiliary pattern as a result of the transfer evaluation of the mask, the resist is removed and washed (213), and the light-absorbing resist coating (208) is re-created. . At this time, the patch pattern drawing (209) is a pattern whose design has been changed.

  A manufacturing process flow of a conventional Tri-tone halftone phase shift mask is shown in FIG. Halftone blanks with Cr are prepared (301), resist coating (302), patch pattern drawing (303), development (304), Cr etching (305), resist peeling, and cleaning (306) are performed, and then the mask appearance and A dimension inspection (307) is performed. Those that fail the inspection are corrected, those that can be corrected are corrected, and those that cannot be corrected are re-produced from the Cr halftone blank preparation (301) step. Those that have passed the inspection are resist coating (308), halftone pattern (circuit pattern) drawing (309), development (310), halftone film etching (311), resist stripping, cleaning (312), and appearance. And dimensional inspection (313). If it passes the inspection, it is completed (314). On the other hand, those that have been rejected can be corrected, but those that cannot be corrected are reproduced from the beginning (from Cr-added halftone blank preparation (301)).

  When the yield of each process is high and the inspection passes 100%, the present invention has 11 processes and the conventional method has 13 processes. The process can be shortened by this method.

  When a dimensional accuracy of 10 nm is required, the dimensional yield of the circuit pattern is reduced to 10 to 30%. On the other hand, a patch pattern such as an auxiliary pattern or a light shielding band pattern has little influence on the transfer size to the wafer, and thus does not require such high accuracy. For this reason, the patch pattern formation yield is 90% or more. Considering this yield, the present invention is probabilistic (on average) to complete one mask when the circuit pattern formation yield is 30% and the patch pattern production yield is 90%. It takes 27.8 steps. On the other hand, in the case of a conventional mask, 45.9 steps are required. Assuming that the circuit pattern formation yield is 10% and the patch pattern production yield is 90%, the present invention is 74.5 steps, and the conventional method is 137.8 steps. In this way, a substantial difference in the number of processes occurs. For this reason, the mask cost is greatly reduced, and the mask supply TAT becomes very short.

  FIG. 15 shows the relationship between the number of process steps between the present invention and the conventional method with respect to circuit pattern formation yield, using the production yield of patch patterns (auxiliary patterns) as a parameter. When the circuit pattern formation yield is 40% or less, the difference in the number of processes rapidly increases, and the effect of the present invention increases rapidly.

  Furthermore, in the present invention, after the circuit pattern matrix mask is formed, the patch pattern can be recreated in the form of reuse of the matrix mask. The time required for changing the patch pattern can be greatly reduced. For example, in the present invention, when the circuit pattern formation yield is 30% and the patch pattern manufacturing yield is 90%, the conventional method requires 74.4 steps, but the present method requires only 6.1 steps. The amount of masks to be discarded is reduced, which is also effective in terms of environmental protection. Improvement of the mask supply TAT is particularly useful for shortening the period of LSI development and product development.

(Embodiment 3)
6A and 6B are structural views of a photomask showing the third embodiment, in which FIG. 6A is a top view, and FIG. 6B is a line connecting A and A ′ in FIG. It is sectional drawing when cut. Reference numeral 140 denotes a metal outer frame, and a reticle mark 141 for mask (reticle) alignment is formed on the outer frame. The outer frame also incorporates the function of a shading band. Here, Cr is used as the metal. 130 is a main circuit pattern, 100 is a glass substrate, and 101 is a halftone film. The auxiliary pattern 140 is made of a resist as in the first embodiment. When a normal halftone mask is manufactured and the transfer characteristics of the mask are examined, this mask is particularly effective in terms of supply TAT and cost when a sub peak is transferred. This is because a tri-tone mask with an auxiliary pattern can be manufactured by applying a resist on the matrix mask, drawing and developing the matrix mask. In addition, it is necessary to use the resist which has a light absorbency with respect to wafer exposure light as a resist. Alternatively, if the auxiliary pattern is a fine pattern smaller than the dimension that can be transferred, a film transparent to the wafer exposure light may be used if the resist film thickness is set to a film thickness that reverses the phase of the wafer exposure light.

  In ArF lithography, resist sub-peak transfer prevention performance is insufficient, so even if the transmittance of the halftone film is as low as 4%, sometimes the sub-peak is transferred, and the auxiliary pattern is It may be necessary additionally. For this reason, this method is particularly useful for small corrections, for example, when switching from KrF lithography to ArF lithography or performing pattern shrinking based on a mask that has been proven in KrF lithography to create a mask for ArF lithography.

(Embodiment 4)
7A and 7B are structural views of a photomask showing a fourth embodiment. FIG. 7A is a top view, and FIG. 7B is a line connecting A and A ′ in FIG. It is sectional drawing when cut. Reference numeral 140 denotes a metal outer frame, and a reticle mark 141 for mask (reticle) alignment is formed on the outer frame. The outer frame also incorporates the function of a shading band. 130 is a main circuit pattern, 100 is a glass substrate, and 101 is a halftone film. The auxiliary pattern is composed of 142 made of the same metal as the outer frame and 140 made of resist. This is particularly effective in terms of supply TAT and cost, when a normal Tri-tone halftone mask having a metal auxiliary pattern is manufactured and the transfer characteristics of the mask are examined and the sub-peak is transferred. . This is because it is possible to easily manufacture a mask in which the auxiliary pattern is corrected by applying a resist on the base mask, drawing and developing it. In addition, it is necessary to use the resist which has a light absorbency with respect to wafer exposure light as a resist. Alternatively, if the auxiliary pattern is a fine pattern smaller than the dimension that can be transferred, a film transparent to the wafer exposure light may be used if the resist film thickness is set to a film thickness that reverses the phase of the wafer exposure light.

(Embodiment 5)
An example of the auxiliary pattern arrangement will be described below with reference to layout diagrams 8 to 10 in which the pattern is observed from the upper surface. 8 and 9 are examples of wiring pattern layouts. In the figure, 101 is a halftone film, 103 is a circuit pattern (opening pattern), and 104 is a resist auxiliary pattern. The auxiliary pattern is arranged at a sub-peak generation location predicted by optical image simulation. This is where the light from the surrounding aperture pattern is collected by interference. As for typical dimensions, the minimum line width of the main body circuit pattern is (0.45 × λ) / NA or less, and the auxiliary pattern dimension is also equal to or smaller than that size, typically 1/3 to 3/4 of the minimum main body dimension. The present invention is particularly effective. As the size of the auxiliary pattern increases, sub-peaks are less likely to occur, but the halftone effect, that is, the resolution improvement effect decreases. In particular, when the minimum line width of the main circuit pattern is (0.4 × λ) / NA or less, the effect of the halftone mask using the auxiliary pattern is increased. NA is the numerical aperture of the projection lens of the stepper or scanner, and λ is the exposure wavelength of the stepper or scanner.

  FIG. 10 shows an example of a hole pattern. In FIG. 10A, the sub-peak is generated at the place where the auxiliary pattern 104 is placed, which is called the four-point, and where the diffracted light from the surrounding opening 103 gathers with the same phase. An auxiliary pattern is arranged here. In FIG. 10B, the auxiliary patterns are arranged in a bar shape, and are arranged in a place including the above-described four points. The arrangement in the case of FIG. 10A has a wide halftone area, and the effect of improving the resolution of holes is great. On the other hand, the bar-shaped arrangement of FIG. 10B has a feature that the size of the auxiliary pattern is large and the drawing burden is small.

(Embodiment 6)
The sixth embodiment relates to the manufacture of a semiconductor integrated circuit device having a twin well type CMIS (Complementary MIS) circuit. The manufacturing process will be described with reference to FIG.

  FIG. 12 is a fragmentary cross-sectional view of the semiconductor wafer during the manufacturing process. The semiconductor substrate 3 s constituting the semiconductor wafer is made of, for example, a Si single crystal whose n-type plane is circular. In the upper part, for example, an n well 6n and a p well 6p are formed. For example, an n-type impurity such as phosphorus or As is introduced into the n-well 6n. Further, p-type impurities such as boron are introduced into the p-well 6p. The n well and p well are formed as follows. First, a wafer alignment mark for mask alignment is formed on the semiconductor substrate 3s (not shown). This wafer alignment mark can be formed at the time of well formation by adding a selective oxidation step. Thereafter, as shown in FIG. 12A, an oxide film 17 is formed on the semiconductor substrate 3s, and a resist pattern 18 for an implantation mask is subsequently formed on the oxide film 17 by i-line lithography. The mask is a normal Cr mask. Then phosphorus was implanted. Since the minimum dimension is as large as 2.4 μm and high dimensional accuracy is not required, low cost i-line lithography was used.

  After that, ashing is performed to remove the resist 18 and the oxide film 17 is removed. Then, as shown in FIG. 12B, an oxide film 19 is formed on the semiconductor substrate 3s, and the resist pattern 20 for the implantation mask is subsequently formed as i. It is formed on the oxide film 19 by line lithography. The mask is a normal Cr mask. Then phosphorus was implanted.

  Thereafter, the resist 20 and the oxide film 19 are removed, and a separation field insulating film 7 made of, for example, a silicon oxide film is formed in the form of groove type isolation on the main surface (first main surface) of the semiconductor substrate 3s. (FIG. 12 (c)). FIG. 16 shows an isolation layout pattern. In the figure, reference numeral 50 denotes an active area pattern.

Note that a LOCOS (Local Oxidation of Silicon) method may be used as an isolation method. However, the LOCOS method has a problem that the layout dimension becomes large due to the reason that the bird's beak is extended. For the lithography during the production of the isolation, an ArF excimer laser reduced projection exposure apparatus and the halftone phase shift mask with a resist auxiliary pattern described in the first embodiment were used. This is because the minimum dimension required for the mask was as small as 520 nm (130 nm on the wafer) and the dimensional accuracy was as strict as 13 nm. The exposure at this time was performed as shown in FIG. That is, the photomask shown in Embodiment 1 is set on the mask stage 152 with the main surface on which the pattern is disposed facing downward, and exposure light (in this case, ArF excimer laser light) 151 is irradiated from the upper surface, and the projection lens Pattern exposure was performed on the wafer 155 placed on the wafer stage 156 via the line 153. In the figure, reference numeral 154 denotes a condensing state of exposure light, and the projection lens 153 is a reduction projection optical system. Here, the reduction ratio is 4x. However, the reduction ratio is not limited, and may be 5x, 2.5x, 10x, for example. The auxiliary pattern 104 and the light-shielding band pattern 105 are made of resist. However, the reduced light is irradiated with the reduced light through the halftone film 101 and the wafer is exposed through the reduction projection system. Since the illuminance on the mask is lower than that on the wafer, the light irradiation damage to the resist is small. Here, since the transmittance of the halftone film is 6%, the illuminance received by the resist auxiliary pattern and the resist light-shielding band pattern compared to the resist on the wafer is (1/4) × (1/4) × 0.06 × ( 1 / 0.6) = 0. Here, 0.6 is the transmittance of the projection lens 153.
In the active region surrounded by the field insulating film 7, nMIS Qn and pMIS Qp are formed. The gate insulating film 8 of nMIS Qn and pMIS Qp is made of, for example, a silicon oxide film and is formed by a thermal oxidation method or the like. The gate electrode 9 of the nMIS Qn and the pMIS Qp is described in the ArF excimer laser reduced projection exposure apparatus and the first embodiment after a gate forming film made of, for example, low resistance polysilicon is deposited by the CVD method or the like. Lithography is performed using a halftone phase shift mask using the resist auxiliary pattern, and then etching is performed. The gate electrode 9 can also be subjected to lithography using a KrF excimer laser reduced projection exposure apparatus and a halftone phase shift mask using the resist auxiliary pattern described in the first embodiment. A layout pattern of the gate electrode is shown in FIG. In the figure, 51 is a gate wiring pattern.

  However, since the exposure wavelength is shorter, the use of the ArF excimer laser resolves fine patterns with exposure latitude. Since the gate is required to have particularly high dimensional accuracy, the mask manufacturing yield is small and this mask is particularly effective. The required accuracy of the gate circuit pattern is 9 nm on the mask. Therefore, a mask that satisfies the required accuracy can be manufactured by the fifth circuit pattern formation. For this reason, the number of mask manufacturing steps was 35. When this was made with a normal Tri-tone halftone mask, the number of steps was 65, and the cost was reduced and the mask supply TAT was improved.

  The semiconductor region 10 of nMIS Qn is formed in a self-aligned manner with respect to the gate electrode 9 by introducing, for example, phosphorus or arsenic into the semiconductor substrate 3s using the gate electrode 9 as a mask by an ion implantation method or the like. The semiconductor region 11 of the pMIS Qp is formed in a self-aligned manner with respect to the gate electrode 9 by introducing, for example, boron into the semiconductor substrate 3s by an ion implantation method or the like using the gate electrode 9 as a mask. However, the gate electrode 9 is not limited to being formed of, for example, a single film of low resistance polysilicon, and can be variously modified. For example, tungsten silicide, cobalt silicide, or the like is formed on the low resistance polysilicon film. A so-called polycide structure may be formed by providing a silicide layer, or a metal antinode such as tungsten may be provided on a low resistance polysilicon film via a barrier conductor film such as titanium nitride or tungsten nitride. A so-called polymetal structure may be used.

First, as shown in FIG. 12D, an interlayer insulating film 12 made of, for example, a silicon oxide film is deposited on such a semiconductor substrate 3s by a CVD method or the like, and then a polysilicon film is formed on the upper surface thereof by a CVD method or the like. Deposited by. Subsequently, lithography is performed on the polysilicon film, etching is patterned, and then impurities are introduced into a predetermined region of the patterned polysilicon film, thereby forming a wiring 13L and a resistor 13R made of the polysilicon film. To do.
Thereafter, as shown in FIG. 12E, a silicon oxide film 14, for example, is deposited on the semiconductor substrate 3s by a CVD method or the like, and then the semiconductor regions 10, 11 and the wiring 13L are formed on the interlayer insulating film 12 and the silicon oxide film 14. The connection hole 15 in which a part of the contact hole 15 is exposed is formed by lithography using the ArF excimer laser reduced projection exposure apparatus and the halftone mask provided with the resist auxiliary pattern described in the first embodiment, and then etched and drilled. Here, the layout pattern of the connection holes is shown in FIG. 52 in the figure is a connection hole pattern.

  Here, since the hole diameter of the connection hole was 0.13 μm, ArF excimer laser exposure was used. However, if the hole diameter is larger than 0.16 μm, KrF excimer laser exposure may be used. KrF excimer laser exposure is less expensive than ArF lithography due to the cost of the apparatus.

  Further, after sequentially depositing a metal film made of titanium (Ti), titanium nitride (TiN) and tungsten (W) on the semiconductor substrate 3s by the sputtering method and the CVD method, the metal film is deposited on an ArF excimer laser reduced projection exposure apparatus. Then, lithography is performed using the halftone mask provided with the resist auxiliary pattern described in the first embodiment, and etching is performed, thereby forming the first layer wiring 16L1 as shown in FIG. Thereafter, the second layer wiring and subsequent layers are formed in the same manner as the first layer wiring 16L1, and the semiconductor integrated circuit device is manufactured. Here, since the wiring pitch was 0.24 μm, ArF excimer laser exposure was used. However, when forming a wiring pitch pattern looser than 0.36 μm, KrF excimer laser exposure is used from the viewpoint of cost. Here, a layout example of the wiring pattern is shown in FIG. 53 in the figure is a wiring pattern.

  In custom LSI products, mask debugging is often performed especially with the first wiring layer as the center. Since the speed of the mask supply TAT to the first wiring layer determines the product development capability and the required number of masks increases, it is particularly effective to apply the mask of the present invention having a short mask supply TAT to this step.

  In the above description, the case where the present invention is applied to CMIS has been described. However, the present invention is not limited thereto. For example, SRAM (Static Random Access Memory) or flash memory (EEPROM; Electric Erasable Read Only Electric Memory) or the like. The present invention can also be applied to a semiconductor integrated circuit device having a memory circuit, a mixed type semiconductor integrated circuit device in which the memory circuit and the logic circuit are provided on the same semiconductor substrate, a wiring board device, a magnetic recording device, and other electronic devices.

It is a structural view showing the structure of a photomask used in the present invention. (A) is a top view, (b) is sectional drawing. (A)-(f) is process drawing which showed the preparation methods of the mask of this invention with sectional drawing. (A)-(h) is process drawing which showed the preparation methods of the conventional mask with sectional drawing. It is process drawing which showed the manufacturing method of the mask of this invention with the flowchart. It is process drawing which showed the manufacturing method of the conventional mask with the flowchart. It is a structural view showing the structure of a photomask used in the present invention. (A) is a top view, (b) is sectional drawing. It is a structural view showing the structure of a photomask used in the present invention. (A) is a top view, (b) is sectional drawing. FIG. 5 is a pattern layout diagram showing an example of the arrangement of auxiliary patterns according to the present invention in a top view. FIG. 5 is a pattern layout diagram showing an example of the arrangement of auxiliary patterns according to the present invention in a top view. FIG. 5 is a pattern layout diagram showing an example of the arrangement of auxiliary patterns according to the present invention in a top view. FIG. 3 is a structural diagram showing a cross-sectional structure of a main part of a photomask used in the present invention. (A)-(f) is manufacturing process drawing of the semiconductor integrated circuit device shown with the principal part sectional drawing. It is explanatory drawing which shows a structure when performing exposure using this invention. It is explanatory drawing explaining the phenomenon of a subject. It is a characteristic view which shows the effect of this invention. It is the layout figure which showed the example of arrangement | positioning of the isolation pattern. It is the layout figure which showed the example of arrangement | positioning of a gate electrode pattern. It is the layout figure which showed the example of arrangement | positioning of a connection hole pattern. It is a layout diagram showing an example of the arrangement of wiring patterns. It is the layout figure which showed the example of arrangement | positioning of a quadrupole pattern.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 3 ... Semiconductor wafer, 3s ... Semiconductor substrate, 6n ... n well, 6p ... p well, 7 ... Field insulating film, 8, 9 ... Gate insulating film, 10 ... Semiconductor region of nMISQn, 11 ... Semiconductor region of pMISQp, 12 ... Interlayer insulation film, 13L ... wiring, 13R ... resistance, 14 ... TEOS film, 15 ... connection hole, 16L1 ... first layer wiring, 50 ... isolation pattern, 51 ... gate wiring pattern, 52 ... connection hole pattern, 53 ... wiring Pattern: 100 ... Quartz glass (blanks), 101 ... Halftone film, 103 ... Circuit pattern (main body pattern), 104 ... Auxiliary pattern (resist pattern), 105 ... Resist shading band, 106 ... Drawing alignment mark, 110 ... Resist 111 ... EB, 112 ... circuit pattern, 113 ... resist, 114 ... EB, 115 ... regis , 130 ... Cr, 131 ... resist, 132 ... EB, 133 ... resist pattern, 134 ... Cr light shielding band, 135 ... Cr auxiliary pattern, 136 ... resist, 137 ... EB, 138 ... circuit pattern, 140 ... Cr outer frame, 141 ... reticle alignment mark, 142 ... Cr auxiliary pattern, 151 ... exposure light, 152 ... mask stage, 153 ... projection lens, 155 ... wafer, 156 ... wafer stage.

Claims (3)

In a manufacturing method of an electronic device using a phase shift mask using a phase shift film translucent to exposure light,
Preparing a phase shift mask matrix on which an opening pattern for forming a circuit pattern is formed on the phase shift film;
Forming a first auxiliary pattern made of an organic film having a light attenuation property or a light shielding property on exposure light on the phase shift film in the vicinity of the opening pattern of the phase shift mask base;
Setting the phase shift mask in a direction in which exposure light is directed to the first auxiliary pattern through the phase shift film, and performing pattern exposure to transfer the pattern onto the first substrate;
Peeling the first auxiliary pattern;
Forming a second auxiliary pattern made of an organic film having a light-reducing property or a light-shielding property on exposure light on a phase shift film in the vicinity of the opening pattern of the phase shift mask base;
Setting the phase shift mask in a direction in which exposure light is directed toward the second auxiliary pattern via the phase shift film, and performing pattern exposure to transfer the pattern onto the second substrate;
A method for manufacturing an electronic device, comprising: In a manufacturing method of an electronic device using a phase shift mask using a phase shift film translucent to exposure light,
Preparing a phase shift mask matrix on which an opening pattern for forming a circuit pattern is formed on the phase shift film;
Forming a first auxiliary pattern made of an organic film having a light attenuation property or a light shielding property on exposure light on the phase shift film in the vicinity of the opening pattern of the phase shift mask base;
Setting the phase shift mask in a direction in which exposure light is directed to the first auxiliary pattern through the phase shift film, and performing pattern exposure to transfer the pattern onto the first substrate;
Inspecting the presence or absence of unnecessary pattern transfer due to sub-peaks of the transferred image on the first substrate;
When the unnecessary pattern is found, peeling the first auxiliary pattern;
On the phase shift film in the vicinity of the opening pattern of the phase shift mask matrix, from an organic film having a light-reducing property or a light-shielding property with respect to the exposure light modified based on the size and position information of the unnecessary pattern Forming a second auxiliary pattern comprising:
Setting the phase shift mask in a direction in which exposure light is directed toward the second auxiliary pattern via the phase shift film, and performing pattern exposure to transfer the pattern onto the second substrate;
A method for manufacturing an electronic device, comprising: In a manufacturing method of an electronic device using a phase shift mask using a phase shift film translucent to exposure light,
Preparing a phase shift mask matrix on which an opening pattern for forming a circuit pattern is formed on the phase shift film;
Forming a first auxiliary pattern made of a metal film or an organic film having a light attenuation property or a light shielding property on exposure light on the phase shift film in the vicinity of the opening pattern of the phase shift mask base;
Setting the phase shift mask in a direction in which exposure light is directed to the first auxiliary pattern through the phase shift film, and performing pattern exposure to transfer the pattern onto the first substrate;
Inspecting the presence or absence of unnecessary pattern transfer due to sub-peaks of the transferred image on the first substrate;
When the unnecessary pattern is found, the exposure light is dimmed on the phase shift film in the vicinity of the opening pattern of the phase shift mask base based on the size and position information of the unnecessary pattern. A step of additionally forming a second auxiliary pattern made of an organic film having a property or a light shielding property;
Setting the phase shift mask in a direction in which exposure light is directed toward the second auxiliary pattern via the phase shift film, and performing pattern exposure to transfer the pattern onto the second substrate;
A method for manufacturing an electronic device, comprising:

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