JP2007181288A - Power supply circuit and electronic device using the same - Google Patents

Abstract

【Task】
To provide a power supply circuit that does not require a separate resistor in the middle of a charging circuit and can perform soft start without changing the comparison operation between soft start and normal even during feedback control.
[Solution]
The power supply circuit is a charge in which the first switching transistors 16 and 22, the capacitors C1 and C2, and the second switching transistors 18 and 24 are connected in series in this order between the first power supply line 12 and the second power supply line 14. Circuits 10 and 20 are included. Based on the soft start signal SSS, the soft start voltage supply circuits 60, 70, and 80 supply the normal on-potential based on the clock signals CL1 and CL2 to one gate of the first and second switching transistors. Also, a soft start voltage SSD for increasing the on-resistance value of one of the first and second switching transistors is supplied to one gate of the first and second switching transistors.
[Selection] Figure 3

Description

  The present invention relates to a power supply circuit capable of realizing a low inrush current when power is turned on and an electronic apparatus using the power supply circuit.

  For example, in a liquid crystal display device or the like, a DC / DC converter that increases or decreases a power supply voltage is used to generate a plurality of types of drive voltages. This DC / DC converter has a charging circuit in which a first switching transistor, a capacitor, and a second switching transistor are connected in series in this order between a VDD line and a VSS line.

  However, immediately after the power is turned on, an inrush current flows through the first and second switching transistors having low on-resistance until the initial charge is charged in the capacitor. For example, even if a current consumption of 100 mA is assumed in a steady state, if an inrush current of about 1 A flows, for example, the IC latches up, the power load increases, the voltage drops, and the system power supply voltage is reduced. A detrimental effect will occur.

  Therefore, conventionally, another transistor having a high on-resistance value (low capacity) is added in the middle of the above-described charging circuit to prevent inrush current.

In DC / DC converters that control the output voltage by feedback, the reference voltage compared with the output voltage is gradually increased by a comparator such as an error amplifier, or the output voltage is supplied to the comparator at startup. Soft start was performed in which the output voltage gradually increased without being input (Patent Document 1).
JP 2003-299348 A

  The object of the present invention is not to require a resistor having a large resistance value in the middle of the charging circuit, and even if the comparison between the output voltage and the reference voltage is fed back, the comparison operation is performed at the soft start time and the normal time. It is an object of the present invention to provide a power supply circuit capable of performing a soft start without change and an electronic device using the power supply circuit.

  A power supply circuit according to one embodiment of the present invention includes a first switching transistor, a capacitor, and a second switch between a first power supply line and a second power supply line having a lower potential than the power supply potential of the first power supply line. It has a charging circuit in which switching transistors are connected in series in that order. Each of the first and second switch transistors is simultaneously turned on / off based on a clock signal. Based on a soft start signal that is active during a soft start period for a predetermined time from when the power is turned on, one of the gates of the first and second switching transistors is turned on at the normal time based on the clock signal. A soft start voltage for increasing the ON resistance value of one of the first and second switching transistors to one gate of the first and second switching transistors than when supplying a potential. A start voltage supply circuit was provided.

  Immediately after the power is turned on, the on-resistance value of the switching transistor is increased by applying a soft start voltage to one gate of the first and second switching transistors. For this reason, even when the initial charge is not charged in the capacitor, the inrush current is blocked by the high on-resistance value. In addition, since there is no high resistance value at the steady time (normal time) when the power supply voltage is stable, there is no problem in the steady charging operation. In the present invention, the inrush current can be reduced without necessarily feeding back the output voltage.

  In one aspect of the present invention, the soft start voltage supply circuit has a potential increase rate higher than a potential increase rate at the time of power-on of the reference potential of the clock signal supplied to one of the first and second switching transistors. The soft start voltage having a low value can be supplied. With such a soft start voltage, the on-resistance value of one of the first and second switching transistors can be increased during the soft start period.

  In one embodiment of the present invention, an inverter connected to one gate of the first and second switching transistors and driven by the clock signal can be further included. The inverter may include a P-type transistor and an N-type transistor connected in series between the first power line and the second power line. The soft start voltage supply circuit turns off the P-type transistor within the soft start period, and supplies the soft start voltage according to the logic of the clock signal instead of the power supply potential from the first power supply line. The P-type transistor is turned on / off. The soft start voltage supply circuit turns the P-type transistor on and off according to the logic of the clock signal outside the soft start period. As a result, the inrush current can be reduced by the soft start voltage during the soft start period, and one of the first and second switching transistors can be turned on and off. The first and second switching transistors can be turned on and off based on the power supply potential outside the soft start. One of the two switching transistors can be turned on / off.

  In one aspect of the present invention, the soft start voltage supply circuit includes the clock signal over the soft start period based on the voltage source of the soft start voltage and the logic of the clock signal and the soft start signal. The P-type transistor of the inverter is driven over the soft start period based on the logic of the first logic gate that enables the voltage source in an output enable state according to the logic of the clock signal and the soft start signal. And a second logic gate that turns off and on the P-type transistor in accordance with the logic of the clock signal outside the soft start period.

  In this way, in the soft start period, a soft start voltage can be supplied to one of the first and second switching transistors according to the logic of the first clock signal by the first logic gate, and at that time, the P type can be supplied by the second logic gate. Supply of the power supply potential via the transistor can be blocked. Outside the soft start period, the inverter can be driven based on the power supply potential as usual by the first and second logic gates.

  In one embodiment of the present invention, one drive potential of the first and second switching transistors is the same as the power supply potential, and the other drive potential of the first and second switching transistors is higher than the power supply potential. It should be set high. This is because the boosted voltage is applied to the other of the first and second switching transistors. In this case, the size can be reduced by connecting a soft start voltage supply circuit to one of the first and second switching transistors.

  A power supply circuit according to another aspect of the present invention includes a first P-type switching transistor, a first power supply line between a first power supply line and a second power supply line having a lower potential than the power supply potential of the first power supply line. A first charging circuit in which a capacitor and an N-type switching transistor are connected in series in that order; and a second P-type switching transistor, the first capacitor, a second capacitor between the first power supply line and the second power supply line And a second charging circuit in which a P-type switching transistor and a second capacitor are connected in series in that order, and a voltage charged in the second capacitor is used as an output voltage, and the N-type and second P-type switches Each of the transistors is complementarily turned on and off based on a first clock signal having the same phase, and each of the first and third P-type switching transistors is based on a second clock signal having a different phase. The first and second P-type switching transistors are complementarily turned on / off, and are complementarily turned on / off, and are activated based on a soft start signal that is active in a soft start period for a predetermined time from power-on. Thus, at least one on-resistance value of the N-type and second P-type switching transistors is higher than when a potential based on the clock signal is supplied to at least one gate of the N-type and second P-type switching transistors. At least one soft start voltage supply circuit for supplying a soft start voltage for increasing the voltage to at least one gate of the N-type and second P-type switching transistors.

  Immediately after the power is turned on, a soft start voltage is applied to at least one of the gates of the N-type and second P-type switching transistors to increase the on-resistance value of the switching transistors. For this reason, even when the initial charge is not charged in the capacitor, the inrush current is blocked by the high on-resistance value. In addition, since there is no high resistance value at steady state when the power supply voltage is stable, there is no problem in charging operation at steady state. In the present invention, the inrush current can be reduced without necessarily feeding back the output voltage.

  Here, in another aspect of the present invention, unlike the one aspect of the present invention, provision of a soft start voltage supply circuit to the first and third P-type switching transistors is not defined. This is because the gate cannot be accurately controlled unless the output voltage is determined in the first and third P-type switching transistors. On the other hand, in the N-type and second P-type switching transistors, the source-side voltage is constant as the potentials of the first and second power supply lines, so that the gate is easy to control and the low inrush current is surely achieved. realizable.

  Note that in one aspect of the present invention, the first and third P-type switching transistors in the other aspects of the present invention are defined as one or the other of the first and second switching transistors in the charging circuit. Depending on the setting of the start voltage, it is possible to gate the first and third P-type switching transistors.

  In another aspect of the present invention, the at least one soft start voltage supply circuit supplies the soft start voltage whose potential rise rate is lower than the potential rise rate when the reference potential of the first clock signal is turned on. be able to.

  In another aspect of the present invention, the semiconductor device further includes an inverter connected to at least one gate of the N-type and second P-type three switching transistors and driven by the first clock signal, and the inverter is a P-type transistor. And N-type transistors. The at least one soft start voltage supply circuit turns off the P-type transistor within the soft start period, and replaces the power supply potential from the first power supply line according to the logic of the first clock signal. A soft start voltage is supplied to turn on and off the P-type transistor, and outside the soft start period, the P-type transistor is turned on and off according to the logic of the first clock signal.

  In another aspect of the present invention, the at least one soft start voltage supply circuit is configured to perform the soft start period based on a logic of the voltage source of the soft start voltage, the clock signal, and the soft start signal. The first logic gate that enables the voltage source to be output enabled according to the logic of the first clock signal, and the logic of the clock signal and the soft start signal, over the soft start period, And a second logic gate that turns off the P-type transistor of the inverter and turns the P-type transistor on and off according to the logic of the first clock signal outside the soft start period.

  In another aspect of the present invention, the drive potentials of the N-type and second P-type switching transistors are the same as the power supply potential, and the drive potentials of the first and third P-type switching transistors are set higher than the power supply potential. Can be set higher. In this case, the at least one soft star voltage supply circuit supplies the soft start voltage only to the gate of the N-type switching transistor. In this way, the soft start voltage supply circuit can be reduced in size.

  Instead, two soft start voltage supply circuits are prepared, one of which supplies the soft start voltage to the gate of the N-type switching transistor, and the other supplies the soft start voltage to the second P It may be supplied to the gate of the type switching transistor.

  In one embodiment and another embodiment of the present invention, a power-on reset signal can be used as the soft start signal.

  Alternatively, an output monitoring circuit that compares the output voltage with a reference voltage may be provided. In this case, the soft start signal is output from the output monitoring circuit, and the soft start signal is activated when the output voltage is lower than the reference voltage in the output monitoring circuit.

  In still another embodiment of the present invention, an electronic device having a power supply circuit according to one embodiment or another embodiment of the present invention, for example, a flat display such as a liquid crystal display device, or a portable device equipped with the same is defined.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a basic circuit diagram of a power supply circuit having no soft start voltage supply circuit, and FIG. 2 is an operation timing chart thereof. FIG. 3 is a circuit diagram of a soft start voltage supply circuit added to the circuit of FIG. 1, and FIG. 6 is an operation timing chart thereof.

1. 1. Basic Configuration and Basic Operation of Power Supply Circuit In FIG. 1, this power supply circuit is provided in a semiconductor device such as an IC that drives a display unit such as a liquid crystal display unit of an electronic device such as a mobile phone, and is charged with a power supply potential VDD. The first charging circuit 10 and the second charging circuit 20 charged with a potential twice the power supply potential VDD. This power supply circuit is a DC / DC converter that boosts the power supply potential VDD by a charge pump method.

  The first charging circuit (charging circuit in a broad sense) 10 includes a first P power line between a VDD power line (first power line in a broad sense) 12 and a VSS power line (second power line in a broad sense) 14. Type switching transistor (one of first and second switching transistors in a broad sense) 16, a first capacitor (also referred to as a capacitor) C1 and an N type switching transistor (the other of the first and second switching transistors in a broad sense) 18 Are connected in series in that order.

  The second charging circuit (charging circuit in a broad sense) 20 includes a second P-type switched transistor (one of the first and second switching transistors in a broad sense) between the VDD power supply line 12 and the VSS power supply line 14. ) 22, a first capacitor C1, a third P-type switching transistor (the other of the first and second switching transistors in a broad sense) 24, and a second capacitor C2 (a capacitor in a broad sense) in that order. Connected and configured.

  Here, when both the first P-type and N-type switching transistors 16 and 18 are turned on and both the second and third P-type switching transistors 22 and 24 are turned off, as shown in FIG. The capacitor C1 is charged with the power supply potential VDD. Next, when both the first P-type and N-type switching transistors 16 and 18 are turned off and both the second and third P-type switching transistors 22 and 24 are turned on, the one-end voltage of the first capacitor C1 is increased. Since the power supply potential becomes VDD, the potential at the other end is shifted to 2 × VDD. As a result, the 2 × VDD potential is charged in the second capacitor C2 as shown in FIG. In the present embodiment, this 2 × VDD potential is the output voltage. However, a circuit in the subsequent stage may be added to further increase or decrease the output voltage.

  Note that the N-type and second P-type switching transistors 18 and 22 are formed of LV (Low Voltage) transistors driven by the power supply potential VDD. On the other hand, the first and third P-type switching transistors 16 and 24 are formed of HV (High Voltage) transistors that are driven at a potential VPP higher than the power supply potential VDD.

  For this reason, the HV system supplied to the first and third P-type switching transistors 16 and 24 separately from the LV system first clock CL1 supplied to the N-type and second P-type switching transistors 18 and 22. The second clock signal CL2 is prepared. The first clock generation circuit 30 generates the first clock signal CL1 based on VDD (reference potential of the first clock signal) and VSS potential. On the other hand, the second clock generation circuit 32 generates the second clock signal CL2 based on VPP (VPP> VDD) and the VSS potential.

  FIG. 2 shows a boosting operation in a steady state that is not immediately after power-on (during startup). The first and second clock signals CL1 and CL2 have the same phase, but the potential to become HIGH is different from VDD and VPP.

  In order to perform the step-up operation, the first clock signal CL1 is supplied to the gate of the N-type switching transistor 18 by passing the inverter 40 through the first clock signal CL1. Similarly, the inverted first clock signal / CL1 is supplied to the gate of the second P-type switching transistor 22 by passing the first clock signal CL1 through the inverter 42. That is, as shown in FIG. 2, the N-type and second P-type switching transistors 18 and 22 are complementarily turned on and off by the inverted first clock signal / CL1 having the same phase.

  By passing the second clock signal CL2 through the inverter 50, the inverted second clock signal / CL2 is supplied to the gate of the third P-type switching transistor 24. The second clock signal CL2 is supplied to the gate of the first P-type switching transistor 16 by passing the second clock signal CL2 through the buffer 52. That is, as shown in FIG. 2, the first and third P-type switching transistors 16 and 24 are complementarily turned on and off by the second clock signals CL2 and / CL2 having opposite phases.

2. Soft Start Voltage Supply Circuit The soft start voltage supply circuit described below may be connected to any of the four switching transistors 16, 18, 22, and 24 shown in FIG. 1, but in the following example, the N type switching transistor 18 Only connected to.

  FIG. 3 is a circuit diagram of the soft start voltage supply circuit 60 connected to the gate of the N-type switching transistor 18. FIG. 3 shows the inverter 40 shown in FIG. 1 in addition to the N-type switching transistor 18 and the soft start voltage supply circuit 60. The inverter 40 includes a P-type transistor 40A and an N-type transistor 40B connected in series between the VDD power supply line 12 and the VSS power supply line 14, and the drains of the two transistors 40A and 40B are the N-type switching transistor 18. Connected to the gate.

  The soft start voltage supply circuit 60 includes a voltage source that supplies the first soft start voltage SSV to the gate of the N-type switching transistor 18 according to the logic of the first clock signal CL1, for example, a constant current charging circuit 62.

  Based on the logic of the first clock signal CL1 and the soft start signal SSS, the soft start voltage supply circuit 60 sets the constant current charging circuit 62 to the output enable state according to the logic of the first clock signal over the soft start period. 1 logic gate 64 is further provided.

  The soft start voltage supply circuit 60 turns off the P-type transistor 40A of the inverter 40 over the soft start period based on the logic of the first clock signal CL1 and the soft start signal SSS. There is a second logic gate 66 for turning on and off the P-type transistor 40B in accordance with the logic of the signal CL1.

  In the present embodiment, as the soft start signal SSS, a power-on reset signal that becomes active (for example, HIGH) for a predetermined period of time, for example, several tens of msec from when the power is turned on is used.

3. Operation of soft start voltage supply circuit 3.1. Operation within Soft Start Period FIG. 4 is a truth table of the first logic gate 64 that can be formed by an AND gate. In the soft start period (at startup) in which the soft start signal SSS is active (for example, HIGH). When the first clock signal CL1 is HIGH (the inverted first clock signal / CL1 is LOW), the output of the first logic gate 64 is active (HIGH). The active output of the first logic gate 64 enables the output state of the constant current charging circuit 62 (HIGH enable). Therefore, when the first clock signal CL1 is HIGH, the output of the constant current charging circuit 62 is supplied to the N-type switching transistor 18 to turn on the N-type switching transistor 18. When the first clock signal CL1 is LOW, the output of the first logic circuit 62 is inactive (LOW), and the constant current charging circuit 62 is in an output disabled state.

  FIG. 5 is a truth table of the second logic gate 66, and in the soft start period in which the soft start signal SSS is active (HIGH), the first logic gate 66 has the logic regardless of the logic of the first clock signal CL1. The output is HIGH. As a result, in the soft start period, the P-type transistor 42A is always turned off, and voltage supply from the P-type transistor 40A to the gate of the P-type switching transistor 18 is always blocked.

  Here, as shown in FIG. 3, the inverted signal / CL1 of the first clock signal CL1 is supplied to the gate of the N-type transistor 40B of the inverter 40. Therefore, even during the soft start period, when the first clock signal CL1 is LOW, the N-type switching transistor 18 is turned off. That is, when the first clock signal CL1 is LOW, the constant current charging circuit 62 is in the output disabled state as shown in FIG. 4, and the P-type transistor 40A of the inverter 40 is turned off as shown in FIG. However, when the N-type transistor 40B of the inverter 40 is turned on, the gate potential of the N-type switching transistor 18 becomes the ground potential.

  From the above, in the soft start period, if the first clock signal CL1 is HIGH, the N-type switching transistor 18 is turned on by the soft start voltage SSV from the constant current charging circuit 62, and the inverted signal of the first clock signal. The N-type transistor 40B to which / CL1 is supplied is turned on when the first clock signal CL1 is LOW. Thus, even during the soft start period, the N-type switching transistor 18 can be turned on / off by controlling the inverter 40 according to the logic of the first clock signal CL1 driven at a frequency of several MHz, for example.

  At this time, the soft start voltage SSV from the constant current charging circuit 62 is supplied to the gate of the N-type switching transistor 18 instead of the power supply voltage VDD passing through the P-type transistor 40A of the inverter 40.

  FIG. 6 schematically shows the soft start voltage SSD and the power supply voltage VDD after the power is turned on. The soft start voltage SSD is, for example, 3 V when charging is completed, and the potential rising speed is lower than the voltage rising speed after the power supply voltage VDD of, for example, 5 V is turned on. If the potential rise rate is slow, the potential level does not matter, such as the potential of the soft start voltage SSD is the same as the power supply potential.

  The on-resistance value of the N-type switching transistor 18 to which the soft start voltage SSV is applied during the soft start period is lower than when the power supply voltage VDD is applied. For this reason, immediately after the power is turned on, the inrush current flowing through the N-type switching transistor having a high on-resistance value can be reduced even during the period until the first capacitor CL1 is charged with the initial charge. Thereby, the inrush current in the first charging circuit 10 can be reduced.

  Thus, while realizing a low inrush current, the charging operation is repeated alternately in the first charging circuit 10 and the second charging circuit 20 in the same manner as the basic operation described above, as shown in FIG. The output voltage VOUT rises.

3.2. Operation Outside Soft Start Period As shown in FIG. 6, when the soft start signal SSS becomes LOW, the soft start period ends.
In the truth table of the first logic gate 64 shown in FIG. 4, in the “steady state” when the soft start signal SSS is inactive (LOW), regardless of the logic of the first clock signal CL1, the first logic The output of the gate 64 becomes inactive (LOW). Therefore, outside the soft start period, the constant current charging circuit 62 is in an output disabled state. Therefore, as indicated by a broken line in FIG. 6, the constant current charging circuit 62 may be discharged after the soft start signal SSS becomes inactive (LOW).

  In the truth table of the second logic gate 66 shown in FIG. 5, in the “steady state” when the soft start signal SSS is inactive (LOW), the logic of the first clock signal CL1 is output as the output of the second logic gate 66. Is inverted and output. Therefore, if the first clock signal CL1 is HIGH, the P-type transistor 40A of the inverter 40 is turned on, and the N-type switching transistor 18 to which the power supply voltage VDD is applied to the gate is turned on. Since the first clock signal CL1 is also supplied to the gate of the N-type transistor 40B of the inverter 40, if the first clock signal CL1 is LOW, the N-type transistor 40B of the inverter 40 is turned on and the ground voltage VSS is set. The N-type switching transistor 18 applied to the gate is turned off.

Thus, outside the soft start period, the charging operation is alternately repeated in the first charging circuit 10 and the second charging circuit 20 in the same manner as the basic operation described above, and as shown in FIG. The voltage VOUT is stabilized at 2 × VDD. At this time, since sufficient initial charge is charged in the first and second capacitors C1 and C, no inrush current flows.
4). Modified Example of Soft Start Signal SSS FIG. 7 shows a modified example in which the soft start signal SSS is generated without using the power-on reset signal. A soft start voltage generation circuit 70 shown in FIG. 7 includes an output voltage monitoring circuit 72 in addition to the constant current charging circuit 62 and the first and second logic gates 64 and 66 described above.

  The output voltage monitoring circuit 72 has a comparator 74 that compares the output voltage VOUT shown in FIG. 1 with a reference voltage. As shown in FIG. 6, the comparator 74 is active (eg, HIGH) when the output voltage VOUT rising immediately after power-on is equal to or lower than a predetermined voltage (output voltage at the end of the soft start period shown in FIG. 6). The soft start signal SSS is output. Even if it does in this way, it can be operated similarly to embodiment mentioned above. In addition, since the soft start period can be set by monitoring the actual output voltage VOUT, a more reliable operation for realizing a low inrush current can be guaranteed.

  In addition, this invention is not limited to embodiment mentioned above, A various deformation | transformation implementation is possible within the range of the summary of this invention.

  In the above-described embodiment, the inrush current is reduced by the first charging circuit 10. However, the present invention may be applied to the second charging circuit 20 in combination with this or alone. FIG. 8 shows a soft start voltage supply circuit 80 connected to the gate of the second P-type switching transistor 22. The soft start voltage supply circuit 80 has the same configuration as that shown in FIG. However, as its operation, when the first clock signal CL1 in the soft start period (SSS = HIGH) shown in FIG. 4 is LOW, the constant current charging circuit 62 is in the output enable state, and the second P-type switching transistor 22 Turned on. In the soft start period, the second P-type switching transistor 22 is turned off when the first clock signal CL1 is HIGH. When the first clock signal CL1 is LOW outside the soft start period (SSS = LOW) shown in FIG. 5, the second P-type switching transistor 22 is turned on. Outside the soft start period, the second P-type switching transistor 22 is turned off when the first clock signal CL1 is HIGH.

It is a basic circuit diagram showing an example of a power supply circuit to which the present invention is applied. 2 is a timing chart showing a basic operation of the power supply circuit shown in FIG. 1. It is a block diagram of the soft start voltage supply circuit added to the basic circuit of FIG. FIG. 4 is a schematic explanatory diagram showing an operation of the first logic gate shown in FIG. 3. It is a schematic explanatory drawing which shows the operation | movement of the 2nd logic gate shown in FIG. 4 is an operation explanation of the soft start voltage supply circuit shown in FIG. 3. It is a circuit diagram which shows the modification which produces | generates the soft start signal shown in FIG. 3 in an output monitoring circuit. It is a schematic explanatory drawing which shows the soft start voltage supply circuit connected to the gate of a 2nd P-type switching transistor.

Explanation of symbols

10 First charging circuit (charging circuit), 12 First power supply line (VDD), 14 Second power supply line (VSS), 16 First P-type switching transistor (first switching transistor), 18 N-type switching transistor ( Second switching transistor), 20 second charging circuit (charging circuit), 22 second P-type switching transistor (first switching transistor), 24 third P-type switching transistor (second switching transistor), 30 First clock generating circuit, 32 Second clock generating circuit, 40, 42 inverter, 40A, 42A P-type transistor, 40B, 42B N-type transistor, 50 inverter, 52 buffer, 60, 70, 80 Soft start voltage supply circuit, 62 Constant current charging circuit (voltage source), 64 first Logic gate, 66 second logic gate, 72 output voltage monitoring circuit, C1 first capacitor (capacitor), C2 second capacitor (capacitor), CL1 first clock signal, CL2 second clock signal, SSD soft start voltage, SSS Soft start signal

Claims (14)

A charging circuit in which a first switching transistor, a capacitor, and a second switching transistor are connected in series in this order between a first power supply line and a second power supply line having a potential lower than the power supply potential of the first power supply line Have
Each of the first and second switch transistors is simultaneously turned on / off based on a clock signal,
When a normal on-potential based on the clock signal is supplied to one gate of the first and second switching transistors based on a soft start signal that is active during a soft start period of a predetermined time from when the power is turned on. A soft start voltage supply circuit that supplies a soft start voltage for increasing the on-resistance value of one of the first and second switching transistors to one gate of the first and second switching transistors. A power supply circuit characterized by being provided. In claim 1,
The soft start voltage supply circuit supplies the soft start voltage having a potential increase rate lower than a potential increase rate at the time of power-on of a reference potential of the clock signal supplied to one of the first and second switching transistors. A power supply circuit characterized by being supplied. In claim 2,
An inverter connected to one gate of the first and second switching transistors and driven by the clock signal is further connected in series between the first power line and the second power line. Including P-type and N-type transistors,
The soft start voltage supply circuit turns off the P-type transistor within the soft start period, and supplies the soft start voltage according to the logic of the clock signal instead of the power supply potential from the first power supply line. Then, the P-type transistor is turned on / off, and the P-type transistor is turned on / off according to the logic of the clock signal outside the soft start period. In claim 3,
The soft start voltage supply circuit includes:
A voltage source of the soft start voltage;
A first logic gate that, based on the logic of the clock signal and the soft start signal, enables the voltage source in an output enable state according to the logic of the clock signal over the soft start period;
Based on the logic of the clock signal and the soft start signal, the P type transistor of the inverter is turned off during the soft start period, and outside the soft start period, the P type transistor is in accordance with the logic of the clock signal. A second logic gate for turning on and off;
A power supply circuit comprising: In any one of Claims 1 thru | or 4,
The drive potential of one of the first and second switching transistors is the same as the power supply potential, the other drive potential of the first and second switching transistors is set higher than the power supply potential, and the soft start A power supply circuit, wherein a voltage supply circuit is connected to one gate of each of the first and second switching transistors. A first P-type switching transistor, a first capacitor, and an N-type switching transistor are connected in series in this order between the first power supply line and the second power supply line having a lower potential than the power supply potential of the first power supply line. A first charging circuit,
Second charging in which a second P-type switching transistor, the first capacitor, a third P-type switching transistor, and a second capacitor are connected in series in that order between the first power supply line and the second power supply line. Circuit,
And the voltage charged in the second capacitor is an output voltage,
Each of the N-type and second P-type switch transistors is complementarily turned on / off based on a first clock signal having the same phase, and each of the first and third P-type switching transistors is different in phase. And the first and second P-type switching transistors are complementarily turned on / off based on two clock signals, and
From the time of supplying a potential based on the clock signal to at least one gate of the N-type and second P-type switching transistors based on a soft-start signal that is active during a soft-start period of a predetermined time from when the power is turned on. A soft start voltage for increasing at least one on-resistance value of the N-type and second P-type switching transistors is supplied to at least one gate of the N-type and second P-type switching transistors. A power supply circuit provided with one soft start voltage supply circuit. In claim 6,
The power supply circuit, wherein the at least one soft-start voltage supply circuit supplies the soft-start voltage having a lower potential rise speed than a potential rise speed when the reference potential of the first clock signal is turned on. Claim 6 Tama or 7
An inverter connected to at least one gate of the N-type and second P-type 3 switching transistors and driven by the first clock signal, the inverter including a P-type transistor and an N-type transistor;
The at least one soft start voltage supply circuit turns off the P-type transistor within the soft start period, and replaces the power supply potential from the first power supply line according to the logic of the first clock signal. A power supply circuit, wherein a soft start voltage is supplied to turn on and off the P-type transistor, and the P-type transistor is turned on and off according to the logic of the first clock signal outside the soft start period. In claim 8,
The at least one soft start voltage supply circuit includes:
A voltage source of the soft start voltage;
A first logic gate that enables the voltage source in an output enabled state according to the logic of the first clock signal over the soft start period based on the logic of the clock signal and the soft start signal;
Based on the logic of the clock signal and the soft start signal, the P-type transistor of the inverter is turned off over the soft start period, and outside the soft start period, the P type transistor according to the logic of the first clock signal. A second logic gate for turning on and off the type transistor;
A power supply circuit comprising: In any one of Claims 6 thru | or 9.
The drive potentials of the N-type and second P-type switching transistors are the same as the power supply potential, and the drive potentials of the first and third P-type switching transistors are set higher than the power supply potential.
The power supply circuit, wherein the at least one soft star voltage supply circuit supplies the soft start voltage only to a gate of the N-type switching transistor. In any one of Claims 6 thru | or 9.
One of the two soft start voltage supply circuits supplies the soft start voltage to the gate of the N-type switching transistor, and the other of the two soft start voltage supply circuits supplies the soft start voltage to the second P type. A power supply circuit that supplies power to a gate of a switching transistor. In any one of Claims 1 thru | or 11,
The power supply circuit, wherein the soft start signal is a power-on reset signal. In any of claims 6 to 11,
An output monitoring circuit that compares the output voltage with a reference voltage is further provided, and the soft start signal is output from the output monitoring circuit,
The power supply circuit, wherein the soft start signal is activated when the output voltage is lower than the reference voltage in the output monitoring circuit.   An electronic apparatus comprising the power supply circuit according to claim 1.

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