JP2007181000A - Timing extraction circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To extract a reproduction clock whose frequency and phase are accurately synchronized with input data.
A VCO1 and a frequency comparator 2 form a PLL loop, and a VCO1 oscillates a reproduction clock 7 at a frequency of a reference clock 5 having the same frequency as the data rate of input data 4, and a phase control terminal 1a of the VCO1. The input data 4 is input to the input signal 4 and the phase of the reproduction clock 7 is instantaneously adjusted in accordance with the timing of the input data 4.
[Selection] Figure 1

Description

  The present invention relates to a timing extraction circuit that extracts a reproduction clock having a phase and a frequency that match input data.

  The PON (Passive Optical Network) system, which is being developed as a technique for realizing FTTH (Fiber To The Home), needs to handle burst data. In these systems, a CDR (Clock Data Recovery) circuit that establishes phase synchronization instantaneously for burst data received asynchronously, extracts a recovered clock, and retimes data using the recovered clock is essential. This type of circuit can be referred to in Non-Patent Document 1, for example.

  FIG. 3 shows a configuration example of a timing extraction circuit used for such a purpose. Input data 4 is input to a phase control input terminal 11 a of a main VCO (voltage controlled oscillator) 11, and the main VCO 11 uses the timing of the input data 4, that is, a voltage value transition point as a trigger, and the oscillation phase of the input data 4 It is adjusted to match the phase. The phase-adjusted oscillation signal is taken out from the main VCO 11 as a reproduction clock 7 in phase with the input data 4 and input to the clock terminal 3b of the flip-flop (F / F) 3 and input to the data input terminal 3a. Retiming of input data 4 to be performed is performed. As a result, the reproduction data 6 is output from the output terminal 3 c of the flip-flop 3.

  On the other hand, the sub VCO 12 having the same circuit configuration as that of the main VCO 11 forms a PLL (Phase-Locked Loop) together with the frequency comparator 2, and has a frequency equal to the data rate of the input data 4 or a frequency that is an integer of the frequency. Oscillates at the same frequency as the reference clock 5. The control signal 8 output from the output terminal 2c of the frequency comparator 2 is simultaneously supplied to the frequency control terminal 11b of the main VCO 11 and the frequency control terminal 12b of the sub VCO 12, and the output terminal 12c of the sub VCO 12 and the output terminal 11c of the main VCO 11 are supplied. Is controlled so that the frequency of the reproduction clock 7 output from the same is the same.

With such a configuration, the main VCO 11 can continue oscillation of the reproduction clock 7 at the same frequency as the data rate of the input data 4 even when the input data 4 is not input, and the input data 4 is input. In this case, by adjusting only the phase, the reproduction clock 7 can be controlled in the same phase as the input data 4 in a very short time to establish synchronization.
Yusuke Ota, et al., “High-Speed, Burst Mode, Packet-Capable Optical Receiver and Instantaneous Clock Recovery for Optical Bus Operation”, Journal of Lightwave Technology, Vol. 12, No. 2, Feb. (1994)

  According to the configuration described above, since the data rate of the input data 4 and the frequency of the reproduction clock 7 output from the main VCO 11 always coincide with each other when operated ideally, when the input data 4 is input. The main VCO 11 only needs to match the phase, and synchronization with data can be established instantaneously.

  However, actually, even if the same control signal 8 is given due to various causes such as variations in elements constituting the timing extraction circuit, differences in current values, temperature non-uniformity, etc., an error in the oscillation frequency occurs between the main VCO 11 and the sub VCO 12. Occurs. Since the sub VCO 12 is oscillated by being locked to the reference clock 5 having the same frequency as the data rate by the PLL loop, if there is an error in the oscillation frequency of the main VCO 11 and the sub VCO 12, the frequency of the main VCO 11 and the input data 4 is increased. An error will occur. If there is an error in the frequency of the main VCO 11 and the input data 4, phase adjustment is not performed in the main VCO 11 while the same sign is continued in the input data 4. The phase of 7 gradually shifts. Then, the oscillation phase of the main VCO 11 is abruptly shifted so that the phases of the input data 4 and the recovered clock 7 are matched at the next data transition point. As a result of such repeated operation, the jitter of the recovered clock 7 becomes large.

  Further, when the oscillation frequency error between the VCOs 11 and 12 becomes large and the phase difference of the input data 4 within the maximum same sign continuous time becomes 360 degrees or more, the main VCO 11 cannot adjust the phase itself, and the reproduced data 6 A bit error will occur.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a timing extraction circuit capable of extracting a reproduction clock whose frequency and phase are accurately synchronized with input data.

In order to achieve the above object, an invention according to claim 1 includes an oscillation circuit having a frequency control input terminal, an output terminal for outputting a recovered clock, and a phase control input terminal for controlling the phase of the recovered clock; A frequency comparator is provided that inputs a reference clock and the recovered clock, compares the frequencies thereof, and inputs the result as a control signal to the frequency control input terminal of the oscillation circuit. Closed loop control is performed so that the frequency matches the frequency of the reference clock, and the oscillation circuit instantaneously adjusts the phase of the recovered clock in accordance with the timing of the input data by inputting the input data to the phase control input terminal. It is characterized by doing so.
The invention according to a second aspect is the invention according to the first aspect, wherein the frequencies of the recovered clock and the reference clock are respectively 1 / n times and 1 / m times (n and m are integers and n = m or n ≠ m). ), And a signal output from each frequency divider is input to the frequency comparator.
The invention according to claim 3 is the invention according to claim 1 or 2, wherein the input data is input to a data input terminal, the reproduction clock is input to a clock input terminal, a retiming operation is performed, and reproduction data is output. A flip-flop is provided.
The invention according to claim 4 is the invention according to claim 3, characterized in that the flip-flop is replaced with a FIFO.

  According to the present invention, since the phase adjustment with the input data and the frequency adjustment with the reference clock are performed by one VCO, the frequency of the recovered clock, which has been a problem in the conventional timing recovery circuit using two VCOs. Bit errors of reproduced data due to errors can be reduced.

[First embodiment]
FIG. 1 is a diagram showing a timing extraction circuit according to a first embodiment of the present invention. In FIG. 1, reference numeral 1 denotes a VCO, which has a phase control input terminal 1a, a frequency control input terminal 1b, and an oscillation output terminal 1c. Reference numeral 2 denotes a frequency comparator, which has an output terminal 2c that compares the input terminals 2a and 2b with two frequencies input thereto and outputs a control voltage corresponding to the difference. These VCO 1 and frequency comparator 2 constitute a PLL loop. Reference numeral 3 denotes a flip-flop, which has a data input terminal 3a, a clock terminal 3b for inputting a clock, and a data output terminal 3c. Reference numeral 4 is input data, 5 is a reference clock having the same frequency as the data rate of the input data 4, 6 is reproduction data, 7 is a reproduction clock, and 8 is a control signal.

  Input data 4 is input to the phase control input terminal 1 a of the VCO 1 and the data input terminal 3 a of the flip-flop 3. The VCO 1 oscillates the reproduction clock 7 at a frequency corresponding to the control signal (voltage) 8, and the phase is adjusted to match the timing of the input data 4, that is, the voltage value transition timing. The flip-flop 3 retimes the input data 4 by the reproduction clock 7 output from the VCO 1 and outputs the reproduction data 6. In the frequency comparator 2, the frequencies of the reference clock 5 and the recovered clock 7 are compared, and a control signal 8 proportional to the frequency difference is sent to the VCO 1.

  Therefore, since the VCO 1 oscillates at the same frequency as the reference clock 5 having the same frequency as the data rate of the input data 4, the recovered clock 7 is a clock whose phase and frequency match the input data 4. As a result, no bit error occurs during retiming in the flip-flop 3.

  Here, the control signal 8 to the VCO 1 is connected to the output of the frequency comparator 2. In order to operate the control signal 8 slowly, a charge pump and a low-pass filter are provided between the frequency comparator 2 and the VCO 1. It goes without saying that may be connected.

  The frequency comparator 2 changes the control signal 8 when there is a frequency difference between the two inputs of the reference clock 5 and the reproduction clock 7, but controls the control signal 8 so as not to change when there is a certain frequency error. Also good.

  Further, the flip-flop 3 may be replaced with a FIFO (Fast-In-Fast-Out) so that the timing of writing the input data 4 and the timing of reading the reproduction data 6 are different.

[Second embodiment]
FIG. 2 shows a second embodiment of the present invention, in which the recovered clock 7 and reference clock 5 output from the VCO 1 are divided by 1 / n times and 1 / m times (n and m are integers) by frequency dividers 9 and 10, respectively. ), The frequency comparator 2 detects the frequency difference.

  When the oscillation frequency of the VCO 1 is high, the operating speed required for the frequency comparator 2 can be reduced by comparing the frequency after frequency division as in this embodiment. In this case, the frequency of the reference clock 5 is set to the m / n frequency of the data rate of the input data 4. Even when the frequency comparator 2 compares the clock signals divided by the frequency dividers 9 and 10 in this way, the effect of the present invention is not impaired. Here, n or m may be 1, that is, either the frequency divider 9 or the frequency divider 10 may be deleted.

FIG. 3 is a block diagram illustrating a configuration of a timing extraction circuit according to the first exemplary embodiment of the present invention. It is a block diagram which shows the structure of the timing extraction circuit of the 2nd Example of this invention. It is a block diagram which shows the structure of the conventional timing extraction circuit.

Explanation of symbols

1, 11, 12: VCO
2: frequency comparator 3: flip-flop 4: input data 5: reference clock 6: reproduction data 7: reproduction clock 8: control signal 9, 10: frequency divider

Claims (4)

An oscillation circuit having a frequency control input terminal, an output terminal for outputting a recovered clock, and a phase control input terminal for controlling the phase of the recovered clock, and inputting a reference clock and the recovered clock and comparing their frequencies And a frequency comparator for inputting the result to the frequency control input terminal of the oscillation circuit as a control signal,
The frequency comparator performs closed loop control so that the frequency of the recovered clock matches the frequency of the reference clock, and the oscillation circuit inputs the input data to the phase control input terminal to match the timing of the input data. A timing extraction circuit characterized by instantaneously adjusting the phase of a recovered clock.   Frequency dividers for dividing the frequency of the reproduction clock and the reference clock by 1 / n times and 1 / m times (n and m are integers, n = m or n ≠ m), respectively. 2. The timing extraction circuit according to claim 1, wherein a signal output from a frequency is input to the frequency comparator.   3. The timing according to claim 1, further comprising a flip-flop that inputs the input data to a data input terminal, inputs the reproduction clock to a clock input terminal, performs a retiming operation, and outputs the reproduction data. Extraction circuit. 4. The timing extraction circuit according to claim 3, wherein the flip-flop is replaced with a FIFO.

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