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JP2007166005A - Synthesizer module - Google Patents

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JP2007166005A
JP2007166005A JP2005356328A JP2005356328A JP2007166005A JP 2007166005 A JP2007166005 A JP 2007166005A JP 2005356328 A JP2005356328 A JP 2005356328A JP 2005356328 A JP2005356328 A JP 2005356328A JP 2007166005 A JP2007166005 A JP 2007166005A
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ground pattern
insulating substrate
pll circuit
filter
pattern region
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Hironori Kobayashi
浩紀 小林
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Alps Alpine Co Ltd
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Alps Electric Co Ltd
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Priority to JP2005356328A priority Critical patent/JP2007166005A/en
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a synthesizer module in which leakage of a reference signal to a voltage controlled oscillator 1 is eliminated by connecting a filter 4 for removing the reference signal between a ground pattern region 7 for PLL circuit and a wide area ground pattern 11. <P>SOLUTION: A voltage controlled oscillator 1 and a PLL circuit 2 are mounted, and a ground pattern region 6 for the voltage controlled oscillator and a ground pattern region 7 for the PLL circuit are formed on the upper surface of an insulating substrate 5, and a wide area ground pattern 11 is formed on the lower surface of the insulating substrate 5. Furthermore, a filter 4 for removing the reference signal of the PLL circuit is mounted and a ground pattern region 10 for the filter is formed on the upper surface of the insulating substrate 5, the filter 4 is connected between the ground pattern region 7 for the PLL circuit and the ground pattern region 10 for the filter, and the ground pattern region 10 for the filter is connected conductively with the wide area ground pattern 11. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、電圧制御発振器とPLL回路とを一体構成したシンセサイザモジュールに係り、特に、電圧制御発振器とPLL回路との一体構成時に、電圧制御発振器やPLL回路から漏洩するスプリアス周波数成分が電圧制御発振器の発振信号に重畳するのを抑圧する手段を備えたシンセサイザモジュールに関する。   The present invention relates to a synthesizer module in which a voltage controlled oscillator and a PLL circuit are integrated, and in particular, a spurious frequency component leaking from the voltage controlled oscillator and the PLL circuit when the voltage controlled oscillator and the PLL circuit are integrated is a voltage controlled oscillator. The present invention relates to a synthesizer module provided with means for suppressing superimposition on the oscillation signal.

一般に、高周波送受信機器においては、クロック信号を発生する電圧制御発振器と、その電圧制御発振器から発振されるクロック周波数を所定周波数になるように制御するPLL回路とを備えている。かかる電圧制御発振器とPLL回路は、実装時にできるだけそれらの占有部分を小さくするため、通常、一体構成されたシンセサイザモジュールが用いられている。   Generally, a high-frequency transmission / reception device includes a voltage controlled oscillator that generates a clock signal and a PLL circuit that controls a clock frequency oscillated from the voltage controlled oscillator to a predetermined frequency. Such voltage-controlled oscillators and PLL circuits usually use an integrally configured synthesizer module in order to minimize the occupied portion when mounted.

ここで、図4は、代表的なシンセサイザモジュールの回路構成の一例を示すブロック図である。   Here, FIG. 4 is a block diagram showing an example of a circuit configuration of a typical synthesizer module.

図4に示されるように、このシンセサイザモジュールは、電圧制御発振器(VCO)31とPLL回路(PLL)32とからなり、電圧制御発振器31は、制御端31(2)がPLL回路32の制御出力端32(1)に接続され、その接地端31(3)がPLL回路32の接地端32(3)と一緒に接地パターン(図3に図示なし)に接続され、出力端31(1)から高周波発振信号(RF)が出力される。また、図3に図示されていないが、基準周波数発生器が用いられ、この基準周波数発生器の出力がPLL回路32の制御入力端32(2)に接続されている。この場合、PLL回路32は、電圧制御発振器31から出力された高周波発振信号の周波数と基準周波数発生器から供給された基準周波数信号の周波数とが比較され、その比較結果に対応した周波数制御電圧が制御出力端32(1)から電圧制御発振器31の制御端31(2)に供給され、その周波数制御電圧により電圧制御発振器31の発振周波数が所定周波数になるように制御される。   As shown in FIG. 4, the synthesizer module includes a voltage controlled oscillator (VCO) 31 and a PLL circuit (PLL) 32, and the control terminal 31 (2) of the voltage controlled oscillator 31 is a control output of the PLL circuit 32. The ground terminal 31 (3) is connected to the ground pattern (not shown in FIG. 3) together with the ground terminal 32 (3) of the PLL circuit 32, and the output terminal 31 (1) is connected to the ground terminal 31 (1). A high frequency oscillation signal (RF) is output. Although not shown in FIG. 3, a reference frequency generator is used, and an output of the reference frequency generator is connected to the control input terminal 32 (2) of the PLL circuit 32. In this case, the PLL circuit 32 compares the frequency of the high-frequency oscillation signal output from the voltage-controlled oscillator 31 with the frequency of the reference frequency signal supplied from the reference frequency generator, and the frequency control voltage corresponding to the comparison result is obtained. The voltage is supplied from the control output terminal 32 (1) to the control terminal 31 (2) of the voltage controlled oscillator 31 and controlled by the frequency control voltage so that the oscillation frequency of the voltage controlled oscillator 31 becomes a predetermined frequency.

かかる構成を備えたシンセサイザモジュールは、構成上単純なものであるが、電圧制御発振器31の接地端31(3)とPLL回路32の接地端32(3)とが共通の接地パターンに接続されているので、スプリアス周波数成分がPLL回路32から共通の接地パターンを通して電圧制御発振器31に供給され、電圧制御発振器31から発生する高周波信号にこのスプリアス周波数成分が重畳することがある。   The synthesizer module having such a configuration is simple in configuration, but the ground terminal 31 (3) of the voltage controlled oscillator 31 and the ground terminal 32 (3) of the PLL circuit 32 are connected to a common ground pattern. Therefore, the spurious frequency component may be supplied from the PLL circuit 32 to the voltage controlled oscillator 31 through a common ground pattern, and this spurious frequency component may be superimposed on the high frequency signal generated from the voltage controlled oscillator 31.

近年、高周波送受信機器の小型化のために、できるだけ小型のシンセサイザモジュールを構成すること、及び、利用周波数帯域の高周波化に伴い電圧制御発振器の高周波発振信号の周波数を高く設定する要望が強くなっている。この場合、シンセサイザモジュールの小型化の要望や利用周波数帯域のより高周波化の要望に沿ったシンセサイザモジュールを実装構成する場合は、必然的に電圧制御発振器とPLL回路とをかなり接近した状態で実装する必要がある。ところが、電圧制御発振器とPLL回路とを近接配置したときは、それらの間で相互影響が生じることが多くなり、その結果、前記代表的なシンセサイザモジュールのように、電圧制御発振器から出力される高周波発振信号にスプリアス周波数成分が重畳したりするようになる。   In recent years, in order to reduce the size of high-frequency transmission / reception equipment, there has been a growing demand to configure a synthesizer module that is as small as possible, and to set the frequency of the high-frequency oscillation signal of the voltage-controlled oscillator to a higher value as the frequency band used increases. Yes. In this case, when the synthesizer module is mounted and configured in accordance with the demand for miniaturization of the synthesizer module and the demand for higher frequency of use frequency band, the voltage controlled oscillator and the PLL circuit are necessarily mounted in a considerably close state. There is a need. However, when the voltage controlled oscillator and the PLL circuit are arranged close to each other, mutual effects often occur between them, and as a result, the high frequency output from the voltage controlled oscillator as in the typical synthesizer module. A spurious frequency component is superimposed on the oscillation signal.

かかるスプリアス周波数成分の影響を除去するため、実装時の接地構造に工夫を施し、一つの機能回路グループから出力されたノイズ成分が他の機能回路グループに伝送されないようにした実装構造が提案されており、その中の一つとして、特開2004−119598号に開示の実装構造がある。   In order to eliminate the influence of such spurious frequency components, a mounting structure has been proposed in which the grounding structure at the time of mounting is devised so that noise components output from one functional circuit group are not transmitted to other functional circuit groups. One of them is a mounting structure disclosed in Japanese Patent Application Laid-Open No. 2004-119598.

図5は、特開2004−119598号に開示の実装構造の横断面を示す断面図である。   FIG. 5 is a sectional view showing a transverse section of the mounting structure disclosed in Japanese Patent Application Laid-Open No. 2004-119598.

図5に示されるように、この実装構造は、3層構造の絶縁基板41、42、43を備え、最上層の絶縁基板41は、その上側に4つの機能回路グループ44A、44B、44C、44Dとそれらの接地パターン領域45A、45B、45C、45Dが形成され、絶縁基板41、42の間に中間接地パターン46が形成され、絶縁基板42、43の間に電源供給パターン47が形成され、絶縁基板43の下側に接地パターン48が形成されたものである。この場合、中間接地パターン46及び接地パターン48は外部接地点Gに接続され、電源供給パターン4は外部電源供給端子Vccに接続されている。   As shown in FIG. 5, this mounting structure includes insulating substrates 41, 42 and 43 having a three-layer structure, and the uppermost insulating substrate 41 has four functional circuit groups 44A, 44B, 44C and 44D on the upper side thereof. And ground pattern regions 45A, 45B, 45C and 45D are formed, an intermediate ground pattern 46 is formed between the insulating substrates 41 and 42, a power supply pattern 47 is formed between the insulating substrates 42 and 43, and insulation is performed. A ground pattern 48 is formed on the lower side of the substrate 43. In this case, the intermediate ground pattern 46 and the ground pattern 48 are connected to the external ground point G, and the power supply pattern 4 is connected to the external power supply terminal Vcc.

そして、4つの接地パターン領域45A、45B、45C、45Dは、それぞれ中間接地パターン46に導電接続されるとともに、絶縁基板42、43の間にそれぞれ形成されたスルーホール49A、49B、49C、49Dを通して接地パターン48に導電接続され、4つの機能回路グループ44A、44B、44C、44Dの接地回路が形成されている。また、4つの機能回路グループ44A、44B、44C、44Dの各電源端子は、絶縁基板41、42の間にそれぞれ形成されたスルーホール50A、50B、50C、50Dを通して電源供給パターン47に導電接続され、それらの電源供給経路が形成されている。   The four ground pattern regions 45A, 45B, 45C, and 45D are conductively connected to the intermediate ground pattern 46, and through through holes 49A, 49B, 49C, and 49D formed between the insulating substrates 42 and 43, respectively. The ground pattern 48 is conductively connected to form four functional circuit groups 44A, 44B, 44C and 44D. The power terminals of the four functional circuit groups 44A, 44B, 44C, and 44D are conductively connected to the power supply pattern 47 through through holes 50A, 50B, 50C, and 50D formed between the insulating substrates 41 and 42, respectively. These power supply paths are formed.

前記構成によるこの実装構造は、4つの機能回路グループ44A、44B、44C、44Dの各接地パターン領域45A、45B、45C、45Dは、広域の中間接地パターン46に導電接続されるとともに、スルーホール49A、49B、49C、49Dを通して接地パターン48に導電接続されるので、4つの機能回路グループ44A、44B、44C、44D間に動作時に大きな電流差があっても、各接地パターン領域45A、45B、45C、45D間に電流が流れることがなく、4つの機能回路グループ44A、44B、44C、44Dの接地レベルが変動しない安定化したものになり、例えば、機能回路グループ44C、44Dが電圧制御発振器であり、機能回路グループ44A、44BがPLL回路であっても、電圧制御発振器から出力されるクロック信号に含まれるジッタを低減させることができるものである。
特開2004−119598号
In this mounting structure having the above-described configuration, the ground pattern areas 45A, 45B, 45C, and 45D of the four functional circuit groups 44A, 44B, 44C, and 44D are conductively connected to the intermediate ground pattern 46 in a wide area, and the through hole 49A. 49B, 49C, and 49D, the ground pattern 48 is conductively connected. Even if there is a large current difference during operation between the four functional circuit groups 44A, 44B, 44C, and 44D, the ground pattern regions 45A, 45B, and 45C are connected. , 45D, no current flows between the four functional circuit groups 44A, 44B, 44C, 44D, and the ground level of the functional circuit groups 44C, 44D is stabilized. For example, the functional circuit groups 44C, 44D are voltage controlled oscillators. Even if the functional circuit groups 44A and 44B are PLL circuits, voltage controlled oscillation It is capable of reducing the jitter on the clock signal output from the.
JP 2004-119598 A

前記特開2004−119598号に開示の実装構造は、4つの機能回路グループ44A、44B、44C、44Dの各接地パターン領域45A、45B、45C、45Dが広域の中間接地パターン46によって導電接続された構成になっているため、4つの機能回路グループ44A、44B、44C、44Dのいずれかが電圧制御発振器であり、他のいずれかがPLL回路である場合に、基準周波数信号と周波数比較される基準周波数比較信号や、PLL回路で発生する位相比較周波数信号等のスプリアス周波数信号成分が導電接続された広域の中間接地パターン46を通して電圧制御発振器に回り込み、それによりスプリアス周波数信号成分が重畳されたクロック信号が出力されることがある。   In the mounting structure disclosed in Japanese Patent Application Laid-Open No. 2004-119598, the ground pattern areas 45A, 45B, 45C, and 45D of the four functional circuit groups 44A, 44B, 44C, and 44D are conductively connected by a wide-area intermediate ground pattern 46. Therefore, when one of the four functional circuit groups 44A, 44B, 44C, and 44D is a voltage-controlled oscillator and the other is a PLL circuit, the reference that is frequency-compared with the reference frequency signal A clock signal in which a spurious frequency signal component such as a frequency comparison signal and a phase comparison frequency signal generated by a PLL circuit wraps around a voltage-controlled oscillator through a wide intermediate ground pattern 46 electrically connected to the spurious frequency signal component. May be output.

本発明は、このような技術的背景に鑑みてなされたもので、その目的は、PLL回路の接地パターン領域と広域の接地パターン間に、スプリアス周波数信号成分を除去するフィルタを接続し、電圧制御発振器へのスプリアス周波数信号成分の回り込みをなくしたシンセサイザモジュールを提供することにある。   The present invention has been made in view of such a technical background, and an object of the present invention is to connect a filter for removing spurious frequency signal components between a ground pattern region of a PLL circuit and a wide-area ground pattern to control voltage. An object of the present invention is to provide a synthesizer module that eliminates spurious frequency signal components from sneaking into an oscillator.

前記目的を達成するために、本発明によるシンセサイザモジュールは、絶縁基板を用い、絶縁基板の上面に、電圧制御発振器及びPLL回路を装着するとともに電圧制御発振器用接地パターン領域及びPLL回路用接地パターン領域を形成し、絶縁基板の下面に広域接地パターンを形成したものであって、絶縁基板の上面にさらにPLL回路の基準信号を除去するフィルタを装着するとともにフィルタ用接地パターン領域を形成し、フィルタの入力端をPLL回路用接地パターン領域に接続し、フィルタの出力端をフィルタ用接地パターン領域に導電接続し、フィルタ用接地パターン領域を広域接地パターンに導電接続した第1構成手段を具備する。   In order to achieve the above object, a synthesizer module according to the present invention uses an insulating substrate, and a voltage controlled oscillator and a PLL circuit are mounted on the upper surface of the insulating substrate, and a ground pattern region for the voltage controlled oscillator and a ground pattern region for the PLL circuit. A wide-area ground pattern is formed on the lower surface of the insulating substrate, and a filter for removing the reference signal of the PLL circuit is further mounted on the upper surface of the insulating substrate and a ground pattern area for the filter is formed. First input means having an input end connected to the PLL circuit ground pattern region, a filter output end conductively connected to the filter ground pattern region, and a filter ground pattern region conductively connected to the wide area ground pattern is provided.

この場合、第1構成手段における電圧制御発振器用接地パターン領域と広域接地パターンとの間及びフィルタ用接地パターン領域と広域接地パターンとの間は、それぞれ絶縁基板に設けたスルーホールを介して導電接続しているものである。   In this case, a conductive connection is made between the ground pattern area for the voltage controlled oscillator and the wide area ground pattern and the ground pattern area for the filter and the wide area ground pattern in the first component via through holes provided in the insulating substrate. It is what you are doing.

また、前記目的を達成するために、本発明によるシンセサイザモジュールは、上側絶縁基板及び下側絶縁基板からなる積層型絶縁基板を用い、上側絶縁基板の上面に、電圧制御発振器及びPLL回路を装着するとともに電圧制御発振器用接地パターン領域及びPLL回路用接地パターン領域を形成し、下側絶縁基板の下面に広域接地パターンを形成したものであって、上側絶縁基板の上面にさらにPLL回路の基準信号を除去するフィルタを装着するとともにフィルタの入力端及び出力端に別個に導電接続される入力側接続パターン領域及び出力側接続パターン領域を形成し、上側絶縁基板と下側絶縁基板との接合部に部分的接地パターンを形成し、前記PLL回路用接地パターン領域及び入力側接続パターン領域を部分的接地パターンに導電接続し、出力側接続パターン領域を広域接地パターンに導電接続した第2構成手段を具備する。   In order to achieve the above object, a synthesizer module according to the present invention uses a laminated insulating substrate composed of an upper insulating substrate and a lower insulating substrate, and a voltage controlled oscillator and a PLL circuit are mounted on the upper surface of the upper insulating substrate. In addition, a ground pattern region for a voltage controlled oscillator and a ground pattern region for a PLL circuit are formed, and a wide-area ground pattern is formed on the lower surface of the lower insulating substrate, and a reference signal for the PLL circuit is further provided on the upper surface of the upper insulating substrate. A filter to be removed is mounted, and an input-side connection pattern region and an output-side connection pattern region that are separately conductively connected to the input end and output end of the filter are formed, and a portion is formed at the junction between the upper insulating substrate and the lower insulating substrate. A ground pattern is formed, and the ground pattern area for the PLL circuit and the input side connection pattern area are guided to the partial ground pattern. Connect comprises a second configuration means conductively connecting the output connection pattern region to a wide area ground pattern.

この場合、第2構成手段における電圧制御発振器用接地パターン領域と広域接地パターンとの間及びフィルタ用接地パターン領域と広域接地パターンとの間それにPLL回路用接地パターン領域と部分的接地パターンとの間及び入力側接続パターン領域と部分的接地パターンとの間は、それぞれ介在する絶縁基板に設けたスルーホールを介して導電接続しているものである。   In this case, between the ground pattern area for the voltage controlled oscillator and the wide area ground pattern and between the ground pattern area for the filter and the wide area ground pattern in the second constituent means, and between the ground pattern area for the PLL circuit and the partial ground pattern. In addition, the input side connection pattern region and the partial ground pattern are electrically connected through through holes provided in the interposed insulating substrate.

以上のように、請求項1及び2に記載のシンセサイザモジュールによれば、電圧制御発振器とPLL回路を装着した絶縁基板の上面に、PLL回路の基準信号を除去するフィルタを装着し、当該絶縁基板の上面にそれぞれ形成したPLL回路用接地パターン領域とフィルタ用接地パターン領域との間に、このPLL回路の基準信号を除去するフィルタを接続するようにしたもので、電圧制御発振器用接地パターン領域及びPLL回路用接地パターン領域とがこの回路のPLL回路の基準信号を除去するフィルタを介して接続され、それにより接地手段を通してPLL回路から電圧制御発振器に回り込むPLL回路の基準信号がこのPLL回路の基準信号を除去するフィルタによって阻止され、PLL回路の基準信号が電圧制御発振器に回り込み入力されるのを防ぐことができるという効果がある。   As described above, according to the synthesizer module according to claim 1, the filter for removing the reference signal of the PLL circuit is mounted on the upper surface of the insulating substrate on which the voltage controlled oscillator and the PLL circuit are mounted, and the insulating substrate A filter for removing the reference signal of the PLL circuit is connected between the PLL circuit ground pattern region and the filter ground pattern region respectively formed on the upper surface of the voltage control oscillator. The PLL circuit ground pattern region is connected via a filter that removes the reference signal of the PLL circuit of this circuit, so that the reference signal of the PLL circuit that passes from the PLL circuit to the voltage controlled oscillator through the grounding means is the reference of this PLL circuit. Blocked by a filter that removes the signal, the reference signal of the PLL circuit wraps around the voltage controlled oscillator There is an effect that it is possible to prevent the input.

また、請求項3及び4に記載のシンセサイザモジュールによれば、電圧制御発振器用接地パターン領域を下側絶縁基板の下面に形成した広域接地パターンに接続し、PLL回路用接地パターン領域を上側絶縁基板と下側絶縁基板との接合部に形成した部分的接地パターンに接続した後、PLL回路の基準信号を除去するフィルタを介して広域接地パターンに接続するようにしているので、このPLL回路の基準信号を除去するフィルタの接続と相俟って、接地手段を通してPLL回路から電圧制御発振器に回り込むPLL回路の基準信号が電圧制御発振器に回り込み入力されるのをほぼ完全に防ぐことができるという効果がある。   According to the synthesizer module of claim 3, the voltage-controlled oscillator ground pattern region is connected to a wide-area ground pattern formed on the lower surface of the lower insulating substrate, and the PLL circuit ground pattern region is connected to the upper insulating substrate. After connecting to the partial ground pattern formed at the junction of the lower insulating substrate and the lower insulating substrate, it is connected to the wide area ground pattern through a filter that removes the reference signal of the PLL circuit. Combined with the connection of the filter for removing the signal, there is an effect that it is possible to almost completely prevent the reference signal of the PLL circuit that goes from the PLL circuit to the voltage controlled oscillator through the grounding means and is inputted to the voltage controlled oscillator. is there.

以下、本発明の実施の形態を図面を参照して説明する。   Hereinafter, embodiments of the present invention will be described with reference to the drawings.

図1は、本発明によるシンセサイザモジュールの構成の概要を示すもので、その要部構成を示すブロック図である。   FIG. 1 is a block diagram showing an outline of the configuration of a synthesizer module according to the present invention.

図1に示されるように、このシンセサイザモジュールは、電圧制御発振器(VCO)1と、PLL回路(PLL)2と、基準周波数信号発生器(X−TAL)3と、基準信号除去用フィルタ(FL)4とからなっている。そして、電圧制御発振器1は、出力端1(1)と周波数制御端1(2)と接地端1(3)とを有し、周波数制御端1(2)がPLL回路2の周波数制御出力端2(1)に接続され、接地端1(3)が接地接続され、出力端1(1)から高周波発振信号(RF)が出力される。PLL回路2は、周波数制御出力端2(1)と基準周波数信号入力端2(2)と接地端2(3)とを有し、基準周波数信号入力端2(2)が基準周波数発生器3の基準周波数信号出力端3(1)に接続され、接地端2(3)が基準信号除去用フィルタ4の入力端4(1)に接続される。基準周波数発生器3は、基準周波数信号出力端3(1)と接地端3(2)とを有し、接地端3(2)が接地接続される。基準信号除去用フィルタ4は、入力端4(1)と出力端4(2)とを有し、出力端4(2)が接地接続される。   As shown in FIG. 1, the synthesizer module includes a voltage controlled oscillator (VCO) 1, a PLL circuit (PLL) 2, a reference frequency signal generator (X-TAL) 3, and a reference signal removal filter (FL). ) 4. The voltage controlled oscillator 1 has an output terminal 1 (1), a frequency control terminal 1 (2), and a ground terminal 1 (3), and the frequency control terminal 1 (2) is a frequency control output terminal of the PLL circuit 2. 2 (1), the ground terminal 1 (3) is grounded, and a high frequency oscillation signal (RF) is output from the output terminal 1 (1). The PLL circuit 2 has a frequency control output terminal 2 (1), a reference frequency signal input terminal 2 (2), and a ground terminal 2 (3). The reference frequency signal input terminal 2 (2) is a reference frequency generator 3. Is connected to the reference frequency signal output terminal 3 (1), and the ground terminal 2 (3) is connected to the input terminal 4 (1) of the reference signal removal filter 4. The reference frequency generator 3 has a reference frequency signal output terminal 3 (1) and a ground terminal 3 (2), and the ground terminal 3 (2) is grounded. The reference signal removal filter 4 has an input end 4 (1) and an output end 4 (2), and the output end 4 (2) is grounded.

また、図2は、図1に図示のシンセサイザモジュールの第1の実施の形態に係わるもので、実装構造の横断面を示す断面図である。   FIG. 2 is a cross-sectional view showing a transverse cross section of the mounting structure according to the first embodiment of the synthesizer module shown in FIG.

図2に示されるように、この実施の形態によるシンセサイザモジュールの実装構造は、絶縁基板5と、絶縁基板5の上面にそれぞれ装着された電圧制御発振器1、PLL回路2、基準周波数信号発生器3、基準信号除去用フィルタ4と、絶縁基板5の上面にそれぞれ形成された電圧制御発振器用接地パターン領域6、PLL回路用接地パターン領域7、基準周波数信号発生器用接地パターン領域8、フィルタ用入力側接続パターン領域9、フィルタ用接地パターン領域を構成するフィルタ用出力側接続パターン領域10と、絶縁基板5の下面に形成された広域接地パターン11とを備えている。また、電圧制御発振器用接地パターン領域6と広域接地パターン11との間に絶縁基板5を貫通するスルーホール12が形成されて、電圧制御発振器用接地パターン領域6と広域接地パターン11とが導電接続され、フィルタ用出力側接続パターン領域10と広域接地パターン11との間にも絶縁基板5を貫通するスルーホール13が形成されて、フィルタ用出力側接続パターン領域10と広域接地パターン11とが導電接続されている。この場合、PLL回路用接地パターン領域7、基準周波数信号発生器用接地パターン領域8、フィルタ用入力側接続パターン領域9とは、互いに接続された一体化構造になっている。   As shown in FIG. 2, the synthesizer module mounting structure according to this embodiment includes an insulating substrate 5, a voltage controlled oscillator 1, a PLL circuit 2, and a reference frequency signal generator 3 mounted on the upper surface of the insulating substrate 5. , A reference signal removing filter 4, a voltage-controlled oscillator ground pattern region 6, a PLL circuit ground pattern region 7, a reference frequency signal generator ground pattern region 8, and a filter input side formed on the upper surface of the insulating substrate 5, respectively. A connection pattern region 9, a filter output side connection pattern region 10 constituting the filter ground pattern region, and a wide area ground pattern 11 formed on the lower surface of the insulating substrate 5 are provided. Further, a through hole 12 penetrating the insulating substrate 5 is formed between the voltage-controlled oscillator ground pattern region 6 and the wide-area ground pattern 11 so that the voltage-controlled oscillator ground pattern region 6 and the wide-area ground pattern 11 are electrically connected. In addition, a through hole 13 penetrating the insulating substrate 5 is also formed between the filter output side connection pattern region 10 and the wide area ground pattern 11 so that the filter output side connection pattern area 10 and the wide area ground pattern 11 are electrically conductive. It is connected. In this case, the PLL circuit ground pattern region 7, the reference frequency signal generator ground pattern region 8, and the filter input side connection pattern region 9 are integrated with each other.

また、図1に図示するように、電圧制御発振器1とPLL回路2とは、電圧制御発振器1の周波数制御端1(2)がPLL回路2の周波数制御出力端2(1)に接続され、PLL回路2と基準周波数発生器3とは、PLL回路2の基準周波数信号入力端2(2)が基準周波数発生器3の基準周波数信号出力端3(1)に接続されている。   As shown in FIG. 1, the voltage controlled oscillator 1 and the PLL circuit 2 are configured such that the frequency control terminal 1 (2) of the voltage controlled oscillator 1 is connected to the frequency control output terminal 2 (1) of the PLL circuit 2, In the PLL circuit 2 and the reference frequency generator 3, the reference frequency signal input terminal 2 (2) of the PLL circuit 2 is connected to the reference frequency signal output terminal 3 (1) of the reference frequency generator 3.

前記構成によるシンセサイザモジュールは、基本的には、既に述べた図4に図示のシンセサイザモジュールにおける動作と同じ動作が行われるもので、PLL回路2は、電圧制御発振器1から出力された高周波発振信号の周波数と基準周波数発生器3から供給された基準周波数信号の周波数とを周波数比較し、その周波数比較結果に対応した周波数制御電圧が制御出力端2(1)から電圧制御発振器1の制御端1(2)に供給され、電圧制御発振器1は、供給された周波数制御電圧によりその発振周波数が所定周波数になるように制御される。   The synthesizer module having the above-described configuration basically performs the same operation as that of the synthesizer module shown in FIG. 4 described above. The PLL circuit 2 generates a high-frequency oscillation signal output from the voltage-controlled oscillator 1. The frequency is compared with the frequency of the reference frequency signal supplied from the reference frequency generator 3, and the frequency control voltage corresponding to the frequency comparison result is transferred from the control output terminal 2 (1) to the control terminal 1 ( 2), the voltage controlled oscillator 1 is controlled by the supplied frequency control voltage so that its oscillation frequency becomes a predetermined frequency.

この動作時に、PLL回路2は、基準周波数発生器3からPLL回路2に供給される基準信号や、電圧制御発振器1から出力された高周波発振信号の分周信号等がPLL回路2から外部、特に、接地手段であるPLL回路用接地パターン領域7に漏洩し、本願発明のように基準信号除去用フィルタ4を接続しないと、漏洩した基準信号や分周信号は、PLL回路用接地パターン領域7から広域接地パターン11に伝送され、次いで電圧制御発振器用接地パターン領域6に伝送され、接地手段を介して電圧制御発振器1に回り込み、電圧制御発振器1から出力されるクロック信号に重畳されるようになる。   During this operation, the PLL circuit 2 receives a reference signal supplied from the reference frequency generator 3 to the PLL circuit 2, a frequency-divided signal of the high-frequency oscillation signal output from the voltage controlled oscillator 1, etc. If the reference signal removal filter 4 is not connected as in the present invention, the leaked reference signal and the divided signal are leaked from the PLL circuit ground pattern region 7. It is transmitted to the wide-area ground pattern 11 and then transmitted to the ground pattern area 6 for the voltage controlled oscillator, wraps around the voltage controlled oscillator 1 through the grounding means, and is superposed on the clock signal output from the voltage controlled oscillator 1. .

これに対して、この実施の形態においては、PLL回路用接地パターン領域7と広域接地パターン11との間に、PLL回路2の基準信号を除去するフィルタ、すなわち基準信号除去用フィルタ4を挿入接続しているので、PLL回路用接地パターン領域7にPLL回路2から漏洩した基準信号が生じたとしても、その基準信号は基準信号除去用フィルタ4において大幅に減衰を受け、殆ど広域接地パターン11に伝送されることがないので、接地手段を介して電圧制御発振器1に基準信号が回り込むことがなくなり、電圧制御発振器1から出力されるクロック信号にスプリアス周波数成分が重畳して出力されることがない。   On the other hand, in this embodiment, a filter for removing the reference signal of the PLL circuit 2, that is, a reference signal removing filter 4 is inserted and connected between the PLL circuit ground pattern region 7 and the wide area ground pattern 11. Therefore, even if the reference signal leaked from the PLL circuit 2 is generated in the PLL circuit ground pattern region 7, the reference signal is greatly attenuated in the reference signal removal filter 4, and is almost entirely in the wide-area ground pattern 11. Since it is not transmitted, the reference signal does not wrap around the voltage controlled oscillator 1 via the grounding means, and the spurious frequency component is not superimposed on the clock signal output from the voltage controlled oscillator 1 and output. .

次いで、図3は、図1に図示のシンセサイザモジュールの第2の実施の形態に係わるもので、実装構造の横断面を示す断面図である。   Next, FIG. 3 relates to the second embodiment of the synthesizer module shown in FIG. 1, and is a sectional view showing a transverse section of the mounting structure.

図3に示されるように、この実施の形態によるシンセサイザモジュールの実装構造は、積層された上側絶縁基板5(1)及び下側絶縁基板5(2)と、上側絶縁基板5(1)の上面にそれぞれ装着された電圧制御発振器1、PLL回路2、基準周波数信号発生器3、基準信号除去用フィルタ4と、上側絶縁基板5(1)の上面にそれぞれ形成された電圧制御発振器用接地パターン領域6、PLL回路用接地パターン領域7、基準周波数信号発生器用接地パターン領域8、フィルタ用入力側接続パターン領域9、フィルタ用出力側接続パターン領域10と、下側絶縁基板5(2)の下面に形成された広域接地パターン11と、上側絶縁基板5(1)と下側絶縁基板5(2)の接合面に形成された中間接地パターン14とを備えている。   As shown in FIG. 3, the mounting structure of the synthesizer module according to this embodiment includes a stacked upper insulating substrate 5 (1) and lower insulating substrate 5 (2), and an upper surface of the upper insulating substrate 5 (1). Voltage control oscillator 1, PLL circuit 2, reference frequency signal generator 3, reference signal removal filter 4, and voltage control oscillator ground pattern region formed on the upper surface of upper insulating substrate 5 (1), respectively. 6, PLL circuit ground pattern region 7, reference frequency signal generator ground pattern region 8, filter input side connection pattern region 9, filter output side connection pattern region 10, and lower surface of lower insulating substrate 5 (2) A wide-area ground pattern 11 is formed, and an intermediate ground pattern 14 is formed on the joint surface between the upper insulating substrate 5 (1) and the lower insulating substrate 5 (2).

また、電圧制御発振器用接地パターン領域6と広域接地パターン11との間に上側絶縁基板5(1)及び下側絶縁基板5(2)を貫通するスルーホール12が形成されて、電圧制御発振器用接地パターン領域6と広域接地パターン11とが導電接続され、フィルタ用出力側接続パターン領域10と広域接地パターン11との間に上側絶縁基板5(1)及び下側絶縁基板5(2)を貫通するスルーホール13が形成されて、出力側接続パターン領域10と広域接地パターン11とが導電接続され、さらに、PLL回路用接地パターン領域7と中間接地パターン14との間に上側絶縁基板5(1)を貫通するスルーホール15が形成されて、PLL回路用接地パターン領域7と中間接地パターン14とが導電接続され、基準周波数信号発生器用接地パターン領域8と中間接地パターン14との間に上側絶縁基板5(1)を貫通するスルーホール16が形成されて、基準周波数信号発生器用接地パターン領域8と中間接地パターン14とが導電接続され、フィルタ用入力側接続パターン領域9との間に上側絶縁基板5(1)を貫通するスルーホール17が形成されて、フィルタ用入力側接続パターン領域9とが導電接続されている。   Further, a through hole 12 penetrating the upper insulating substrate 5 (1) and the lower insulating substrate 5 (2) is formed between the voltage-controlled oscillator ground pattern region 6 and the wide-area ground pattern 11, so that the voltage-controlled oscillator The ground pattern region 6 and the wide area ground pattern 11 are conductively connected, and the upper insulating substrate 5 (1) and the lower insulating substrate 5 (2) are passed between the filter output side connection pattern region 10 and the wide area ground pattern 11. Through-hole 13 is formed, and the output-side connection pattern region 10 and the wide area ground pattern 11 are conductively connected. Further, the upper insulating substrate 5 (1) is connected between the PLL circuit ground pattern region 7 and the intermediate ground pattern 14. ) Is formed so that the PLL circuit ground pattern region 7 and the intermediate ground pattern 14 are conductively connected, and the reference frequency signal generator contact is connected. A through hole 16 penetrating the upper insulating substrate 5 (1) is formed between the pattern region 8 and the intermediate ground pattern 14, and the reference frequency signal generator ground pattern region 8 and the intermediate ground pattern 14 are conductively connected. A through hole 17 penetrating the upper insulating substrate 5 (1) is formed between the filter input side connection pattern region 9 and the filter input side connection pattern region 9 is conductively connected.

前記構成を備えた第2の実施の形態によるシンセサイザモジュールは、既に述べたように、基本的に、図2に図示された第1の実施の形態によるシンセサイザモジュールにおける動作と同じ動作が行われ、PLL回路2は、電圧制御発振器1から出力された高周波発振信号の周波数と基準周波数発生器3から供給された基準周波数信号の周波数とを周波数比較し、その周波数比較結果に対応した周波数制御電圧が制御出力端2(1)から電圧制御発振器1の制御端1(2)に供給され、電圧制御発振器1は、供給された周波数制御電圧によりその発振周波数が所定周波数になるように制御される。   The synthesizer module according to the second embodiment having the above-described configuration basically performs the same operation as that of the synthesizer module according to the first embodiment illustrated in FIG. The PLL circuit 2 compares the frequency of the high-frequency oscillation signal output from the voltage-controlled oscillator 1 with the frequency of the reference frequency signal supplied from the reference frequency generator 3, and a frequency control voltage corresponding to the frequency comparison result is obtained. The voltage is supplied from the control output terminal 2 (1) to the control terminal 1 (2) of the voltage controlled oscillator 1, and the voltage controlled oscillator 1 is controlled by the supplied frequency control voltage so that the oscillation frequency becomes a predetermined frequency.

第2の実施の形態においても、PLL回路用接地パターン領域7と広域接地パターン11との間、具体的には、PLL回路用接地パターン領域7に導電接続された中間接地パターン14及び中間接地パターン14に導電接続されたフィルタ用入力側接続パターン領域9と、広域接地パターン11に導電接続されたフィルタ用出力側接続パターン領域10との間にPLL回路2の基準信号を除去するフィルタ、すなわち基準信号除去用フィルタ4を挿入接続しているので、PLL回路用接地パターン領域7にPLL回路2から漏洩した基準信号が生じたとしても、その基準信号は基準信号除去用フィルタ4において大幅に減衰を受け、殆ど広域接地パターン11に伝送されることがないので、接地手段を介して電圧制御発振器1に基準信号が回り込むことがなくなり、電圧制御発振器1から出力されるクロック信号にスプリアス周波数成分が重畳して出力されることがない。   Also in the second embodiment, an intermediate ground pattern 14 and an intermediate ground pattern which are conductively connected between the PLL circuit ground pattern region 7 and the wide area ground pattern 11, specifically, the PLL circuit ground pattern region 7. 14 is a filter that removes the reference signal of the PLL circuit 2 between the filter input side connection pattern region 9 conductively connected to 14 and the filter output side connection pattern region 10 conductively connected to the wide area ground pattern 11, that is, a reference Since the signal removal filter 4 is inserted and connected, even if a reference signal leaked from the PLL circuit 2 is generated in the PLL circuit ground pattern region 7, the reference signal is greatly attenuated in the reference signal removal filter 4. Since it is hardly transmitted to the wide area ground pattern 11, the reference signal is transmitted to the voltage controlled oscillator 1 via the grounding means. Writing it eliminates, never spurious frequency components in the clock signal output from the voltage controlled oscillator 1 is output by superimposing.

この場合、PLL回路用接地パターン領域7をフィルタ用入力側接続パターン領域9に接続する接地接続手段として中間接地パターン14を用いており、この中間接地パターン14の形成位置は、上側絶縁基板5(1)と下側絶縁基板5(2)との接合面、すなわち上側絶縁基板5(1)の下面であるのに対して、PLL回路2の配置位置やPLL回路用接地パターン領域7の形成位置は、上側絶縁基板5(1)の上面であって、上側絶縁基板5(1)の厚み分だけその形成位置を異にしているので、PLL回路2から漏洩した基準信号等が直接中間接地パターン14に伝送されることはなく、基準信号除去用フィルタ4を接続したことと相俟って、電圧制御発振器1に基準信号が回り込むことをほぼ完全になくすことができ、電圧制御発振器1から出力されるクロック信号にスプリアス周波数成分が重畳して出力されることが殆どない。   In this case, the intermediate ground pattern 14 is used as a ground connection means for connecting the PLL circuit ground pattern region 7 to the filter input side connection pattern region 9. The intermediate ground pattern 14 is formed at the upper insulating substrate 5 ( 1) and the lower insulating substrate 5 (2), that is, the lower surface of the upper insulating substrate 5 (1), the position where the PLL circuit 2 is disposed and the position where the PLL circuit ground pattern region 7 is formed Is the upper surface of the upper insulating substrate 5 (1), and its formation position is different by the thickness of the upper insulating substrate 5 (1), so that the reference signal leaked from the PLL circuit 2 is directly connected to the intermediate ground pattern. 14, coupled with the connection of the reference signal removal filter 4, it is possible to almost completely eliminate the reference signal from wrapping around the voltage controlled oscillator 1. Little spurious frequency component is output by superimposing a clock signal output from the 1.

本発明によるシンセサイザモジュールの構成の概要を示すもので、その要部構成を示すブロック図である。BRIEF DESCRIPTION OF THE DRAWINGS It is a block diagram which shows the outline | summary of a structure of the synthesizer module by this invention, and shows the principal part structure. 図1に図示のシンセサイザモジュールの第1の実施の形態に係わるもので、実装構造の横断面を示す断面図である。FIG. 2 is a cross-sectional view showing a transverse cross section of the mounting structure according to the first embodiment of the synthesizer module shown in FIG. 1. 図1に図示のシンセサイザモジュールの第2の実施の形態に係わるもので、実装構造の横断面を示す断面図である。FIG. 10 is a cross-sectional view showing a transverse cross section of the mounting structure according to the second embodiment of the synthesizer module shown in FIG. 1. 既知のシンセサイザモジュールの回路構成の一例を示すブロック図である。It is a block diagram which shows an example of the circuit structure of a known synthesizer module. 特開2004−119598号に開示の実装構造の横断面を示す断面図である。It is sectional drawing which shows the cross section of the mounting structure of Unexamined-Japanese-Patent No. 2004-119598.

符号の説明Explanation of symbols

1 電圧制御発振器(VCO)
2 PLL回路(PLL)
3 基準周波数信号発生器(X−TAL)
4 基準信号除去用フィルタ(FL)
5 絶縁基板
5(1) 上側絶縁基板
5(2) 下側絶縁基板
6 電圧制御発振器用接地パターン領域
7 PLL回路用接地パターン領域
8 基準周波数信号発生器用接地パターン領域
9 フィルタ用入力側接続パターン領域
10 フィルタ用出力側接続パターン領域(フィルタ用接地パターン領域)
11 広域接地パターン
12、13、15、16、17 スルーホール
14 中間接地パターン
1 Voltage controlled oscillator (VCO)
2 PLL circuit (PLL)
3 Reference frequency signal generator (X-TAL)
4 Reference signal removal filter (FL)
5 Insulating substrate 5 (1) Upper insulating substrate 5 (2) Lower insulating substrate 6 Voltage-controlled oscillator ground pattern area 7 PLL circuit ground pattern area 8 Reference frequency signal generator ground pattern area 9 Filter input side connection pattern area 10 Filter output side connection pattern area (filter ground pattern area)
11 Wide-area ground pattern 12, 13, 15, 16, 17 Through hole 14 Intermediate ground pattern

Claims (4)

絶縁基板を用い、前記絶縁基板の上面に、電圧制御発振器及びPLL回路を装着するとともに電圧制御発振器用接地パターン領域及びPLL回路用接地パターン領域を形成し、前記絶縁基板の下面に広域接地パターンを形成したシンセサイザモジュールであって、前記絶縁基板の上面にさらに前記PLL回路の基準信号を除去するフィルタを装着するとともに前記フィルタ用接地パターン領域を形成し、前記フィルタの入力端を前記PLL回路用接地パターン領域に接続し、前記フィルタの出力端を前記フィルタ用接地パターン領域に導電接続し、前記フィルタ用接地パターン領域を前記広域接地パターンに導電接続したことを特徴とするシンセサイザモジュール。 Using an insulating substrate, a voltage controlled oscillator and a PLL circuit are mounted on the upper surface of the insulating substrate, a ground pattern region for the voltage controlled oscillator and a ground pattern region for the PLL circuit are formed, and a wide area ground pattern is formed on the lower surface of the insulating substrate. In the synthesizer module formed, a filter for removing the reference signal of the PLL circuit is further mounted on the upper surface of the insulating substrate, the ground pattern area for the filter is formed, and the input end of the filter is connected to the ground for the PLL circuit. A synthesizer module, wherein the synthesizer module is connected to a pattern region, the output end of the filter is conductively connected to the filter ground pattern region, and the filter ground pattern region is conductively connected to the wide area ground pattern. 前記電圧制御発振器用接地パターン領域と前記広域接地パターンとの間及び前記フィルタ用接地パターン領域と前記広域接地パターンとの間は、それぞれ前記絶縁基板に設けたスルーホールを介して導電接続していることを特徴とする請求項1に記載のシンセサイザモジュール。 The voltage-controlled oscillator ground pattern region and the wide-area ground pattern and the filter ground pattern region and the wide-area ground pattern are conductively connected through through holes provided in the insulating substrate, respectively. The synthesizer module according to claim 1. 上側絶縁基板及び下側絶縁基板からなる積層型絶縁基板を用い、前記上側絶縁基板の上面に、電圧制御発振器及びPLL回路を装着するとともに電圧制御発振器用接地パターン領域及びPLL回路用接地パターン領域を形成し、前記下側絶縁基板の下面に広域接地パターンを形成したシンセサイザモジュールであって、前記上側絶縁基板の上面にさらに前記PLL回路の基準信号を除去するフィルタを装着するとともに前記フィルタの入力端及び出力端に別個に導電接続される入力側接続パターン領域及び出力側接続パターン領域を形成し、前記上側絶縁基板と前記下側絶縁基板との接合部に部分的接地パターンを形成し、前記PLL回路用接地パターン領域及び前記入力側接続パターン領域を前記部分的接地パターンに導電接続し、前記出力側接続パターン領域を前記広域接地パターンに導電接続したことを特徴とするシンセサイザモジュール。 Using a laminated insulating substrate composed of an upper insulating substrate and a lower insulating substrate, a voltage controlled oscillator and a PLL circuit are mounted on the upper surface of the upper insulating substrate, and a ground pattern region for the voltage controlled oscillator and a ground pattern region for the PLL circuit are provided. And a synthesizer module having a wide-area ground pattern formed on a lower surface of the lower insulating substrate, wherein a filter for removing a reference signal of the PLL circuit is further mounted on the upper surface of the upper insulating substrate, and an input end of the filter And an input-side connection pattern region and an output-side connection pattern region that are separately conductively connected to the output end, and a partial ground pattern is formed at a joint between the upper insulating substrate and the lower insulating substrate, and the PLL The circuit ground pattern region and the input side connection pattern region are conductively connected to the partial ground pattern, and the output Synthesizer module, wherein a side connecting pattern region is conductively connected to the wide area ground pattern. 前記電圧制御発振器用接地パターン領域と前記広域接地パターンとの間及び前記フィルタ用接地パターン領域と前記広域接地パターンとの間それに前記PLL回路用接地パターン領域と前記部分的接地パターンとの間及び前記入力側接続パターン領域と前記部分的接地パターンとの間は、それぞれ介在する絶縁基板に設けたスルーホールを介して導電接続していることを特徴とする請求項3に記載のシンセサイザモジュール。 Between the ground pattern area for the voltage controlled oscillator and the wide area ground pattern, between the ground pattern area for the filter and the wide area ground pattern, between the ground pattern area for the PLL circuit and the partial ground pattern, and 4. The synthesizer module according to claim 3, wherein the input side connection pattern region and the partial ground pattern are conductively connected through through holes provided in an insulating substrate interposed therebetween. 5.
JP2005356328A 2005-12-09 2005-12-09 Synthesizer module Withdrawn JP2007166005A (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102830471A (en) * 2009-10-29 2012-12-19 住友电气工业株式会社 Pluggable optical transceiver and manufacturing method therefor
US8821038B2 (en) 2009-10-29 2014-09-02 Sumitomo Electric Industries, Ltd. Pluggable optical transceiver having inner optical connection and optical connector installed therein
US8821039B2 (en) 2009-10-29 2014-09-02 Sumitomo Electric Industries, Ltd. Optical transceiver having optical receptacle arranged diagonally to longitudinal axis
US9052477B2 (en) 2009-10-29 2015-06-09 Sumitomo Electric Industries, Ltd. Optical transceiver with inner fiber set within tray securing thermal path from electronic device to housing

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102830471A (en) * 2009-10-29 2012-12-19 住友电气工业株式会社 Pluggable optical transceiver and manufacturing method therefor
US8821038B2 (en) 2009-10-29 2014-09-02 Sumitomo Electric Industries, Ltd. Pluggable optical transceiver having inner optical connection and optical connector installed therein
US8821039B2 (en) 2009-10-29 2014-09-02 Sumitomo Electric Industries, Ltd. Optical transceiver having optical receptacle arranged diagonally to longitudinal axis
US8821037B2 (en) 2009-10-29 2014-09-02 Sumitomo Electric Industries, Ltd. Method for manufacturing pluggable optical transceiver
US9052477B2 (en) 2009-10-29 2015-06-09 Sumitomo Electric Industries, Ltd. Optical transceiver with inner fiber set within tray securing thermal path from electronic device to housing

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