JP2007164837A - Nonvolatile storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nonvolatile storage device in which a highly accurate data read-out can be executed by suppressing decrease of a data read-out margin in a constitution for executing read-out of the data with a plurality of bits. <P>SOLUTION: A sub-source line SLP electrically connected anew to a fixed voltage is arranged along a column direction, and it is electrically connected each other with a plurality of source lines arranged along a memory cell row. By this arrangement, when a path of current flowing into the source lines SL of the memory cell side and a path of current flowing into the source lines SL of a dummy memory cell side are looked up, a floating of potentials based on parasitic resistances of the source lines is set to the same potential each other by the sub-source line SLP and become equivalent. That is, since the floating of the potentials based on the parasitic resistances of the sources becomes the same floating, a constant data read-out margin can be secured by suppressing the excessive increase or decrease of the data read-out voltage in the relation relative with a reference current flowing into the source lines. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a nonvolatile memory device, and more particularly to an MRAM (Magnetic Random Access Memory).

  In recent years, MRAM devices have attracted attention as a new generation of nonvolatile storage devices. An MRAM device is a non-volatile storage device that is formed in a semiconductor integrated circuit and allows a plurality of accesses.

  In particular, in recent years, it has been announced that the performance of an MRAM device will be dramatically improved by using it as a thin film magnetic memory cell using a magnetic tunnel junction (MTJ).

  In general, when data reading of a memory cell used as a storage device of these nonvolatile storage devices is executed, a predetermined voltage is applied to a tunnel magnetoresistive element (TMR) constituting the storage device, A configuration is used in which data reading is performed by detecting the passing current at that time.

  For example, the resistance value of a tunnel magnetoresistive element (TMR) that is a memory cell in a memory state with a data level “1” is R, and the resistance value of a tunnel magnetoresistive element (TMR) in a memory state “0” is “R + ΔR”. ", A standard dummy memory cell is arranged in addition to the normal memory cell in the memory cell array, and the stored data is read based on a comparison of the passing currents of the two.

  Specifically, the resistance value of the dummy memory cell is fixed, and the tunnel magnetoresistive element (TMR) constituting the memory cell has an intermediate value between the resistance value in the storage state of “1” and the resistance value in the storage state of “0”. Designed to have a value of.

  Reading of stored data is performed by amplifying a voltage difference based on a difference in passing current flowing between the selected memory cell and the dummy memory cell and comparing the magnitudes of the voltages.

  For example, if the voltage obtained from the memory cell is smaller than the voltage obtained from the dummy memory cell, the storage state of the memory cell, that is, the data level is “0”, and if it is greater, the storage state of the memory cell (ie, the data level) is “1”. ". In this example, the resistance value of the tunnel magnetoresistive element is described in relation to the storage state of the memory cell, that is, the data level, corresponding to “0” and “1” for the high resistance state (Rmax) and the low resistance state (Rmin). However, the present invention is not limited to this, and the data levels can be described in association with “1” and “0”, respectively.

In the above example, 1-bit data reading has been described. For example, in Japanese Patent Application Laid-Open No. 2004-103060, a configuration in which data reading of a plurality of bits, for example, 4 bits is executed in parallel by comparison with a reference current flowing through a dummy memory cell. As shown, large-capacity data can be read out.
JP 2004-103060 A

  However, when data reading of a plurality of bits is executed, a data reading current is supplied for each bit, so that a data reading current for a plurality of bits flows through the source line.

  In recent years, the capacity of a memory array has also been increased, and the parasitic resistance of the source line accompanying the increase in the wiring length of the source line has become a size that cannot be ignored.

  That is, when the parasitic resistance of the source line is large, the source line is lifted by a voltage drop based on the product of the parasitic resistance and the flowing data read current. In particular, it is considered that as the data read current flowing through the source line increases, the degree of floating increases and the data read current decreases.

  In general, since the source line uses a diffusion layer having a high resistance value, the longer the current flow path, the higher the parasitic resistance. Therefore, depending on the position of a group of memory cells that perform data reading, There is a possibility that an excessive lift will occur.

  Such floating of the source line lowers the data read margin, so that there is a possibility that highly accurate data read cannot be executed.

  The present invention has been made to solve the above-described problem, and in a configuration in which data reading of a plurality of bits is performed, it is possible to perform highly accurate data reading while suppressing a decrease in data reading margin. An object of the present invention is to provide a possible non-volatile storage device.

  A nonvolatile memory device according to the present invention includes a memory cell array having a plurality of memory cells and a plurality of dummy memory cells arranged in a matrix and executing nonvolatile data storage, and a plurality of bits of parallel data reading at the time of data reading And a plurality of data line pairs provided corresponding to the plurality of read circuits, respectively. The plurality of dummy memory cells are arranged so as to share the memory cell columns of the plurality of memory cells arranged in a matrix. The memory cell array is provided with a plurality of word lines provided corresponding to the memory cell rows, a plurality of bit lines provided corresponding to the memory cell columns, and a memory cell row, respectively. A plurality of source lines electrically coupled to the voltage and electrically coupled to the corresponding bit line via the memory cell group of the corresponding memory cell column. The plurality of bit lines are divided into a plurality of groups including a bit line group in which parallel data reading is executed during the data reading. A plurality of gate transistor groups that are provided corresponding to a plurality of groups, respectively, and that control electrical connection between the bit line groups included in the corresponding groups and the plurality of data line pairs in response to a column selection instruction. Is further provided. At the time of data reading, one data line of each of the data line pairs is electrically coupled to a corresponding source line via a memory cell corresponding to a selected word line of the plurality of word lines to be stored data. A corresponding data read current is supplied. During data read, the other data line of each data line pair is electrically coupled to a corresponding source line via a dummy memory cell and supplied with a reference current used as a target for comparison with the data read current. . The memory cell array further includes sub-source lines provided to intersect the plurality of source lines and electrically coupled to each other.

  Another nonvolatile memory device according to the present invention is arranged in a matrix and has a memory cell array having a plurality of memory cells for executing nonvolatile data storage, and for performing parallel data reading of a plurality of bits at the time of data reading A plurality of read circuits, and a plurality of data line pairs provided corresponding to the plurality of read circuits, respectively. The memory cell array is provided with a plurality of word lines provided corresponding to the memory cell rows, a plurality of bit lines provided corresponding to the memory cell columns, and a memory cell row, respectively. A plurality of source lines electrically coupled to the voltage and electrically coupled to the corresponding bit line via the memory cell group of the corresponding memory cell column. The plurality of bit lines are divided into a plurality of groups including bit line groups in which parallel data reading is executed at the time of data reading, provided corresponding to the plurality of groups, respectively, each in response to a column selection instruction. It further includes a plurality of gate transistor groups for controlling electrical connection between the bit line group included in the corresponding group and the plurality of data line pairs. At the time of data reading, one data line of each of the data line pairs is electrically coupled to a corresponding source line via a memory cell corresponding to a selected word line of the plurality of word lines to be stored data. A corresponding data read current is supplied. During data read, the other data line of each data line pair is electrically coupled to a corresponding source line via a dummy memory cell and supplied with a reference current used as a target for comparison with the data read current. . At least one of the plurality of groups constitutes a shape dummy group that does not execute the data reading. A plurality of column selection lines are provided corresponding to the plurality of groups along the column direction, respectively, for transmitting a column selection instruction to the corresponding gate transistor group. At least one column selection line provided corresponding to the shape dummy group among a plurality of column selection lines is electrically coupled to the plurality of source lines and to the fixed voltage. The

  Still another nonvolatile memory device according to the present invention includes a memory cell array having a plurality of memory cells and a plurality of dummy memory cells arranged in a matrix and executing nonvolatile data storage, and a plurality of bits in parallel during data reading. And a plurality of read circuits for executing data reading, and a plurality of data line pairs provided corresponding to the plurality of read circuits, respectively. The plurality of dummy memory cells are arranged so as to share the memory cell columns of the plurality of memory cells arranged in a matrix. A memory cell array includes a plurality of word lines provided corresponding to memory cell rows and dummy memory cell rows, a plurality of bit line pairs provided corresponding to two adjacent memory cell columns, and a memory cell A plurality of lines each provided corresponding to a row and a dummy memory cell row and electrically coupled to a fixed voltage and each electrically coupled to a corresponding bit line via a memory cell group of a corresponding memory cell column Source line. The plurality of bit line pairs are divided into a plurality of groups in which parallel data reading is executed at the time of data reading, corresponding to the plurality of data line pairs, respectively. A plurality of gate transistor groups that are provided corresponding to the plurality of groups, respectively, and that control electrical connection between the bit line pairs included in the corresponding group and the corresponding data line pair in response to the selection instruction; Prepare. At the time of data reading, one bit line of each of the bit line pairs is electrically coupled to a corresponding source line via a memory cell corresponding to a selected word line of the plurality of word lines to be stored data. A corresponding data read current is supplied. The other bit line complementary to the one bit line of each pair of bit lines is activated in response to the selection of the word line corresponding to the dummy memory cell row among the plurality of word lines during data reading. A reference current which is electrically coupled to the corresponding source line via the dummy memory cell and used for comparison with the data read current is supplied. An even number of the other data lines of the plurality of data line pairs are provided. Half of the dummy memory cells electrically coupled to each other data line are set to a high resistance state indicating one data level of the storage data of the memory cell, and the remaining half The dummy memory cell is set in a low resistance state indicating the other data level. The plurality of other data lines are electrically coupled to each other.

  The nonvolatile memory device according to the present invention further includes sub-source lines that electrically couple the source lines to each other. With this configuration, when data of a plurality of bits is read, all the potential rises of the source lines can be set to the same potential, so that the data read current is excessive in relation to the reference current based on the dummy memory cell. It is possible to suppress the increase or decrease and secure a certain data read margin and execute highly accurate data reading.

  Another nonvolatile memory device according to the present invention includes a shape dummy group that does not execute data reading, and at least one column selection line provided corresponding to the shape dummy group is electrically connected to a plurality of source lines. And is electrically coupled to a fixed voltage. Thus, with this configuration, when reading data of a plurality of bits, it is possible to set all the rises in the potentials of the source lines to the same potential, so that the data read current is relative to the reference current based on the dummy memory cell. Therefore, it is possible to prevent data from being excessively increased or decreased and to secure a constant data read margin and to perform highly accurate data reading. In addition, since the source lines are electrically coupled to each other using the column selection line, it is not necessary to apply a special design rule, which can be realized with a simple process.

  Still another nonvolatile memory device according to the present invention includes a plurality of read circuits for executing parallel data reading of a plurality of bits at the time of data reading, and a plurality of data line pairs provided corresponding to the plurality of read circuits, respectively. And the plurality of bit line pairs are divided into a plurality of groups corresponding to the plurality of data line pairs, respectively, in which parallel data reading is performed during the data reading, and each of the plurality of bit line pairs corresponds to the plurality of groups. A configuration further includes a plurality of gate transistor groups that are provided and that control electrical connection between the bit line pairs included in the corresponding group and the corresponding data line pair in response to the selection instruction. Along with this, it is possible to disperse bit line pairs that execute data reading in parallel to a plurality of groups, and accordingly, it is possible to disperse the path length of the current passing through the source line and flow to the source line. The entire length of the current path is prevented from becoming too long, so that an excessive rise at the position of a specific group of memory cells is suppressed, and a decrease in the data read margin is suppressed and a high-precision data read is performed. Can be executed.

  Embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

(Embodiment 1)
FIG. 1 is a schematic block diagram showing an overall configuration of an MRAM device 1 shown as a representative example of a nonvolatile memory device according to Embodiment 1 of the present invention.

  Referring to FIG. 1, an MRAM device 1 includes a control circuit 5 for controlling the entire operation of MRAM device 1 in response to a control signal CMD, and a memory array including MTJ memory cells MC arranged in a matrix. 10.

  Here, the rows and columns of the plurality of memory cells MC arranged in each matrix of the memory array 10 are also referred to as memory cell rows and memory cell columns, respectively.

  The MRAM device 1 also includes a row decoder 20, a column decoder 25, and an input / output control circuit 30.

  The row decoder 20 selectively performs row selection in the memory array 10 to be accessed based on the row address RA included in the address signal ADD. The column decoder 25 selectively performs column selection of the memory array 10 to be accessed based on the column address CA included in the address signal ADD.

  The input / output control circuit 30 controls input / output of data such as input data DIN, output data DOUT, etc., and transmits it to the internal circuit or outputs it to the outside in response to an instruction from the control circuit 5.

  In the following, the binary high voltage state and low voltage state in the signal, signal line, data level, etc. are also referred to as “H” level and “L” level, respectively.

  In this example, a single memory cell MC is typically shown in memory array 10 and corresponds to word line WL, digit line DL and source line SL, and a memory cell column provided corresponding to the memory cell row. The bit lines BL provided are typically shown one by one.

Here, the circuit configuration of the memory cell MC will be described.
FIG. 2 is a schematic diagram showing a configuration of an MTJ memory cell MC (hereinafter also simply referred to as a memory cell MC) having a magnetic tunnel junction.

  Referring to FIG. 2, memory cell MC includes a tunnel magnetoresistive element TMR whose electrical resistance changes according to the data level of magnetically written storage data, and access transistor ATR. Access transistor ATR is connected in series with tunneling magneto-resistance element TMR between bit line BL and ground voltage GND. Typically, a field effect transistor formed on a semiconductor substrate is applied as access transistor ATR.

  For memory cell MC, there are provided bit line BL and digit line DL for flowing data write currents in different directions at the time of data writing, and word line RWL activated at the time of data reading. In data reading, tunnel magnetoresistive element TMR is electrically coupled between ground voltage GND and bit line BL in response to turn-on of access transistor ATR.

Here, the configuration of the MTJ memory cell and the data storage principle will be described.
FIG. 3 is a conceptual diagram for explaining the structure and data storage principle of the MTJ memory cell.

  Referring to FIG. 3, tunneling magneto-resistance element TMR corresponds to a ferromagnetic layer (hereinafter, also simply referred to as “fixed magnetization layer”) FL having a fixed fixed magnetization direction and an externally applied magnetic field. And a ferromagnetic layer (hereinafter, also simply referred to as “free magnetic layer”) VL that can be magnetized in the direction. A tunnel barrier (tunnel film) TB formed of an insulator film is provided between the fixed magnetic layer FL and the free magnetic layer VL. Free magnetic layer VL is magnetized in the same direction as fixed magnetic layer FL or in the opposite direction to fixed magnetic layer FL according to the level of stored data to be written. A magnetic tunnel junction is formed by these fixed magnetic layer FL, tunnel barrier TB, and free magnetic layer VL.

  The electric resistance of tunneling magneto-resistance element TMR changes according to the relative relationship between the magnetization directions of fixed magnetic layer FL and free magnetic layer VL. Specifically, the electric resistance of tunneling magneto-resistance element TMR becomes the minimum value Rmin when the magnetization direction of fixed magnetic layer FL and the magnetization direction of free magnetic layer VL are the same (parallel), and the magnetization directions of both are The maximum value Rmax is obtained in the opposite (antiparallel) direction.

  In data writing, word line RWL is inactivated and access transistor ATR is turned off. In this state, the data write current for magnetizing free magnetic layer VL flows in the direction corresponding to the level of the write data in each of bit line BL and digit line DL.

  FIG. 4 is a conceptual diagram showing the relationship between the supply of the data write current to the MTJ memory cell and the magnetization direction of the tunnel magnetoresistive element.

  Referring to FIG. 4, the horizontal axis H (EA) represents a magnetic field applied in the easy axis (EA) direction in free magnetic layer VL in tunneling magneto-resistance element TMR. On the other hand, the vertical axis H (HA) indicates a magnetic field that acts in the hard magnetization axis (HA) direction in the free magnetic layer VL. Magnetic fields H (EA) and H (HA) respectively correspond to one of two magnetic fields generated by currents flowing through bit line BL and digit line DL, respectively.

  In the MTJ memory cell, the fixed magnetization direction of the fixed magnetization layer FL is along the easy axis of the free magnetization layer VL, and the free magnetization layer VL extends in the easy axis direction according to the level of stored data. Along this direction, the magnetization is magnetized in a direction parallel or antiparallel (opposite) to the fixed magnetization layer FL. The MTJ memory cell can store 1-bit data corresponding to the two magnetization directions of the free magnetic layer VL.

  The magnetization direction of the free magnetic layer VL can be newly rewritten only when the sum of the applied magnetic fields H (EA) and H (HA) reaches a region outside the asteroid characteristic line shown in FIG. it can. That is, when the applied data write magnetic field has a strength corresponding to the region inside the asteroid characteristic line, the magnetization direction of the free magnetic layer VL does not change.

  As indicated by the asteroid characteristic line, by applying a magnetic field in the hard axis direction to the free magnetic layer VL, the magnetization threshold required to change the magnetization direction along the easy axis is lowered. be able to. As shown in FIG. 4, the operating point at the time of data writing is that the data stored in the MTJ memory cell, that is, the tunnel magnetoresistance when a predetermined data write current is passed through both the digit line DL and the bit line BL. It is designed so that the magnetization direction of element TMR can be rewritten.

At the operating point illustrated in FIG. 4, the data write magnetic field in the easy axis direction is designed so that its strength is H _WR in the MTJ memory cell that is the data write target. That is, the value of the data write current that flows through bit line BL or digit line DL is designed so that this data write magnetic field _HWR is obtained. Generally, data write magnetic field H _WR is the switching magnetic field H _SW necessary for switching the magnetization direction is indicated by the sum of the margin [Delta] H. That is, H _WR = H _SW + ΔH.

  The magnetization direction once written in tunneling magneto-resistance element TMR, that is, data stored in the MTJ memory cell is held in a nonvolatile manner until new data writing is executed. Strictly speaking, the electric resistance of each memory cell is the sum of the tunnel magnetoresistive element TMR, the on-resistance of the access transistor ATR, and other parasitic resistances. The resistance other than the tunnel magnetoresistive element TMR depends on the stored data. In the following, the electric resistances of the two types of normal memory cells corresponding to the stored data are also represented by Rmax and Rmin, and the difference between them is represented by ΔR (that is, ΔR = Rmax−Rmin). And

  In the present invention, the digit line DL and the like used for the data write operation are not shown in order to mainly explain the data read operation.

  FIG. 5 is a diagram illustrating memory array 10 and its peripheral circuits according to the first embodiment of the present invention.

  Referring to FIG. 5, memory array 10 includes memory cells MC arranged in a matrix.

  In addition, it includes a plurality of bit lines BL provided corresponding to the memory cell columns, a plurality of word lines WL and a plurality of source lines SL provided corresponding to the memory cell rows, respectively.

  Bit lines BL are provided along the column direction, and word lines WL and source lines SL are provided along the row direction.

  In addition, the source line SL is configured so that one source line SL is provided corresponding to two adjacent memory cell rows and is shared by the memory cell rows, and both end sides of the source line SL are fixed. Electrically coupled to voltage VSS.

  Memory array 10 includes a plurality of dummy memory cells DMC for generating a reference current during data reading, and the plurality of dummy memory cells DMC are provided so as to share a memory cell column with normal memory cells. .

  In this example, two dummy word lines RWLe and RWLo are provided corresponding to dummy memory cell rows arranged so as to share a memory cell column.

  The plurality of bit lines BL form a bit line pair BLP with two bit lines BL and / BL adjacent to each other. In this example, four bit line pairs BLP0 to BLP3 are shown. Bit line pair BLP0 includes bit lines BL0 and / BL0.

Next, the peripheral circuit will be described.
In this example, a configuration capable of parallel 4-bit data reading will be described.

  Specifically, four sense amplifiers SA0 to SA3 are provided, and a data line pair LIP is provided corresponding to each sense amplifier SA. Specifically, a data line pair LIP0 is provided corresponding to the sense amplifier SA0, a data line pair LIP1 is provided corresponding to the sense amplifier SA1, and a data line pair LIP2 is provided corresponding to the sense amplifier SA2. A data line pair LIP3 is provided corresponding to sense amplifier SA3. Data line pair LIP0 includes a data line LIO0 and a complementary data line / LIO0. Data line pair LIP1 includes a data line LIO1 and a complementary data line / LIO1. Data line pair LIP2 includes a data line LIO2 and a complementary data line / LIO2. Data line pair LIP3 includes data line LIO3 and complementary data line / LIO3.

  One side and the other side of the input node of sense amplifier SA are electrically coupled to data line pair LIP through switching control circuit 15. The switching control circuit 15 switches the connection between one side of the input node of the sense amplifier SA and the data line LIO to the data line / LIO in response to the input of the switching control signal CT. Similarly, the connection between the other side of the input node of the sense amplifier SA and the data line / LIO is switched to the data line LIO. Further, it is assumed that the other side of the input node of each sense amplifier SA is electrically coupled to each other.

  Gate transistors GT and / GT are provided for electrically coupling the bit lines BL and / BL to the data lines LIO and / LIO, respectively. Specifically, gate transistors GT0 and / GT0 are provided corresponding to the bit lines BL0 and BL0. Further, gate transistors GT1, / GT1 are provided corresponding to the bit lines BL1, / BL1, respectively. In addition, gate transistors GT2 and / GT2 are provided corresponding to the bit lines BL2 and / BL2. Further, gate transistors GT3 and / GT3 are provided corresponding to the bit lines BL3 and / BL3.

  A plurality of column selection lines CSL are provided corresponding to the plurality of bit line groups. In this configuration, 4-bit data reading is executed, and one of a plurality of column selection lines CSL is selected and activated by column decoder 25 in accordance with column address CA, and corresponding bit line pair BLP Data line pair LIP is electrically coupled.

  In this example, four bit line pairs BLP0 to BLP3 form a bit line group BLG0, which is selected in accordance with activation of the column selection line CSL0 and electrically coupled to the data line pairs LIP0 to LIP3, respectively. . Note that the data line pairs LIP0 to LIP3 constitute a data line pair group LIOG.

  Specifically, gate transistor GT0 is provided between bit line BL0 and data line LIO0, and its gate is electrically coupled to column select line CSL0. Gate transistor / GT0 is provided between bit line / BL0 and data line / LIO0, and its gate is electrically coupled to column select line CSL0. Gate transistor GT1 is provided between bit line BL1 and data line LIO1, and its gate is electrically coupled to column select line CSL0. Gate transistor / GT1 is provided between bit line / BL1 and data line / LIO1, and its gate is electrically coupled to column select line CSL0. Gate transistor GT2 is provided between bit line BL2 and data line LIO2, and its gate is electrically coupled to column select line CSL0. Gate transistor / GT2 is provided between bit line / BL2 and data line / LIO2, and its gate is electrically coupled to column select line CSL0. Gate transistor GT3 is provided between bit line BL3 and data line LIO3, and its gate is electrically coupled to column select line CSL0. Gate transistor / GT3 is provided between bit line / BL3 and data line / LIO3, and its gate is electrically coupled to column select line CSL0. A set of gate transistors for controlling the electrical connection between the plurality of data line pairs LIP and the bit line pairs BLP by the gate transistors GT0, / GT0, GT1, / GT1, GT2, / GT2, GT3, / GT3. A group is composed. Although not shown, other sets of gate transistor groups are configured for other bit line pairs according to the same method.

  Although not shown, a bit line group BLG1 is formed by bit line pairs BLP4 to BLP7, which are selected in accordance with activation of column selection line CSL1 and are electrically coupled to data line pairs LIP0 to LIP3, respectively. Hereinafter, it is assumed that a plurality of bit line pairs BLP and a plurality of data line pairs LIP are electrically coupled according to the same method.

  Here, data reading according to the first embodiment of the present invention will be described. Here, the case where the bit line pairs BLP0 to BLP3 are selected will be described.

First, a case where the memory cell MC0 of the bit line pair BLP0 is selected will be described.
At the time of data reading, if bit line pair BLP0-BLP3 is selected, column select line CSL0 is activated in response to an instruction from column decoder 25. Accordingly, gate transistors GT0 and / GT0 are turned on, and bit lines BL0 and / BL0 are electrically coupled to data lines LIO0 and / LIO0, respectively, to form a current path. Further, when the bit line BL0 is selected, the switching control signal CT is set to the “L” level. In this case, it is assumed that switching control circuit 15 does not execute the switching operation, and data lines LIO0 and / LIO0 are electrically coupled to one side and the other side of the input node of sense amplifier SA0, respectively. Sense amplifier SA0 is electrically coupled to power supply voltage VDD and supplied with a data read current.

  Next, when the word line WL0 corresponding to the memory cell MC0 is activated, the internal access transistor is turned on, so that the source line SL and the bit line BL0 electrically coupled to the fixed voltage VSS are electrically connected. Combined.

  Accordingly, a current path is formed between sense amplifier SA0 and source line VSS, and a data read current based on resistance values (Rmax, Rmin) corresponding to storage data of selected memory cell MC0 is applied to data lines LIO0 and LIO0. It flows through the bit line BL0.

  Similarly, when attention is paid to the bit line pair BLP1 to BLP3, the access transistors of the memory cells MC1 to MC3 corresponding to the selected word line WL0 are turned on, and the sense amplifiers SA1 to SA3 are connected to the sense amplifiers SA1 to SA3 via the selected memory cell. Since a current path is formed between the fixed voltage VSS and the source line SL electrically coupled, a data read current corresponding to stored data flows. For example, in the case of sense amplifier SA1, a current flows from data line LIO1 to bit line BL1 to memory cell MC1 to source line SL. Similarly, in the sense amplifier SA2, a current flows from the data line LIO2 to the bit line BL2 to the memory cell MC2 to the source line SL. In the case of the sense amplifier SA3, a current flows from the data line LIO3 to the bit line BL3 to the memory cell MC3 to the source line SL.

Next, reference current supply will be described.
As described above, when the bit line pair BLP0 to BLP3 is selected, the column selection line CSL0 is activated, so that the gate transistors GT0, / GT0, GT1, / GT1GT2, / GT2, GT3, / GT3 Are all turned on. Accordingly, paying attention to complementary data lines / LIO, complementary data lines / LIO0 to / LIO3 are electrically coupled to complementary bit lines / BL0 to / BL3, respectively.

  When bit line BL0 is selected and selected memory cell MC and bit line BL0 are electrically coupled, complementary bit line / BL0 and dummy memory cell / DMC0 are electrically coupled.

  Specifically, the word line RWLe is activated. Here, the word lines RWLo and RWLe are word lines provided corresponding to memory cell rows formed by a plurality of dummy memory cells arranged so as to share a memory cell column. Specifically, the word line RWLo corresponds to a memory cell row formed by dummy memory cells (for example, dummy memory cells DMC0 to DMC3) arranged so as to share the memory cell column of the normal bit line BL. Provided. Word line RWLe corresponds to a memory cell row formed by dummy memory cells (for example, dummy memory cells / DMC0 to / DMC3) arranged so as to share a memory cell column of complementary bit lines / BL. Provided.

  As the word line RWLe is activated, the access transistors of the dummy memory cells / DMC0 to / DMC3 are activated, and the source line SL and the bit lines / BL0 to / BL3 electrically coupled to the fixed voltage VSS are electrically connected. Combined.

  Accordingly, a current path is formed between each sense amplifier SA and source line VSS for dummy memory cell DMC in the same manner as described above, and data reading based on the resistance values of dummy memory cells / DMC0 to / DMC3 is performed. A current flows through complementary data line / LIO and bit line / BL. Here, it is assumed that dummy memory cells / DMC0 to / DMC3 are set to two high resistance states (Rmax) and two low resistance states (Rmin).

  Then, since the other end sides of the input nodes of sense amplifiers SA0 to SA3 are electrically coupled to each other, dummy memory cells / DMC0 to / DMC3 are viewed from the other end side of the input nodes of sense amplifiers SA0 to SA3. The current based on the combined resistance of the dummy memory cells / DMC0 to / DMC3 is supplied from the other end side of the input node of each sense amplifier SA.

  The combined resistance of the dummy memory cells / DMC0 to / DMC3 is (2Rmax + 2Rmin) / 4 = (Rmax + Rmin) / 2 (= Rmid). That is, the reference current based on the intermediate resistance value Rmid between the high resistance value (Rmax) and the low resistance value (Rmin) of the memory cell is supplied to the other end side of the input node of each sense amplifier SA.

  In each sense amplifier SA, the data read current based on the resistance value of memory cell MC electrically coupled to one side of the input node and the combined resistance value of a plurality of dummy memory cells electrically coupled to the other side It is possible to perform data reading by amplifying the current difference by comparing with a reference current based on. That is, parallel 4-bit data reading is possible.

  Note that half of the plurality of dummy memory cells are set to a high resistance value (Rmax), the other half are set to a low resistance value (Rmin), and the other end sides of the input nodes of the plurality of sense amplifiers SA are electrically connected to each other. The combined resistance viewed from the sense amplifier side is set to the intermediate resistance value Rmid, and it is not necessary to adjust and set the resistance value of each dummy memory cell DMC to the intermediate resistance value Rmid. This makes it possible to supply a reference current that is an intermediate current. In addition, since the same reference current is supplied from each sense amplifier SA with this configuration, it is possible to reduce the variation in the reference current due to the variation in the resistance value of the dummy memory cell, and the reference to be compared for data reading. It becomes possible to increase the accuracy of the current.

  In the above example, the case where the memory cell of the bit line BL is selected has been described. However, when the memory cell of the complementary bit line / BL is selected, the switching control signal CT is set to the “H” level. After setting, the switching control circuit 15 executes switching control. Thus, one end side of the sense amplifier SA is always electrically coupled to the selected memory cell, and the other end side is always electrically coupled to the dummy memory cell. Reading is possible.

Next, the floating of the source line based on the influence of the parasitic resistance of the source line will be considered.
FIG. 6 is a diagram for explaining the influence of the parasitic resistance of the source line.

  Referring to FIG. 6A, here, a relationship between a selected memory cell and a source line when the above-described data reading is executed will be described.

  As shown here, when the word line WL is activated and the access transistor ATR is turned on, each of the bit lines BL0 to BL3 corresponding to the selected memory cell and the source line SL are electrically connected as described above. In combination, data read current Icell flows in parallel.

  Since the source line SL is formed using a diffusion layer having a relatively high resistance value, which will be described later, it has a parasitic resistance. For example, in the case of the parasitic resistance Rs1, considering the floating due to the parasitic resistance of the source line SL electrically coupled to the selected memory cell, the voltage Vs1 of the source line on the memory cell side is 4 × Icell × Rs1. It becomes. In particular, as the number of bits for executing parallel data reading increases, the voltage Vs1 of the source line on the memory cell side also increases, and the floating occurs.

  Referring to FIG. 6B, here, a relationship between the dummy memory cell and the source line SL when the above-described data reading is executed is described. For example, when the parasitic resistance Rs1 is set, considering the floating due to the parasitic resistance of the source line SL electrically coupled to the dummy memory cell, the voltage Vref1 of the source line on the dummy memory cell side is (2 × Imax + 2 × Imin). ) × Rs1 (= 4 × Imid × Rs1).

  FIG. 7 is a diagram for explaining the relationship of the data read margin based on the rising of the source line.

  If the selected memory cell MC is in two high resistance states (Rmax) and two low resistance states (Rmin), that is, in the same condition as the dummy memory cell DMC, the memory cell side There is no difference between the rising of the source line SL and the rising of the source line SL on the dummy memory cell side.

  Therefore, in this case, it is considered that there is no particular change in the relative relationship with the reference current Imid which is an intermediate current.

  On the other hand, when the selected memory cell MC has four high resistance states (Rmax), the data read current Icell = Imin. Therefore, the voltage Vs1 of the source line on the memory cell side is Imin × 4 × Rs1 (Vs1 (min)), and it can be said that the floating is small compared to the floating of the source line SL on the dummy memory cell side. On the contrary, the data read current Imin increases because the voltage applied to both ends of the memory cell MC becomes larger than that of the dummy memory cell due to the small rise. As a result, as shown in FIG. 7, the data read margin is reduced in the relative relationship with the reference current.

  On the other hand, when the selected memory cell MC is four low resistance states (Rmin), the data read current Icell = Imax. Therefore, the voltage Vs1 of the source line on the memory cell side is Imax × 4 × Rs1 (Vs1 (max)), and it can be said that the floating is larger than the floating of the source line SL on the dummy memory cell side. On the other hand, since the floating is large, the voltage applied to both ends of the memory cell MC becomes smaller than that of the dummy memory cell, so that the data read current Imax is reduced. As a result, as shown in FIG. 7, the data read margin is reduced in the relative relationship with the reference current.

  When these relationships are arranged, the minimum floating voltage Vs1 (min) <Vref1 <Vs1 (max) is obtained.

  Therefore, in the first embodiment of the present invention, as shown in FIG. 5, a sub-source line SLP which is newly electrically coupled with a fixed voltage is provided corresponding to the memory cell column, and along the column direction. They are arranged and intersect each source line provided along the row direction and are electrically coupled to each other.

  With this configuration, the rise of the potential of the source line SL on the memory cell side and the rise of the potential of the source line SL on the dummy memory cell side are set to the same potential and equal by the sub-source line SLP. That is, since the same rise occurs, it is possible to secure a constant data read margin by suppressing an excessive increase or decrease in the data read current in a relative relationship with the reference current. As a result, highly accurate data reading can be executed.

FIG. 8 is a diagram illustrating a wiring structure of memory cell MC according to the first embodiment of the present invention.
Referring to FIG. 8A, here, a memory cell MC and a bit line BL, a word line WL, a digit line DL, a source line SL, and a column selection line CSL are shown as signal wirings.

  Specifically, the access transistor ATR formed on the P-type semiconductor substrate Psub has source / drain regions 102a and 102b which are N-type regions, and a gate region 109.

  The gate region of access transistor ATR is formed as polysilicon gate 109 in the same wiring layer as word line WL0 from the viewpoint of increasing the degree of integration.

  The source / drain regions 102a and 102b are diffusion wiring layers, and in this example, the source / drain region 102b is provided as a source line SL. As described above, the source line SL is also provided as a shared wiring for adjacent memory cell rows. Here, a word line WL1 provided corresponding to an adjacent memory cell row is shown, and a configuration in which the source / drain regions are shared is shown.

  Source / drain region 102a is coupled to via 102 provided in the first metal wiring layer via contact hole 101. Via 102 is provided in contact hole 103 and via 104 provided in the second metal wiring layer and contact. The hole 105 is electrically coupled to the upper strap ST. Tunneling magneto-resistance element TMR is electrically coupled via a contact hole 106 between strap ST and bit line BL formed in third metal interconnection layer 100.

  Further, the signal line 111 is provided in the second metal wiring layer, and is formed as a digit line provided below the tunnel magnetoresistive element TMR. By supplying a data write current to this digit line, the magnetization direction of tunneling magneto-resistance element TMR can be changed by the write magnetic field described above.

  The first metal wiring layer is provided with a signal line 108, which is formed as the column selection line CSL described above. The column selection line CSL is provided along the column direction.

  FIG. 8B is a diagram illustrating a layout (plan view) of the wiring structure of memory cell MC according to the first embodiment of the present invention as viewed from above.

  Referring to FIG. 8B, the upper metal wiring layer (bit line formed in the third metal wiring layer) above tunnel magnetic resistance element TMR is omitted here. Strap ST of tunneling magneto-resistance element TMR is electrically coupled to the source / drain region of access transistor ATR through contact holes 101, 103, 105 and vias 102, 104. The source line SL is formed using the source / drain region 102b of the access transistor ATR which is a diffusion layer. Between the adjacent memory cell columns, the column selection line CSL is provided along the column direction using the first metal wiring layer.

  FIG. 8C illustrates a wiring structure of sub-source line SLP according to the first embodiment of the present invention.

  As shown in FIG. 8C, here, the sub-source line SLP is provided in the same metal wiring layer as the column selection line CSL, and is formed in the lower source / drain region 102b via the contact hole 112. The source line SL is electrically coupled.

  In this respect, since the column selection line CSL is provided corresponding to a plurality of memory cell columns, the signal line serving as the sub-source line SLP is made the same as the column selection line using the first metal wiring layer. Thus, it can be easily formed between the memory cell columns along the column direction. Note that since the metal wiring layer is in a low resistance state unlike the diffusion layer, the parasitic resistance is almost negligible and can be easily electrically coupled to the source line SL using the contact hole 112. Therefore, the value of the parasitic resistance can be reduced by supplying the data read current through the sub-source line SLP electrically coupled to the fixed voltage VSS. In this example, the configuration in which one sub-source line SLP is provided has been described. However, the present invention is not limited to this, and a configuration in which a plurality of sub-source lines are provided and electrically coupled to each source line SL is also possible. It is possible as well.

(Modification 1 of Embodiment 1)
FIG. 9 is a diagram illustrating a memory array and its peripheral circuits according to the first modification of the first embodiment of the present invention.

  Referring to FIG. 9, the memory array according to the first modification of the first embodiment of the present invention includes a plurality of memory mats. Here, as an example, two memory mats MA0 and MA1 are provided.

  Each of the memory mats MA0 and MA1 has a memory cell MC integrated and arranged in a matrix and a plurality of dummy memory cells MC provided as a comparison reference of the memory cell MC. A plurality of dummy cells DMC are provided one by one so as to share a memory cell column. With this configuration, dummy memory cells can be efficiently arranged and the area of the memory array can be reduced.

  In memory mat MA0, a plurality of word lines WLi (i: a natural number including 0) are provided corresponding to each memory cell row. As an example, in this example, word lines WL0 and WL provided corresponding to the memory cell MC and a word line DWL provided corresponding to a dummy memory cell row composed of a plurality of dummy memory cells DMC are shown. Has been. A plurality of source lines SL are provided corresponding to the memory cell rows, respectively. A plurality of bit lines BL are provided corresponding to the memory cell columns. In this example, bit lines BL0 to BL3 are shown as an example.

  In memory mat MA1, a plurality of word lines / WLi are provided corresponding to the memory cell rows, respectively. As an example, in this example, a word line / WLi provided corresponding to the memory cell MC and a word line / DWL provided corresponding to a dummy memory cell row constituted by a plurality of dummy memory cells DMC are shown. Has been. A plurality of source lines / SL are provided corresponding to the memory cell rows, respectively. In addition, a plurality of bit lines / BL having a complementary relationship with bit lines BL provided corresponding to the memory cell columns in the same column as memory mat MA0 are provided. In this example, complementary bit lines / BL0 to / BL3 of bit lines BL0 to BL3 are shown as an example.

  Bit lines BL and / BL form a bit line pair BLP and are electrically coupled to data line pair LIP through gate transistors GS and / GS.

  Specifically, a gate transistor GS0 is provided corresponding to the bit line BL0. A gate transistor / GS0 is provided corresponding to bit line / BL0. Similarly, gate transistors GS1, / GS1 are provided corresponding to bit lines BL1, / BL1, gate transistors GS2, / GS2 are provided corresponding to bit lines BL2, / BL2, and bit lines BL3, / BL3 are provided. Gate transistors GS3 and / GS3 are provided corresponding to the above.

Here, a configuration for executing 4-bit parallel data reading will be described.
A data line group LIOG provided in common corresponding to memory mats MA0 and MA1 is provided. Data line group LIOG includes four data line pairs LIP. Data line pair LIP0 includes data lines LIO0 and / LIO0. Data line LIO0 is electrically coupled to bit line BL0 through gate transistor GS0. Data line / LIO0 is electrically coupled to bit line / BL0 through gate transistor / GS0. Similarly, data lines LIO1, / LIO1 are electrically coupled to bit lines BL1, / BL1 through gate transistors GS1, / GS1. Data lines LIO2, / LIO2 are electrically coupled to bit lines BL2, / BL2 via gate transistors GS2, / GS2. Data lines LIO3 and / LIO3 are electrically coupled to bit lines BL3 and / BL3 through gate transistors GS3 and / GS3.

  In this example, column selection lines CSL are provided corresponding to the four memory cell columns of memory mats MA0 and MA1. Here, column select line CSL0 is shown, and is electrically coupled to the gates of gate transistors GS0-GS3, / GS0- / GS3 provided corresponding to bit lines BL0-BL3, / BL0- / BL3, respectively. The case is shown. Although not shown, the bit lines BL4 to BL7, / BL4 to / BL7 have the same configuration as the bit lines BL0 to BL3, / BL0 to / BL3, and the column selection line CSL1 is provided according to the same method. Similarly, in this example, the case where the column selection line CSLn is provided is shown in this example.

Here, data reading according to the first modification of the first embodiment of the present invention will be described.
Here, for example, a case where column selection line CSL0 is activated will be described. When column select line CSL0 is activated, all of gate transistors GS0, / GS0, GS1, / GS1, GS2, / GS2, GS3, / GS3 are activated. A set of gate transistors for controlling the electrical connection between the plurality of data line pairs LIP and the bit line pair BLP by the gate transistors GS0, / GS0, GS1, / GS1, GS2, / GS2, GS3, / GS3. A group is formed. The gate transistor group (GS0, GS1, GS2, GS3) on the memory mat MA0 side constitutes a gate transistor unit that controls electrical connection between the plurality of bit lines BL and the data lines LIO. The gate transistor group (/ GS0, / GS1, / GS2, / GS3) on the memory mat MA1 side is a gate for controlling the electrical connection between the plurality of complementary bit lines / BL and the complementary data lines / LIO. A transistor unit is configured.

  Although not shown, other sets of gate transistor groups are configured for other bit line pairs according to the same method.

  Therefore, data lines LIO0 and / LIO0 are electrically coupled to bit lines BL0 and / BL0. Similarly, data lines LIO1, / LIO1 are electrically coupled to bit lines BL1, / BL1. Data lines LIO2, / LIO2 are electrically coupled to bit lines BL2, / BL2. Data lines LIO3, / LIO3 are electrically coupled to bit lines BL3, / BL3.

  When the memory mat MA0 is selected, the memory mat MA0 selects the memory cell MC, and the memory mat MA1 selects the dummy memory cell / DMC.

  Specifically, when the word line WL0 is activated in the memory mat MA0, the access transistor of the memory cell corresponding to the word line WL0 is turned on, and the selected memory cell MC is electrically connected to the bit lines BL0 to BL3. Combined.

  On the other hand, memory mat MA1 activates word line / DWL. Accordingly, bit lines / BL0 to / BL3 are electrically coupled to dummy memory cell / DMC. In this case, it is assumed that the switching control signal CT is set to the “L” level.

  Therefore, as described above, data read current is supplied from sense amplifiers SA0-SA3 through data line LIO and bit line BL, and a reference current which is an intermediate current is supplied through data line / LIO and bit line / BL. Therefore, 4-bit parallel data reading can be executed based on the current difference.

  On the other hand, when memory mat MA1 is selected, memory mat MA1 selects memory cell / MC, and memory mat MA0 selects dummy memory cell DMC. In this case, the switching control signal CT is set to the “H” level.

  Thus, one end side of the sense amplifier SA is always electrically coupled to the selected memory cell, and the other end side is always electrically coupled to the dummy memory cell. Reading is possible.

  Also in the configuration of the first modification of the first embodiment of the present invention, as described above, the sub-source line SLQ that is newly electrically coupled to the fixed voltage corresponding to the memory cell column as shown in FIG. Provided along the column direction, and electrically coupled to each source line provided along the intersecting row direction.

  With this configuration, the rising of the potential of the source line SL on the memory cell side and the rising of the potential of the source line SL on the dummy memory cell side are set to the same potential and equal by the sub-source line SLQ. That is, since the same rise occurs, it is possible to secure a constant data read margin by suppressing an excessive increase or decrease in the data read current in a relative relationship with the reference current. As a result, highly accurate data reading can be executed.

  In addition, as described above, by forming the sub-source line SLQ using the first metal wiring layer that forms the column selection line CSL, it is possible to suppress the parasitic resistance with a simple configuration. In this example, the configuration in which one sub-source line SLQ is provided has been described. However, the present invention is not limited to this, and a configuration in which a plurality of sub-source lines are provided and electrically coupled to each source line SL is also possible. It is possible as well.

(Modification 2 of Embodiment 1)
In the first modification of the first embodiment described above, a sub-source line SLQ is newly provided and electrically coupled to each source line SL, thereby suppressing the rise of the potential of the source line and parasitic of the source line. The method for preventing the data read margin from being reduced based on the resistance has been described.

  In the second modification of the first embodiment of the present invention, a configuration for easily suppressing the floating of the source line SL without providing the sub-source line SLQ will be described.

  FIG. 10 is a conceptual diagram illustrating a memory array and its peripheral circuits according to the second modification of the first embodiment of the present invention.

  Referring to FIG. 10, the configuration according to the second modification of the first embodiment of the present invention is different from the configuration described in FIG. 9 in that sub-source line SLQ is deleted. Since the other points are the same, detailed description thereof will not be repeated.

  In the first modification of the first embodiment, the configuration in which the column selection line CSL is provided corresponding to the four memory cell column groups has been described. In this example, a configuration in which at least one of the column selection lines CSL0 to CSLn described above is used as a sub-source line will be described.

  Specifically, an arbitrary memory cell column group is provided as a shape dummy group, and the column selection line is used as a substitute for the sub-source line SLQ described above.

FIG. 11 is a diagram for explaining the dummy group DMG.
As shown in FIG. 11, all the memory cell columns corresponding to a certain column selection line CSL are formed into the shape dummy group DMG, and the source line SL provided corresponding to the column selection line CSLd and each memory cell row, respectively. Are electrically coupled to each other.

  With this configuration, it is not necessary to newly provide the sub-source line SLQ in another process, and the same effect as described above can be realized with a simple configuration. That is, when the memory cells constituting the memory cell array are integrated and arranged, the memory cells need only be integrated and arranged according to the repetition of the same pattern, and it is not necessary to apply special design rules and can be realized by a simple process. . Note that the memory cells in the shape dummy group have the same cell structure as other memory cells. However, since column select line CSLd is used as a sub-source line, memory cells belonging to these shape dummy groups are not accessed during data reading or data writing.

  FIG. 12 is a diagram illustrating a wiring structure of memory cell MC according to the second modification of the first embodiment of the present invention.

  FIG. 12A shows a cross-sectional structure substantially similar to the cross-sectional structure of the memory cell described with reference to FIG. In the configuration of this example, each source line SL is provided with one source line corresponding to the memory cell row, and is different in that it is not shared by the two memory cell rows. However, since the other points are the same, detailed description thereof will not be repeated.

  FIG. 12B shows a layout (plan view) substantially the same as that described with reference to FIG. As described above, one source line is provided corresponding to a memory cell row, and two adjacent memory cells in the same row are shown. Although this layout is different from the configuration of FIG. 8B in that the source line SL is not shared by adjacent memory cell rows, only the arrangement is different, and the connection relationship and the like are the same. Detailed description will not be repeated.

  12C, in the same manner as shown in FIG. 8C, the signal line 108 provided in the column direction and each source line SL are electrically coupled via the contact 112. It is shown. Here, the case where the column selection line CSLd is used as the sub-source line, instead of newly providing the sub-source line is shown.

  As described above, according to this configuration, it is not necessary to newly provide the sub-source line SLQ in a separate process, and a decrease in the data read margin can be suppressed with a simple configuration. As a result, highly accurate data reading can be executed.

(Embodiment 2)
In the above embodiment, the sub-source line is provided and electrically coupled to the source line provided corresponding to the memory cell row, thereby suppressing the parasitic resistance and suppressing the decrease in the data read margin. Explained.

  In the second embodiment, another method for suppressing a decrease in data read margin will be described.

  Specifically, the influence of the parasitic resistance is largely due to the wiring length of the source line. Therefore, the longer the current path flowing through the source line, the higher the parasitic resistance. When data reading is executed, depending on the position of a group of memory cells from which data is read, an excessive floating occurs with respect to the source line compared to the position of another group of memory cells due to the difference in the length of the current path. There is a possibility. As a result, the data read margin can be extremely reduced in a group of memory cells.

  In the second embodiment, when data reading of a plurality of bits is executed, the current path flowing through the source line at the time of data reading becomes too long, and it is excessive at the position of a specific group of memory cells as a whole. A method for suppressing a decrease in the data read margin so as not to lift will be described.

  FIG. 13 is a diagram illustrating a memory array and its peripheral circuits according to the second embodiment of the present invention.

  Referring to FIG. 13, here, in the memory array, memory cells MC are integrated and arranged according to the same system as described in FIG.

  Specifically, the complementary bit line pair and the data line pair are electrically coupled via the gate transistor.

  In this example, 4-bit parallel data reading is executed, but the difference from the configuration of FIG. 5 is that in the configuration of FIG. 5, in response to activation of one column selection line CSL. Although the configuration in which 4-bit parallel data reading is executed has been described, in this example, the memory array is divided into two block units BKa and BKb, and each block unit BKa and BKb has 2 bits each. Perform parallel data reading.

  Specifically, in the block unit BKa, a column selection line CSLa is provided corresponding to two bits, that is, four bit lines, and a plurality of column selection lines CSLa are set in response to a column selection instruction from the column decoder. One of them is selected and electrically coupled to data line pair LIO0 and LIO1. Then, 2-bit read data is output from sense amplifiers SA0 and SA1 according to the same method as described in FIG.

  In the block BKb, a column selection line CSLb is provided corresponding to every two bits, that is, four bit lines, and one column selection line CSLb is selected from a plurality of column selection lines CSLb in response to a column selection instruction from the column decoder. Is selected and electrically coupled to data line pair LIP2 and LIP3. Then, 2-bit read data is output from sense amplifiers SA2 and SA3 according to the same method as described above. Note that the source line SL is provided in common in the two block units BKa and BKb.

  In FIG. 13, in block units BKa and BKb, column selection lines CSL0a and CSL0b for executing 2-bit data reading in parallel are simultaneously selected to execute 2-bit data reading, respectively, 4-bit parallel data reading is executed.

  Similarly, the column selection lines CSL1a and CSL1b are simultaneously selected for the other column selection lines, and 4-bit parallel data reading is executed.

  That is, the above configuration is a configuration in which the memory array is divided into two regions (block units), and the bit line group selected at one time is also divided into two groups and data is read from each region.

  With this configuration, it is possible to disperse the bit line groups that perform data reading in parallel, and accordingly, it is possible to disperse the path length of the current passing through the source line SL. That is, when performing multi-bit data reading, the length of the current path flowing through each source line during data reading is dispersed so that the total length of the current path flowing through the source line does not become too long. Thus, it is possible to prevent an excessive lift from occurring at the position of a specific group of memory cells.

  Therefore, in the memory array, when data reading of any group of memory cells is executed, the bit line group for executing data reading is distributed in parallel, so that the position of a certain group of memory cells is determined. In this case, it is possible to suppress the occurrence of excessive floating and suppress the decrease in the data read margin. As a result, highly accurate data reading can be executed. Here, the configuration in which the source line SL is provided in common in the two block units BKa and BKb has been described, but a configuration in which a source line is provided for each block unit is also possible. By providing an independent source line for each block unit and making the node connected to the source line independent, the load on the source line at the time of parallel data reading is reduced, and the floating of the source line is prevented. Can do.

(Modification 1 of Embodiment 2)
In the above-described second embodiment, the configuration in which data is read out by 2 bits from each of the block units BKa and BKb by being divided into two block units BKa and BKb has been described. It is also possible to divide and execute 1-bit data reading from each area.

  FIG. 14 is a diagram illustrating a memory array and its peripheral circuits according to the first modification of the second embodiment of the present invention.

  Referring to FIG. 14, here, two memory mats MA0 # and MA1 # are provided as a memory array, and memory cells MC are arranged in an integrated manner in the same manner as described in FIG. Each memory mat MA0 #, MA1 # is divided into two block units. Specifically, memory mat MA0 # is divided into block units BK0 and BK1. Memory mat MA1 # is divided into block units BK00 and BK11.

Also in this example, 4-bit parallel data reading is executed.
A sense amplifier SA is provided corresponding to each block unit BK. Specifically, sense amplifiers SA0 and SA1 are provided corresponding to the block units BK0 and BK1, respectively. Sense amplifiers SA2 and SA3 are provided corresponding to the block units BK00 and BK11, respectively.

  Then, 1-bit data reading is executed in each block unit. Specifically, block unit BK0 is electrically coupled to data line pair LIP0, and 1-bit data is read from sense amplifier SA0. Block unit BK1 is electrically coupled to data line pair LIP1, and 1-bit data is read from sense amplifier SA1. Block unit BK00 is electrically coupled to data line pair LIP2, and 1-bit data is read from sense amplifier SA2. Block unit BK11 is electrically coupled to data line pair LIP3 to execute 1-bit data reading from sense amplifier SA3.

  In each block unit, a column selection line is provided corresponding to each bit line pair. For example, in this example, a case where column selection lines CSLa0 to CSLa4 are provided corresponding to the bit line pairs of the block unit BK0 is shown. Further, the case where column selection lines CSLb0 to CSLb4 are provided corresponding to the bit line pairs of the block unit BK1 is shown. Further, a case is shown in which column selection lines CSLa00 to CSLa44 are provided corresponding to the bit line pairs of the block unit BK00. Further, the case where column selection lines CSLb00 to CSLb44 are provided corresponding to the bit line pairs of the block unit BK11 is shown.

  Then, in response to a column selection instruction from the column decoder, one column selection line is selected from each block unit and is electrically coupled to the data line pair.

  Then, read data is output from each of the sense amplifiers SA0 to SA4 according to the same method as described in FIG.

  It is assumed that source line SL is provided in common in two block units BK0 and BK1 of memory mat MA0 #. It is assumed that the two block units BK00 and BK11 of the memory mat MA1 # are provided in common.

  That is, the above configuration is a configuration in which the memory mat is divided into two regions (block units), and the bit line group selected at one time is also divided into two groups and data is read from each region.

  With this configuration, it is possible to disperse the bit line groups that perform data reading in parallel, and accordingly, it is possible to disperse the path length of the current passing through the source line SL. That is, when data reading of a plurality of bits is executed, the length of the current path flowing through each source line is distributed during data reading so that the total length of the current path flowing through the source line does not become too long. It becomes possible to.

  Therefore, in the memory array, when data reading of any group of memory cells is executed, parasitic resistance is suppressed, and excessive floating is prevented from occurring at the position of a specific group of memory cells. A decrease in read margin can be suppressed. As a result, highly accurate data reading can be executed.

  Note that it is possible to further reduce the load on the source line when reading data in parallel by providing a source line independently for each block unit and making the node connected to the source line independent.

(Modification 2 of Embodiment 2)
FIG. 15 is a diagram illustrating a memory array and its peripheral circuits according to the second modification of the second embodiment of the present invention.

  Referring to FIG. 15, here, a case where two memory arrays 10a and 10b are provided as memory arrays along the row direction is shown. In each of the memory mats 10a and 10b, the memory cells MC are arranged in an integrated manner according to the same method as described in FIG.

  Specifically, the complementary bit line pair and the data line pair are electrically coupled via the gate transistor. Note that the sub-source line is not provided.

  In this example, 4-bit parallel data reading is executed, but the difference from the configuration of FIG. 5 is that in the configuration of FIG. 5, in response to activation of one column selection line CSL. Although the configuration in which 4-bit parallel data reading is executed has been described, in this example, two bits of parallel data reading are executed in each of the two memory arrays 10a and 10b.

  Specifically, in memory array 10a, data line pairs LIP0 and LIP1 are electrically coupled to bit line pairs. Then, 2-bit read data is output from sense amplifiers SA0 and SA1 according to the same method as described in FIG.

  Similarly, in memory array 10b, data line pairs LIP2 and LIP3 are electrically coupled to bit line pairs. Then, 2-bit read data is output from sense amplifiers SA2 and SA3 in accordance with the same method as described in FIG.

  Each memory array is divided into two block units as described with reference to FIG. Specifically, the memory array 10a is divided into two block units BKa0 and BKb0. The memory array 10b is divided into two block units BKa1 and BKb1.

  Then, data reading is executed according to the same method as described in FIG. In FIG. 13, the configuration in which data reading by 2 bits is executed in each block unit has been described. However, in this example, data reading by 1 bit is executed in each block unit.

  Specifically, in each block unit, one column selection line is provided corresponding to two bit lines, that is, one set of bit line pairs. Here, as an example, column selection lines CSLa0 to CSLa4 are provided corresponding to block unit BKa0. Further, column selection lines CSLb0 to CSLb4 are provided corresponding to the block unit BKb0. In addition, column selection lines CSLc0 to CSLc4 are provided corresponding to the block unit BKa1. In addition, column selection lines CSLd0 to CSLd4 are provided corresponding to the block unit BKb1.

  In other words, the above configuration executes 2-bit data reading from each of the two memory arrays, divides each memory array into two areas (block units), and executes data reading from the divided areas. It is the structure to do. Specifically, one of the column selection lines CSLa0 to CSLa4 of the block unit BKa0 is selected, and one of the column selection lines CSLb0 to CSLb4 of the block unit BKb0 is selected and the column of the block unit BKa1 is selected. One of selection lines CSLc0 to CSLc4 is selected, and one of column selection lines CSLd0 to CSLd4 of block unit BKb1 is selected to execute data reading.

  With this configuration, it is possible to further disperse the bit line groups that perform data reading in parallel, and accordingly, it is possible to disperse the path length of the current passing through the source line SL. That is, when data reading of a plurality of bits is executed, the length of the current path flowing through each source line is distributed during data reading so that the total length of the current path flowing through the source line does not become too long. It becomes possible to.

  Therefore, in the memory array, when data is read from any group of memory cells, excessive parasitic resistance is suppressed and excessive floating is prevented from occurring at the position of a specific group of memory cells. Therefore, it is possible to suppress a decrease in data read margin. As a result, highly accurate data reading can be executed.

  Note that it is possible to further reduce the load on the source line when reading data in parallel by providing a source line independently for each block unit and making the node connected to the source line independent.

  In the above embodiment, the MRAM memory cell using a general TMR element has been described as an example. However, the present invention is not limited to this and can be similarly applied to other nonvolatile memories.

  For example, the memory cell is not limited to the above-described data writing method, and a memory cell conforming to another data writing method such as a spin torque switching cell may be employed.

  Further, the memory cell of the current MRAM device employs a method of reversing the magnetization by causing a current to flow through a wiring (including a write word line) adjacent to the TMR element to generate a magnetic field. It is also possible to use a spin injection type memory cell that employs a method in which the magnetization of the TMR element is reversed by the current flowing into the TMR element. This spin injection type memory cell switches the magnetization of the free phase in a direction parallel or antiparallel to the stationary phase by changing the direction of current flow. In this respect, it is called a spin injection method in order to reverse the magnetization by the action of spin-polarized electrons in the current, and it is necessary to provide a write word line for the memory cell of the MRAM device. And a simple cell structure can be realized.

  Furthermore, not only the tunnel magnetoresistive element TMR but also a resistance variable memory element that rewrites memory cell data by applying a current (voltage), such as an RRAM (Resistance RAM) or a phase change memory element, such as an OUM (Ovonic Unified Memories). Is equally applicable.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

1 is a schematic block diagram showing an overall configuration of an MRAM device 1 shown as a representative example of a nonvolatile memory device according to a first embodiment of the present invention. FIG. 3 is a schematic diagram showing a configuration of an MTJ memory cell MC having a magnetic tunnel junction. It is a conceptual diagram explaining the structure and data storage principle of an MTJ memory cell. It is a conceptual diagram which shows the relationship between supply of the data write current to an MTJ memory cell, and the magnetization direction of a tunnel magnetoresistive element. 1 is a diagram illustrating memory array 10 and its peripheral circuits according to a first embodiment of the present invention. FIG. It is a figure explaining the influence of the parasitic resistance of a source line. It is a figure explaining the relationship of the data read margin based on the rising of a source line. It is a diagram illustrating a wiring structure of memory cell MC according to the first embodiment of the present invention. It is a figure explaining the memory array and its peripheral circuit according to the modification 1 of Embodiment 1 of this invention. It is a conceptual diagram explaining the memory array and its peripheral circuit according to the modification 2 of Embodiment 1 of this invention. It is a figure explaining the dummy group DMG. It is a figure explaining the wiring structure of memory cell MC according to the modification 2 of Embodiment 1 of this invention. It is a figure explaining the memory array and its peripheral circuit according to Embodiment 2 of this invention. It is a figure explaining the memory array and its peripheral circuit according to the modification 1 of Embodiment 2 of this invention. It is a figure explaining the memory array and its peripheral circuit according to the modification 2 of Embodiment 2 of this invention.

Explanation of symbols

  1 MRAM device 1, 5 control circuit, 10, 10a, 10b memory array, 15 switching control circuit, 20 row decoder, 25 column decoder, 30 input / output control circuit.

Claims (6)

A memory cell array having a plurality of memory cells and a plurality of dummy memory cells arranged in a matrix and executing nonvolatile data storage;
A plurality of readout circuits for performing parallel data readout of a plurality of bits at the time of data readout;
A plurality of data line pairs provided corresponding to the plurality of readout circuits, respectively.
The plurality of dummy memory cells are arranged to share a memory cell column of the plurality of memory cells arranged in a matrix,
The memory cell array includes:
A plurality of word lines provided corresponding to the memory cell rows, and
A plurality of bit lines respectively corresponding to the memory cell columns;
A plurality of source lines provided corresponding to each memory cell row and electrically coupled to a fixed voltage and each electrically coupled to a corresponding bit line via a memory cell group of a corresponding memory cell column Including
The plurality of bit lines are divided into a plurality of groups including a group of bit lines in which parallel data reading is performed at the time of data reading,
A plurality of gate transistors provided corresponding to the plurality of groups, respectively, and controlling electrical connection between the bit line groups included in the corresponding group and the plurality of data line pairs in response to a column selection instruction Further comprising a group,
At the time of data reading, one data line of each of the data line pairs is electrically coupled to a corresponding source line via a memory cell corresponding to a selected word line of the plurality of word lines to store stored data. A data read current according to
During the data reading, the other data line of each data line pair is electrically coupled to a corresponding source line via a dummy memory cell and supplied with a reference current used as a target for comparison with the data reading current. ,
The non-volatile memory device, wherein the memory cell array further includes sub-source lines provided so as to intersect with the plurality of source lines and electrically coupled to each other. The bit line group included in each group includes a plurality of bit line pairs each provided corresponding to the plurality of data line pairs, each of which is composed of two adjacent bit lines,
One data line of the corresponding data line pair at the time of data reading is electrically coupled to the corresponding memory cell via one bit line of the corresponding bit line pair, and the other data line of the corresponding data line pair The nonvolatile memory device according to claim 1, wherein the nonvolatile memory device is electrically coupled to the dummy memory cell via the other bit line of the corresponding bit line pair. Providing the first and second memory cell arrays provided along the column direction;
The plurality of bit lines of the first memory cell array are divided into a plurality of first groups including a bit line group in which parallel data reading is executed during the data reading,
The plurality of bit lines of the second memory cell array are divided into a plurality of second groups including a group of bit lines in which parallel data reading is executed during the data reading,
The plurality of gate transistor groups are:
Each of the plurality of first groups is provided corresponding to each of the plurality of first groups, and in response to a column selection instruction, each of the bit line groups included in the corresponding first group is electrically connected to the plurality of data line pairs. A plurality of first gate transistor units to be controlled;
Included in a corresponding second group that is provided corresponding to each of the plurality of second groups and forms the same column as the bit line group included in the first group selected in response to the column selection instruction A plurality of second gate transistor units for controlling electrical connection between the bit line group and the plurality of data line pairs,
At the time of data reading, one data line of each data line pair is electrically coupled to a corresponding memory cell via a bit line of a bit line group included in one of the selected first and second groups. ,
When the data is read, the other data line of each data line pair is electrically connected to the dummy memory cell via the bit line of the bit line group constituting the same column included in the other of the selected first and second groups. The non-volatile storage device according to claim 1, wherein the non-volatile storage device is coupled to each other. The other data line of the plurality of data line pairs is provided with an even number,
Half of the plurality of dummy memory cells electrically coupled to each other data line are set to a high resistance state indicating one data level of storage data of the memory cell, and the remaining Half of the dummy memory cells are set to a low resistance state indicating the other data level,
The nonvolatile memory device according to claim 1, wherein the plurality of other data lines are electrically coupled to each other. A memory cell array having a plurality of memory cells arranged in a matrix and executing nonvolatile data storage;
A plurality of readout circuits for performing parallel data readout of a plurality of bits at the time of data readout;
A plurality of data line pairs provided corresponding to the plurality of readout circuits, respectively.
The memory cell array includes:
A plurality of word lines provided corresponding to the memory cell rows, and
A plurality of bit lines respectively corresponding to the memory cell columns;
A plurality of source lines provided corresponding to each memory cell row and electrically coupled to a fixed voltage and each electrically coupled to a corresponding bit line via a memory cell group of a corresponding memory cell column Including
The plurality of bit lines are divided into a plurality of groups including a group of bit lines in which parallel data reading is performed at the time of data reading,
A plurality of gate transistors provided corresponding to the plurality of groups, respectively, and controlling electrical connection between the bit line groups included in the corresponding group and the plurality of data line pairs in response to a column selection instruction Further comprising a group,
At the time of data reading, one data line of each of the data line pairs is electrically coupled to a corresponding source line via a memory cell corresponding to a selected word line of the plurality of word lines to store stored data. A data read current according to
During the data reading, the other data line of each data line pair is electrically coupled to a corresponding source line via a dummy memory cell and supplied with a reference current used as a target for comparison with the data reading current. ,
At least one group of the plurality of groups constitutes a shape dummy group that does not perform the data reading,
A plurality of column selection lines provided corresponding to the plurality of groups along the column direction, respectively, for transmitting a column selection instruction to the corresponding gate transistor group;
At least one column selection line provided corresponding to the shape dummy group among a plurality of column selection lines is electrically coupled to the plurality of source lines and to the fixed voltage. A non-volatile storage device. A memory cell array having a plurality of memory cells and a plurality of dummy memory cells arranged in a matrix and executing nonvolatile data storage;
A plurality of readout circuits for performing parallel data readout of a plurality of bits at the time of data readout;
A plurality of data line pairs provided corresponding to the plurality of readout circuits, respectively.
The plurality of dummy memory cells are arranged to share a memory cell column of the plurality of memory cells arranged in a matrix,
The memory cell array includes:
A plurality of word lines provided corresponding to the memory cell rows and the dummy memory cell rows, and
A plurality of bit line pairs respectively provided corresponding to two adjacent memory cell columns;
Provided corresponding to each memory cell row and dummy memory cell row, and electrically coupled to a fixed voltage and each electrically coupled to a corresponding bit line via a memory cell group of a corresponding memory cell column. Including a plurality of source lines,
The plurality of bit line pairs are divided into a plurality of groups corresponding to the plurality of data line pairs, in which parallel data reading is performed during the data reading,
A plurality of gate transistor groups provided corresponding to the plurality of groups, each of which controls electrical connection between a bit line pair included in the corresponding group and a corresponding data line pair in response to a selection instruction; In addition,
At the time of data reading, one bit line of each of the bit line pairs is electrically coupled to a corresponding source line via a memory cell corresponding to a selected word line of the plurality of word lines to store stored data. A data read current according to
The other bit line complementary to the one bit line of each bit line pair is activated in response to selection of a word line corresponding to a dummy memory cell row among the plurality of word lines during the data reading. A reference current that is electrically coupled to a corresponding source line via a dummy memory cell and used as a target for comparison with the data read current is supplied;
The other data line of the plurality of data line pairs is provided with an even number,
Half of the plurality of dummy memory cells electrically coupled to each other data line are set to a high resistance state indicating one data level of storage data of the memory cell, and the remaining Half of the dummy memory cells are set to a low resistance state indicating the other data level,
The non-volatile memory device, wherein the plurality of other data lines are electrically coupled to each other.

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