JP2007158098A - Semiconductor device - Google Patents

Abstract

In a semiconductor device having a channel formation region with a stripe structure, a common contact hole for taking a source potential and a substrate potential in common can be miniaturized.
A channel forming region, an N ⁺ source region, an N ⁺ drain region, and a gate electrode having a stripe structure in which a planar shape forms a band shape are formed on a surface portion of an N well layer in a semiconductor substrate. The P ⁺ body contact region 14 is intermittently extended in the channel forming region 12 in the extending direction of the channel forming region 12, and the connection of the source electrode with the N ⁺ source region 13 is connected to the P ⁺ body contact region 14. This is performed between adjacent P ⁺ body contact regions 14 in the extending direction.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor device.

Patent Document 1 discloses a stripe-type LDMOS transistor. In paragraph [0002] in Patent Document 1, an N ⁺ source region and a P ⁺ body contact region are formed in a source cell with respect to a substrate potential, and the N ⁺ source region and the P ⁺ body contact region are connected to a common contact. A configuration in which a substrate potential is connected in common with the source by connecting to the source electrode through the hole is shown (see FIG. 21 of Patent Document 1).
Japanese Patent No. 3626293

However, the size of the contact hole for securing the electrical connection between the N ⁺ source region and the P ⁺ body contact region in the source cell is increased (the cell pitch is increased). As a result, the element becomes large. Further, the on-resistance increases due to an increase in the cell pitch.

  The present invention has been made paying attention to the above-described problems, and an object of the present invention is to reduce the size of a common contact hole for taking a common source potential and substrate potential in a semiconductor device having a channel formation region having a stripe structure. The purpose is to make it possible.

  In order to solve the above problems, in the invention according to claim 1, as shown in FIG. 9, the body contact region (14) is arranged in the channel forming region in the extending direction of the channel forming region (Y direction). The source electrode (18) is connected to the source region (13) between the adjacent body contact regions (14) in the extending direction (Y direction) of the body contact region (14). The gist is what we did.

  According to the first aspect of the present invention, as shown in FIG. 10, the body contact region (14) is continuously extended in the channel forming region in the extending direction (Y direction) of the channel forming region. Compared with the case where the source electrode (18) is connected to the source region (13) in the side surface portion of the body contact region (14), the source potential and the substrate potential in the semiconductor device having the channel formation region having the stripe structure are compared. The common contact hole (19) can be reduced in size, and the element size can be reduced.

  According to a second aspect of the present invention, in the semiconductor device according to the first aspect, in a direction perpendicular to the extending direction of the channel formation region, a line through which a contact hole for connecting a drain electrode to the drain region passes. By arranging a contact hole for connecting the source electrode to the source region and the body contact region, a current path flowing between the source and the drain due to a surge can be shortened. As a result, a decrease in ESD tolerance can be suppressed.

  According to a third aspect of the present invention, in the semiconductor device according to the first or second aspect, the semiconductor substrate is an SOI substrate configured by forming a semiconductor layer on a support substrate via a buried insulating film. In the semiconductor layer, the channel formation region, the source region, the body contact region, the drain region, the gate electrode, and the source electrode are formed in a region surrounded by the element isolation trench that reaches the buried insulating film. Since the trench is separated from other elements by the trench, it is possible to prevent other elements from being affected by heat generation.

DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, an embodiment of the invention will be described with reference to the drawings.
FIG. 1 is a plan view of the substrate surface portion of the semiconductor device according to the present embodiment. FIG. 2 is a longitudinal sectional view taken along the line AA of FIG. 1, and in particular, is a longitudinal sectional view mainly showing a source cell and a drain cell. FIG. 3 shows a longitudinal section taken along line BB in FIG.

  The semiconductor device in this embodiment is a composite IC, and a bipolar transistor and a MOS transistor are built in one chip. The MOS transistor is an LDMOS transistor having a stripe structure and an N-channel transistor.

As shown in FIGS. 2 and 3, in this embodiment, an N-type silicon layer 3 is formed as a semiconductor substrate 4 on a support substrate (silicon substrate) 1 via a buried oxide film 2 as a buried insulating film. The formed SOI substrate is used. The thickness of the silicon layer 3 in the semiconductor substrate (SOI substrate) 4 is 14 μm. An N ⁺ buried layer 5 is formed at the bottom of the N-type silicon layer 3.

  An inter-element isolation trench 6 reaching the buried oxide film 2 in the N-type silicon layer 3 is formed, and a region surrounded by the trench 6 is an LDMOS transistor formation region (island). That is, the element isolation trench 6 is formed in an annular shape, and the LDMOS transistor formation region (island) is partitioned. The width of the trench 6 is 2 μm. A silicon oxide film 7 is buried in the element isolation trench 6.

Similarly, a bipolar transistor (not shown) is formed in a bipolar transistor formation region (island) separated between elements by a trench, and an N ⁺ buried layer 5 is formed in the bipolar transistor formation region (island). .

In the LDMOS transistor formation region (island), the following LDMOS transistors are formed.
As shown in FIG. 2, a deep P region 10 is formed over the entire area of the N-type silicon layer 3 in the LDMOS transistor formation region (island). Further, an N well layer 11 as a first conductivity type semiconductor region shallower than the deep P region 10 is formed over the entire region.

  As shown in FIGS. 2 and 3, in the source cell, a P-type channel formation region (P well layer) 12 is formed in the surface layer portion of the N well layer 11, and this channel formation region 12 is connected to the deep P region 10. ing. As shown in FIG. 1, the channel forming region 12 has a stripe structure in which a planar shape forms a strip shape, and linearly extends in the Y direction in the drawing.

As shown in FIG. 3, an N ⁺ source region 13 is formed in the surface layer portion of the P-type channel formation region (P well region) 12. As shown in FIG. 1, the N ⁺ source region 13 extends linearly in the Y direction in the channel forming region 12 as in the channel forming region 12.

As shown in FIG. 2, a P ⁺ body contact region 14 for taking a substrate potential is formed on the surface layer portion of the channel formation region 12, and is in contact with the channel formation region 12 on the bottom surface of the P ⁺ body contact region 14. ing. As shown in FIG. 1, the P ⁺ body contact region 14 is intermittently extended in the extending direction (Y direction) of the channel forming region 12 in a linearly extending P-type channel forming region 12. Each P ⁺ body contact region 14 has the same length, and the length of each P ⁺ body contact region 14 is L1. Naturally, an N ⁺ source region 13 is formed between adjacent body contact regions 14 in the extending direction (Y direction) of the body contact region 14 (see FIG. 3).

In FIG. 3, on the surface side (upper surface side) of the N well layer 11, a polysilicon gate electrode 16 is disposed through at least a partial region of the channel formation region 12 via a gate oxide film 15 as a gate insulating film. . The polysilicon gate electrode 16 is covered with a silicon oxide film 17. Further, in the surface side of the N-well layer 11 (upper side), on the silicon oxide film 17, through the source electrode 18 is a contact hole 19 for taking the source potential and the substrate potential in common, N ⁺ source region 13 and It is arranged so as to be in contact with the P ⁺ body contact region 14 (see FIGS. 2 and 3).

Regarding the layout of the source cells (channel formation region 12), as shown in FIG. 1, a large number of columns of source cells (channel formation region 12) extending linearly are arranged in parallel.
As shown in FIG. 2, in the drain cell, an N ⁺ drain region 20 is formed in a surface layer portion of the N well layer 11 at a position separated from the channel formation region 12. A drain electrode 21 is disposed on the silicon oxide film 17 disposed on the N well layer 11, and the drain electrode 21 is in contact with the N ⁺ drain region 20 through the contact hole 22.

With respect to the layout of the drain cells (N ⁺ drain regions 20), as shown in FIG. 1, a large number of linearly extending drain cells (N ⁺ drain regions 20) are arranged in parallel, and the source cells (channel forming regions) are arranged. 12) are alternately arranged.

2 and 3, a LOCOS oxide film 30 is formed between the source and drain cells.
In such a MOSFET, as shown in FIG. 3, when a voltage is applied to the polysilicon gate electrode 16, current flows from the drain electrode 21 into N ⁺ drain region 20 → N well layer 11 → channel formation region (P well region). ) 12 surface layer portion → N ⁺ source region 13 → source electrode 18 flows.

Here, in the present embodiment, as shown in FIG. 9, the P ⁺ body contact region 14 is extended in the linearly extending P-type channel forming region 12 in the extending direction of the channel forming region 12 (Y in the figure). Direction), and the connection of the source electrode 18 to the N ⁺ source region 13 is indicated by a region S10 in the drawing, and the extension direction of the P ⁺ body contact region 14 (Y direction in the drawing). ) Between adjacent P ⁺ body contact regions 14 in FIG.

  A comparative example will be described with reference to FIGS. 6 is a plan view of a semiconductor device of a comparative example, FIG. 7 is a longitudinal sectional view taken along line AA in FIG. 6, and FIG. 8 is a longitudinal sectional view taken along line BB in FIG.

In the plan view of FIG. 6, source cells and drain cells are alternately formed, and a strip-like P-type channel formation region 12 extends in the Y direction in the source cell and has a stripe structure. As shown in FIGS. 7 and 8, an N ⁺ source region 13 and a P ⁺ body contact region 14 are formed in the surface layer portion of the P-type channel formation region 12. As shown in FIG. 6, the P ⁺ body contact region 14 extends in a state of being linearly connected in the Y direction. On the other hand, as shown in FIGS. 7 and 8, an N ⁺ drain region 20 is formed in the surface layer portion of the drain cell, and as shown in FIG. 6, the strip-like N ⁺ drain region 20 extends in the Y direction.

In this way, in FIG. 10 showing the comparative example, the P ⁺ body contact region 14 is continuous in the extending direction (Y direction in the drawing) of the channel forming region 12 in the linearly extending channel forming region 12. The source electrode 18 and the source region 13 are connected to each other at the side surface portion of the P ⁺ body contact region 14 as indicated by a region S20 in the drawing.

9 and FIG. 10, in the present embodiment shown in FIG. 9, since the distance in the horizontal direction (X direction) of the P ⁺ body contact region 14 can be omitted, the cell pitch P1 shown in FIG. Size can be reduced). As a result, the size can be reduced without increasing the on-resistance.

  Specifically, for the contact size in the source cell, that is, the width of the contact hole 19, the width W10 of the contact hole 19 in FIG. 9 is halved compared to the width W20 of the contact hole 19 in FIG. Can do.

  In this embodiment, the vertical and horizontal sizes of the contact holes 19 in the LDMOS source cell in FIG. 9 are L10 = 3.8 μm and W10 = 0.8 μm, and in FIG. 1, the cell pitch P1 is 10 μm. is there. In this manner, in the comparison of the cell pitch P1 in the embodiment of FIG. 1 and the cell pitch P10 in the comparative example of FIG. 6, the cell pitch P1 in the embodiment is reduced by 10% compared to the cell pitch P10 in the comparative example of FIG. We were able to plan. The vertical and horizontal sizes L10 and W10 of the contact hole 19 in the source cell may be other sizes than those described above.

Further, in the LDMOS in this embodiment, the center of the contact hole 19 is located on the line L5 through which the center of the contact hole 22 in the X direction passes as the positional relationship between the center of the contact hole 22 and the center of the contact hole 19 in FIG. positioned. In this way, in the direction (X direction) perpendicular to the extending direction (Y direction) of the channel forming region 12, the source L is formed on the line L 5 through which the contact hole 22 for connecting the drain electrode 21 to the N ⁺ drain region 20 passes. A contact hole 19 for connecting the electrode 18 to the N ⁺ source region 13 and the P ⁺ body contact region 14 is disposed. That is, the source contact hole 19 is provided beside the drain contact hole 22. Thereby, the current path flowing between the source and the drain due to surge can be shortened. Specifically, as shown in FIG. 2, the surge current is a path of drain electrode 21 → N ⁺ drain region 20 → N well layer 11 → deep P region 10 → channel forming region 12 → P ⁺ body contact region 14 → source electrode 18 It flows in. The surge current path is the shortest distance, the surge current path is short, and the ESD tolerance can be prevented from being reduced.

  In addition, the LDMOS in this embodiment is formed on the semiconductor substrate 4 which is an SOI substrate, and the LDMOS is surrounded by the trench 6 so as to be isolated from other elements. It has a structure that hardly affects the element. That is, when an LDMOS is formed on a normal silicon substrate, heat is transmitted through Si (silicon) due to heat generation, which may adversely affect other elements, but this can be avoided in this embodiment.

  4 and 5 show the measurement results of the withstand voltage and the on-resistance Ron of the structure shown in FIG. Specifically, in FIG. 4, the length L1 (see FIG. 1) of the body contact region 14 is taken on the horizontal axis, and the breakdown voltage is taken on the vertical axis. In FIG. 5, the horizontal axis represents the length L1 (see FIG. 1) of the body contact region 14, and the vertical axis represents the on-resistance Ron. 4 and 5, it can be seen that the on-resistance and breakdown voltage can be controlled by the length L1 of the body contact region 14.

According to the above embodiment, the following effects can be obtained.
(1) The body contact region 14 is intermittently extended in the channel forming region 12 in the extending direction of the channel forming region 12, and the connection of the source electrode 18 with the source region 13 is extended to the body contact region 14. Since it is performed between the adjacent body contact regions 14 in the installation direction, in the semiconductor device having the channel formation region 12 having the stripe structure, the common contact hole 19 for taking the source potential and the substrate potential in common can be downsized. Therefore, the element size can be reduced. Further, since the cell pitch can be reduced, the size can be reduced without increasing the on-resistance. Further, the on-resistance and breakdown voltage can be controlled by the length L1 of the body contact region 14.

(2) The source electrode 18 is connected to the N ⁺ source region 13 and the line L5 through which the contact hole 22 for connecting the drain electrode 21 to the N ⁺ drain region 20 in the direction orthogonal to the extending direction of the channel forming region 12 Since the contact hole 19 for connection to the P ⁺ body contact region 14 is disposed, the current path flowing between the source and drain due to surge can be shortened. As a result, a decrease in ESD tolerance can be suppressed.

  (3) The semiconductor substrate 4 is an SOI substrate configured by forming a silicon layer 3 as a semiconductor layer on a support substrate 1 via a buried oxide film (buried insulating film) 2. In the region surrounded by the element isolation trench 6 reaching the buried oxide film 2 in the element isolation region, the channel formation region 12, the source region 13, the body contact region 14, the drain region 20, the gate electrode 16, and the source Since the electrode 18 is formed, the LDMOS is formed on the SOI substrate and is separated from other elements by the trench 6, so that it is possible to prevent other elements from being affected by heat generation.

  In the above description, an N-channel LDMOS is shown, but a P-channel LDMOS may be used. That is, in the above example, the first conductivity type is N type and the second conductivity type is P type. However, the first conductivity type may be P type and the second conductivity type may be N type. .

The top view of the semiconductor device in an embodiment. The longitudinal cross-sectional view in the AA line of FIG. The longitudinal cross-sectional view in the BB line of FIG. The figure which shows the measurement result of a pressure | voltage resistance when changing the length of a body contact area | region. The figure which shows the measurement result of on-resistance when changing the length of a body contact area | region. The top view of the semiconductor device for a comparison. The longitudinal cross-sectional view in the AA line of FIG. The longitudinal cross-sectional view in the BB line of FIG. FIG. 4 is a plan view and a cross-sectional structure diagram of a source cell portion of the semiconductor device according to the embodiment. The plane and sectional structure figure of the source cell part of the semiconductor device for comparison.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Support substrate, 2 ... Embedded oxide film, 3 ... Silicon layer, 4 ... Semiconductor substrate, 6 ... Trench for element isolation, 11 ... N well layer, 12 ... Channel formation region, 13 ... N ⁺ source region, 14 ... P ⁺ body contact region, 15 ... gate oxide film, 16 ... gate electrode, 18 ... source electrode, 19 ... contact hole, 20 ... N ⁺ drain region, 21 ... drain electrode, 22 ... contact hole.

Claims (3)

A second conductivity type channel forming region (12) having a stripe structure formed in a surface layer portion of the first conductivity type semiconductor region (11) in the semiconductor substrate (4) and having a planar shape in a strip shape;
A first conductivity type source region (13) formed in a surface layer portion of the channel formation region (12);
A body contact region (14) of a second conductivity type formed on a surface layer portion of the channel formation region (12) for taking a substrate potential;
A first conductivity type drain region (20) formed at a position separated from the channel formation region (12) in a surface layer portion of the first conductivity type semiconductor region (11) in the semiconductor substrate (4);
A gate electrode (16) disposed via a gate insulating film (15) with respect to at least a partial region of the channel formation region (12) on the surface side of the first conductivity type semiconductor region (11);
The first conductive type semiconductor region (11) is disposed on the surface side so as to be in contact with the source region (13) and the body contact region (14) through a contact hole (19), and has a common source potential and substrate potential. A source electrode (18) for taking;
A semiconductor device comprising:
The body contact region (14) is intermittently extended in the channel forming region (12) in the extending direction of the channel forming region (12), and the source electrode (18) is connected to the source region (13). Is performed between adjacent body contact regions (14) in the extending direction of the body contact region (14). On the line (L5) through which the contact hole (22) for connecting the drain electrode (21) to the drain region (20) passes in the direction perpendicular to the extending direction of the channel formation region (12), the source electrode 2. The semiconductor device according to claim 1, further comprising a contact hole (19) for connecting (18) to the source region (13) and the body contact region (14). The semiconductor substrate (4) is an SOI substrate configured by forming the semiconductor layer (3) on the support substrate (1) through the buried insulating film (2), and the semiconductor layer (3) The channel forming region (12), the source region (13), the body contact region (14), the drain are formed in a region surrounded by the element isolation trench (6) reaching the buried insulating film (2) and separated from each other. The semiconductor device according to claim 1, wherein a region (20), a gate electrode (16), and a source electrode (18) are formed.

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