JP2007018264A - Bus system and route selection method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent performance degradation due to an increase in latency associated with insertion of storage means.
A bypass selection signal for designating either a route passing through a register slice inserted between a master device and a slave device or a route not passing through the register slice is input. Then, according to the bypass selection signal input by the multiplexer, it is selected whether to enable the path that passes through the register slice or to enable the path that does not pass through the register slice.
[Selection] Figure 8

Description

  The present invention relates to a bus system in which at least one or more master devices and slave devices are interconnected, and a route selection method thereof.

  In recent years, IP (Intellectual Property) cores that require high throughput, such as from USB 1.1 to USB 2.0 or from PCI to PCI-Express, have been rapidly increasing. Along with this, the demand for an on-chip bus that enables high-speed throughput transfer is rapidly increasing (see, for example, Patent Document 1).

  In June 2003, ARM announced the AMBA 3.0 AXI (Advanced eXtensible Interface) protocol as a next-generation on-chip bus standard, and has attracted attention. AMBA is an abbreviation for “Advanced Microcontroller Bus Architecture”. In this AXI, the concept of a channel that was not found in the conventional AHB (Advanced High-Performance Bus) is introduced, and consideration is given to improving the data transfer throughput by performing transfer through this channel. Specifically, it supports an independent transfer method for the address phase and the data phase, and an out-of-order transfer method in which the result of the cycle entered later may be returned to the front.

  Here, as shown in FIG. 1, the channel is defined as a series of transfer paths in which the master 101 and the slave 102 transfer the data 105 by the 2-wire handshake using the signals of valid 103 and ready 104, respectively. The transfer source of data 105 outputs valid 103 and the transfer destination outputs ready 104.

  In this AXI, as shown in FIG. 2, data transfer is performed between the master 201 and the slave 202 using four channels of address 203, write data 205, read data 204, and write response 206. Therefore, since the address channel and the data channel can be transferred independently, address processing can be issued one after another, and the bus can be used effectively.

  Furthermore, by supporting out-of-order, it is possible to return data from a slave having a low latency first. For this reason, AXI can be expected to improve bus utilization efficiency.

  On the other hand, a system having a plurality of CPUs, memories, and I / Os inside a system LSI has become common, and these devices need to be connected to each other. However, a plurality of bus masters and bus slaves are not necessarily arranged and wired equally in the system LSI. For this reason, it is considered that it becomes clear at the stage of the layout process that some connection networks, particularly high-load buses such as addresses and data, cannot be operated at the expected operating frequency.

  In such a case, time and labor have been spent re-laying the path that does not satisfy the timing many times and guaranteeing the timing at the expected operating frequency. As a worst result, the operation frequency may be lowered or the chip size may be increased.

  Therefore, in order to solve such problems, a method is adopted in which a register is inserted into a signal group between a master and a slave, which is a critical path, and the path is divided to reduce the delay amount between the register and the register. Has been. In the case of the point-to-point connection such as AXI described above, the protocol is defined by the two-wire handshake, and the flow of information passed by the handshake is unidirectional. Easy. In AXI, this method is called “register slice”.

FIG. 3 is a diagram illustrating a connection example in which a register slice is inserted into the point-to-point connection illustrated in FIG. In the example shown in FIG. 3, the register slices 301 and 302 are inserted in one stage into the address channel and the read data channel to separate the paths. As a result, the latency from the address issuance of the master 201 to the reading of the read data is increased by two cycles, but it is possible to operate at twice the maximum operating frequency.
Special table 2004-513430 gazette

  As described above, a high operating frequency can be guaranteed by inserting a register for a point-to-point connection and dividing the path. However, even if the operating frequency is increased, the performance is not improved uniformly, and depending on the relationship between the throughput and the increased latency, the performance may be decreased.

  The average transfer rate with respect to the operating frequency when burst transfer is performed using a point-to-point connected 32-bit data bus as shown in FIG. 2 will be described with reference to FIGS.

  FIG. 4 is a diagram showing the relationship between the operating frequency and the transfer rate when 16 burst transfer is performed. FIG. 5 is a diagram showing the relationship between the operating frequency and the transfer rate when 4-burst transfer is performed.

  As shown in FIGS. 4 and 5, a difference in latency appears as a difference in average transfer rate between when the register slice is inserted and when no register slice is inserted. For example, when 16 burst transfer shown in FIG. 4 is performed, a transfer rate of 480 MByte / s is obtained at 120 MHz operation without register slice. On the other hand, if a register slice is inserted, the performance of 120 MHz operation without a register slice cannot be exceeded unless it is operated at an operating frequency of at least about 135 MHz.

  Here, the number of cycles required for 16 burst transfers without register slices is 16 cycles, and when register slices are inserted, 18 cycles due to an increase in latency of “+2 cycles”.

  Further, when the 4-burst transfer shown in FIG. 5 is performed, a transfer speed of 480 MByte / s is obtained at 120 MHz operation without register slice. On the other hand, when a register slice is inserted, the performance of 120 MHz operation without a register slice cannot be exceeded unless it is operated at an operating frequency of at least about 195 MHz.

  In other words, the smaller the burst length that is supported, the greater the demand for operating frequency when register slices are inserted.

  From the above results, if it is found that timing convergence at the target frequency is difficult at the layout stage, there are the following problems even if the target frequency can be satisfied by inserting a register slice. . That is, the target frequency is for the performance before the register slice is inserted, and after the register slice is inserted, the performance may not be satisfied as the latency increases. In this case, it is necessary to select a higher frequency from selectable frequency candidates to satisfy the performance.

  When deploying a developed system LSI platform from low-end models to high-end models according to product specifications, operating at a low operating frequency rather than operating at a high operating frequency for products with low required performance reduces power consumption. There are benefits. However, simply reducing the operating frequency for a system LSI with a register slice inserted may lead to increased performance and insufficient performance.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to prevent performance degradation due to an increase in latency associated with insertion of storage means.

  The present invention is a bus system, and an input means for inputting a signal designating either a route passing through a storage means inserted between a master device and a slave device or a route not passing through the storage means; And a route selection means for selecting whether to enable a route that passes through the storage means or to enable a route that does not pass through the storage means in accordance with a signal input by the input means. To do.

  Further, the present invention is a bus system path selection method for specifying either a path that passes through a storage means inserted between a master device and a slave device or a path that does not pass through the storage means And a route selection step for selecting whether to enable a route that passes through the storage unit or to enable a route that does not pass through the storage unit in accordance with a signal input in the input step. It is characterized by having.

  According to the present invention, when a register is inserted in the layout process, a system that does not go through the register at the same time is provided, thereby preventing a performance degradation due to an increase in latency caused by register addition and selecting an optimum frequency that satisfies the required performance. be able to.

  The best mode for carrying out the invention will be described below in detail with reference to the drawings.

  FIG. 6 is a diagram illustrating a configuration example inside the system LSI in the present embodiment. In this example, three master devices 601 to 603 and three slave devices 604 to 606 exist in the system LSI and are interconnected. The protocol connecting the master devices 601 to 603 and the slave devices 604 to 606 is a simple common protocol (FIG. 1) of valid, data, and ready. Then, four types of information (FIG. 2) of address, write data, read data, and write response are communicated.

  Here, the master-slave data transfer supports burst transfer, and a maximum of 16 burst transfers are possible. The burst transfer length is communicated as part of data in the address information phase. When operating in the fastest condition, it is assumed that it takes 16 cycles for the master to issue an address and take in 16 bursts of read data.

  It is assumed that the following products having different required performance are covered by one system LSI of this embodiment.

Product A: Request transfer rate 525MByte / s
Product B: Required transfer rate 475 MByte / s, low power specification From the relationship shown in FIG. 4, it can be seen that the operating frequency that satisfies the required transfer rate 525 MByte / s when there is no register slice is 130 MHz or higher. Therefore, in this system, the design, simulation, and logic synthesis are performed using the hardware description language in the system LSI design process, and the master and slave are operated at 160 MHz.

[Layout result]
How each device is arranged in the system LSI depends on various factors such as the relationship with other functional modules and external pins, and is rarely arranged evenly.

  Here, as a result of layout, it is assumed that the path delay between the address of the master A 601 to the slave C 606 and the read data is 7.8 ns. Therefore, this path can operate at 120 MHz, but cannot operate at 160 MHz or higher (critical path). As can be seen from FIG. 4, the product A does not reach the target performance at 120 MHz. For all other paths, it is assumed that timing is guaranteed at 160 MHz.

  FIG. 7 is a diagram showing a configuration focusing on the master A 601 -slave C 606. In FIG. 7, the master device 601 and the slave device 606 are connected on a one-to-one basis (point-to-point). Here, only the address and read data channels whose timing could not be satisfied are shown. The clock 702 input to the master A 601 and the slave C 606 is generated by the clock generator 701, and can be selected from a plurality of frequency candidates (120, 140, 160, 180, 200 MHz) by the frequency selection signal 712 of the setting register 711.

[Insert register slice / bypass circuit from layout result]
FIG. 8 is a diagram showing a configuration in which a register slice & bypass circuit is inserted in the layout process. As shown in FIG. 8, a one-stage register is inserted in the layout process for the address valid signal and address, and the read data valid signal and read data. At the same time, a selector is inserted after the register slice, and a circuit is inserted so that a path passing through the register slice and a path not passing through the register slice can be selected. For this selection, it is assumed that a selection signal is input from an external pin that has been previously handled open for the purpose.

[Relay]
At the time of relayout, for a path that does not go through the register slice, the operation frequency is not 160 MHz, but the timing is guaranteed at 120 MHz. Also, the timing at 160 MHz is guaranteed for the path into which the register slice is inserted.

  With such a circuit configuration, it is possible to use a register slice system for 160 MHz operation and a system for bypassing the register slice for 120 MHz operation. As a result, the product A is operated at 160 MHz, and in the case of the product B whose required performance is lower than that of the product A, a register bypass system is used at a transfer of 120 MHz.

  For product B, the performance can be satisfied by operating at 140 MHz or 160 MHz using a register slice. However, the product B can be operated at 120 MHz without inserting a register slice, which has the advantage of reducing power consumption.

[Other Embodiments]
Next, another embodiment according to the present invention will be described in detail with reference to the drawings.

  FIG. 9 is a diagram illustrating an example of a configuration that bypasses a register slice according to another embodiment. In other embodiments, two transparent latches are used instead of register slices and multiplexers. Specifically, as shown in FIG. 9, a low through high latch type 903 and 905 and a high through low latch type 904 and 906 are used in combination.

  A signal 902 masked by a bypass selection signal 901 for selecting whether to bypass the clock 702 supplied from the clock generator 701 to the master A 601 and the slave C 606 is input to the gate input of each transparent latch.

  Thus, in the case of a register slice system operating at high speed, a clock equivalent to the clock signal supplied to the master A 601 and the slave C 606 is input to the gate input of the latch. On the other hand, when the register slice is bypassed and operated at a low speed, the latch is in a through state. Further, the bypass selection signal 901 is connected to an external input pin as in the present embodiment.

  In the embodiment described above, the bypass selection signal is connected to the external pin, but it is also possible to use the flip-flop output of the setting register as well. In this case, since whether or not a register slice is inserted depends on the layout result, a control register is prepared in advance during front-end development.

  Further, although the number of register slices is one, it is naturally possible to insert two or more registers depending on the result of placement and routing. In this case, the present invention can be similarly applied. In addition, although only one master-slave connection to which the present invention is applied is handled, naturally a plurality of connections can also be applied.

  As described above, according to the embodiment, by providing a register slice system and a bypass system thereof, performance degradation due to an increase in latency due to the addition of the register slice is prevented, and the required performance is not over-specified. An optimal frequency can be selected.

  Even if the present invention is applied to a system composed of a plurality of devices (for example, a host computer, an interface device, a reader, a printer, etc.), it is applied to an apparatus (for example, a copier, a facsimile machine, etc.) composed of a single device. It may be applied.

  In addition, a recording medium in which a program code of software for realizing the functions of the above-described embodiments is recorded is supplied to the system or apparatus, and the computer (CPU or MPU) of the system or apparatus stores the program code stored in the recording medium. Read and execute. It goes without saying that the object of the present invention can also be achieved by this.

  In this case, the program code itself read from the recording medium realizes the functions of the above-described embodiment, and the recording medium storing the program code constitutes the present invention.

  As a recording medium for supplying the program code, for example, a floppy (registered trademark) disk, a hard disk, an optical disk, a magneto-optical disk, a CD-ROM, a CD-R, a magnetic tape, a nonvolatile memory card, a ROM, or the like is used. be able to.

  In addition, by executing the program code read by the computer, not only the functions of the above-described embodiments are realized, but also the following cases are included. That is, when the OS (operating system) running on the computer performs part or all of the actual processing based on the instruction of the program code, and the functions of the above-described embodiments are realized by the processing.

  Further, the program code read from the recording medium is written in a memory provided in a function expansion board inserted into the computer or a function expansion unit connected to the computer. After that, based on the instruction of the program code, the CPU of the function expansion board or function expansion unit performs part or all of the actual processing, and the function of the above-described embodiment is realized by the processing. Needless to say.

It is a figure which shows the concept of the channel in an AXI (Advanced eXtensible Interface) protocol. It is a figure which shows four channels used for data transmission between a master and a slave. It is a figure which shows the example of a connection which inserted the register slice with respect to the point-to-point connection shown in FIG. It is a figure which shows the relationship between the operating frequency at the time of performing 16 burst transfer, and a transfer rate. It is a figure which shows the relationship between the operating frequency at the time of performing 4 burst transfer, and a transfer rate. It is a figure which shows the example of a structure inside the system LSI in this embodiment. It is a figure which shows the structure which paid its attention to master A601-slave C606. It is a figure which shows the structure which inserted the register slice & bypass circuit in the layout process. It is a figure which shows an example of the structure which bypasses the register slice in other embodiment.

Claims (9)

An input means for inputting a signal designating either a path that passes through the storage means inserted between the master device and the slave device or a path that does not pass through the storage means;
Route selection means for selecting whether to enable a route that passes through the storage means or to enable a route that does not pass through the storage means in accordance with a signal input by the input means. Bus system.   2. The bus system according to claim 1, wherein the storage means is a register inserted in a layout process in order to operate at a high frequency, and the path selection means is constituted by a selector.   2. The bus system according to claim 1, wherein the storage means and the selection means are constituted by a transparent latch.   2. The bus system according to claim 1, wherein the input means inputs the signal via an external pin for connection to the outside.   2. The bus system according to claim 1, wherein the selection input means inputs the signal output from a predetermined control register.   The bus system according to claim 1, wherein the route selection unit is automatically generated at a subsequent stage of the storage unit. An input step of inputting a signal designating either a route passing through the storage means inserted between the master device and the slave device or a route not passing through the storage means;
And a route selection step of selecting whether to enable a route that passes through the storage unit or to enable a route that does not pass through the storage unit in accordance with the signal input in the input step. Bus system route selection method.   A program for causing a computer to execute the bus system route selection method according to claim 7.   A computer-readable recording medium on which the program according to claim 8 is recorded.

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