JP2007013245A - Solid-state imaging device, driving method of solid-state imaging device, and imaging device - Google Patents

Abstract

A conventional interlaced two-row addition readout method cannot be applied as it is to a solid-state imaging device having an oblique pixel shift arrangement.
In a solid-state imaging device adopting an interlaced two-row addition readout method and having an oblique pixel shift arrangement, two rows are selected for readout, and at the same time, readout is performed for each pixel in a specific row. By executing a non-reset operation, the signal charge accumulation times in the pixels of all rows are made equal, specifically, (1V-1H). This eliminates image flickering in moving image display caused by a difference in pixel accumulation time during interlaced moving image capturing.
[Selection] Figure 10

Description

  The present invention relates to a solid-state imaging device, a driving method of the solid-state imaging device, and an imaging device, and more particularly, to a solid-state imaging device that employs an interlaced two-row addition readout method,

  In a solid-state imaging device, for example, a CMOS image sensor, as a scanning method for reading a signal from each pixel of a pixel array unit in which pixels including photoelectric conversion elements are two-dimensionally arranged in a matrix, it is effective in suppressing flickering of moving image display. There are an interlace scanning method and a progressive scanning method advantageous for high-definition display.

  The interlaced scanning method can be realized by dividing one screen display into two scans of odd and even lines. However, if screen display is performed by simply scanning odd and even rows alternately, the center of gravity shifts between frames, resulting in flickering of moving images. The “frame” here corresponds to a field in units of 1/60 [second] of the NTSC system, for example.

  In order to eliminate the flickering of the moving image caused by the deviation of the center of gravity between the frames described above, conventionally, the screen display of one time is performed by adding pixel signals between two adjacent upper and lower lines. An interlaced two-row addition readout method is adopted in which the combination of adjacent upper and lower rows is shifted by one row and divided into two scans in which pixel signals are added between the upper and lower two rows shifted by one row (for example, Patent Document 1).

JP-A-10-98653

  However, in the above prior art, pixels including photoelectric conversion elements have the same pixel pitch in the horizontal direction (direction along the pixel row; row direction) and the vertical direction (direction along the pixel column; column direction). This is based on the premise of a pixel array arranged in a square lattice.

  Therefore, for the purpose of increasing the effective integration degree of the pixels, each pixel is arranged by shifting the pixel pitch by 1/2 of every row and every column, that is, the pixels are horizontally arranged in the odd and even rows. The above-described conventional technique is applied as it is to a solid-state imaging device having a so-called diagonal pixel shift arrangement in which the pixel pitch is shifted by ½ of the pixel pitch in the odd-numbered and even-numbered columns. I can't.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a solid-state imaging device, a driving method for the solid-state imaging device, and an imaging device that can apply the interlaced two-row addition readout method to an oblique pixel shift arrangement.

  In order to achieve the above object, in the present invention, pixels including photoelectric conversion elements are two-dimensionally arranged in a matrix, and each pixel is arranged obliquely with a pixel pitch shifted by 1/2 of every row and every column. In a solid-state imaging device including a pixel array unit with a pixel shift arrangement, in order to perform interlaced multiple row addition reading, signals are read from the pixels while selectively scanning each pixel of the pixel array unit in units of rows. Therefore, a configuration is adopted in which pixel reset is performed on the pixels in a specific row other than the plurality of rows to be selected.

  In a solid-state imaging device that employs an interlaced multiple-row addition readout method and has an oblique pixel shift arrangement, multiple rows are selected to read signals from the pixels, and at the same time, signals are read from each pixel in a specific row. By executing pixel reset without accompanying, if one frame period is 1V and one horizontal period is 1H, the signal charge accumulation time in all rows of pixels is (1V-1H). The accumulation time can be made equal.

  According to the present invention, in a solid-state imaging device adopting an interlaced multiple-row addition readout method and having an oblique pixel shift arrangement configuration, the signal charge accumulation time in all rows can be made equal. It is possible to eliminate the flicker of the image in the moving image display caused by the difference in time.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a block diagram showing an outline of a configuration of a solid-state imaging device, for example, a CMOS image sensor according to an embodiment of the present invention.

  In the CMOS image sensor according to the present embodiment, as a scanning method for reading out signals from each pixel, an interlaced multiple row addition reading method, for example, a single screen display, adds pixel signals between two adjacent upper and lower rows, In the next round, an interlaced two-row addition readout method is adopted in which the combination of adjacent upper and lower rows is shifted by one row and divided into two scans in which pixel signals are added between the upper and lower two rows shifted by one row. In addition, each pixel does not have a color filter.

  As shown in FIG. 1, a CMOS image sensor 10 according to this embodiment includes a pixel array unit 11 and peripheral circuits of the pixel array unit 11, such as a vertical scanning circuit 12, a voltage level shift circuit 13, a column circuit (column parallel signal). Processing circuit) 14, horizontal scanning circuit 15, output circuit 16 and timing generator 17, and these peripheral circuits 12 to 17 are integrated on the same semiconductor chip (not shown) as the pixel array unit 11. ing.

  In the pixel array unit 11, a large number of pixels 20 including photoelectric conversion elements are two-dimensionally arranged in a matrix, and each pixel 20 is arranged with a deviation of ½ of the pixel pitch for each row and for each column. The pixel 20 has an oblique pixel shift arrangement in which the odd-numbered row and the even-numbered row are shifted by a half of the pixel pitch in the horizontal direction, and the odd-numbered column and the even-numbered column are shifted by a half of the pixel pitch. The vertical signal line 31 is wired for each pixel column, and, for example, three control lines 32, 33, and 34 are wired for each pixel row. The oblique pixel shifting arrangement has a feature that the effective integration degree of pixels can be increased.

(Pixel circuit)
FIG. 2 is a circuit diagram illustrating an example of a circuit configuration of the pixel 20.

  As shown in FIG. 2, the pixel 20 according to this circuit example is a pixel circuit having three transistors, for example, a transfer transistor 22, a reset transistor 23, and an amplification transistor 24 in addition to a photoelectric conversion element, for example, a photodiode 21. ing. Here, as these transistors 22 to 24, for example, N-channel MOS transistors are used. The control lines 32 to 34 described above, that is, the transfer control line 32, the reset control line 33, and the select control line 34 are wired in common to the pixels in the same row.

  In FIG. 2, the photodiode 21 photoelectrically converts received light into photoelectric charges (here, electrons) having a charge amount corresponding to the amount of light. The cathode of the photodiode 21 is electrically connected to the gate of the amplification transistor 24 through the transfer transistor 22. A node electrically connected to the gate of the amplification transistor 24 is referred to as an FD (floating diffusion) portion 25. The FD unit 25 functions to convert charges into voltage.

  The transfer transistor 22 is connected between the cathode of the photodiode 21 and the FD unit 25, and the transfer pulse TG given to the gate via the transfer control line 32 is active (in this example, “H” which is the pixel power supply voltage). Level), the photoelectric charge is photoelectrically converted by the photodiode 21 and the photoelectric charge accumulated in the photodiode 21 is transferred to the FD section 25.

  The reset transistor 23 is turned on when the drain is connected to the select control line 34, the source is connected to the FD unit 25, and the reset pulse RST given to the gate via the reset control line 33 is activated, and the photodiode 21 Prior to the transfer of the signal charge from the FD unit 25 to the FD unit 25, the FD unit 25 is reset (initialized) by sweeping the charge of the FD unit 25 to the select control line 34. The potential of the select control line 34 is normally at the ground level (0 V), and this potential becomes the reset level of the FD unit 25.

  The amplifying transistor 24 has a gate connected to the FD unit 25, a drain connected to the select control line 34, a source connected to the signal line 31, and a selection pulse SEL supplied to the drain via the select control line 34 is supplied with a pixel power supply voltage ("" The operation state (selection state) is brought about by going to the “H” level, and the potential of the FD section 25 after being reset by the reset transistor 23 is outputted to the vertical signal line 31 as a reset level (so-called P-phase reading).

  Further, the amplification transistor 24 outputs the potential of the FD section 25 after the signal charge is transferred from the photodiode 21 by the transfer transistor 22 to the vertical signal line 31 as a signal level (so-called D-phase reading). A constant current source 35 is connected to each end of the vertical signal line 31. Therefore, the reset level and the signal level are read as a change in current to each of the vertical signal lines 31.

  Since the CMOS image sensor 10 according to the present embodiment employs the interlaced two-row addition readout method, the above-described readout operation is performed on each pixel 20 of the pixel array unit 11 under the control of the vertical scanning circuit 12 described later. Will be executed sequentially in two lines.

  The readout of signals from the selected two rows of pixels 20 is performed during a horizontal blanking period within one horizontal period (1H). In other words, in the horizontal blanking period, signals from the pixels 20 in the two rows selected by the vertical scanning by the vertical scanning circuit 12 are read out to the vertical signal lines 31 and are column-paralleled through the vertical signal lines 31. It is supplied to the column circuit 14.

  In the horizontal blanking period, the pixel reset operation is performed after the above-described P-phase readout and D-phase readout operations are performed. This pixel reset is executed when the transfer pulse TG and the reset pulse RST become active simultaneously (in this example, “H” level).

  That is, in the pixel 20 configured as described above, the transfer pulse TG and the reset pulse RST are simultaneously set to the “H” level, so that the charges accumulated in the photodiode 21 are transferred via the transfer transistor 22 as shown in FIG. Charges in the FD unit 25 are further swept out to the select control line 34 via the reset transistor 23. Thereby, initialization of the photodiode 21 and the FD unit 25, that is, pixel reset is performed.

  Note that the pixel 20 is not limited to the above-described three-transistor configuration, that is, a configuration in which the amplification transistor 24 is also used as a selection transistor for pixel selection, and a four-transistor in which a selection transistor is provided separately from the amplification transistor 24. It is also possible to use a configuration or the like.

  Returning to FIG. The vertical scanning circuit 12 is configured by an address decoder or the like, and selectively scans each pixel 20 of the pixel array unit 11 in units of rows based on an address signal A <X: 0> supplied from the timing generator 17, and the selected row. On the other hand, the driving pulse at the logic circuit level, that is, the transfer pulse TG, the reset pulse RST and the selection pulse SEL described above are output.

  Although not shown here, the vertical scanning circuit 12 sequentially selects the pixels 20 in units of rows and performs a reading operation for reading a signal of each pixel 20 in the selected row, and the reading scanning. An electronic shutter scanning system for performing an electronic shutter operation that discards (resets) charges accumulated so far in the photodiodes 21 of the pixels 20 in the same row a time corresponding to the shutter speed before the readout scanning by the system It has composition which has.

  The period from the timing when the unnecessary charge of the photodiode 21 is reset by the shutter scanning by the electronic shutter scanning system to the timing when the signal of the pixel 20 is read by the reading scanning by the readout scanning system is the period of the signal charge in the pixel 20. Accumulation time (exposure time). That is, the electronic shutter operation is an operation of resetting the signal charge accumulated in the photodiode 21 and newly starting accumulation of signal charge.

  The CMOS image sensor 10 according to the present embodiment employs an interlaced 2-row addition reading method, and the operation of the interlaced 2-row addition reading method is executed under the control of the vertical scanning circuit 12. That is, in the case of the interlaced two-row addition readout method, the vertical scanning circuit 12 selectively scans each pixel 20 of the pixel array unit 11 by two rows simultaneously. A specific configuration and operation of the vertical scanning circuit 12 for executing this interlaced two-row addition reading method will be described later.

  The voltage level shift circuit 13 shifts the transfer pulse TG, the reset pulse RST, and the selection pulse SEL at the logic circuit level output from the vertical scanning circuit 12 to the pixel drive level voltage, and then transfers the transfer control line 32 and the reset control. This is supplied to the pixel 20 in the selected row through the line 33 and the select control line 34.

  In the case of the interlaced two-row addition reading method, since selective scanning is performed simultaneously by two rows by vertical scanning by the vertical scanning circuit 12, a signal is sent from each pixel 20 of the selected two rows to each of the vertical signal lines 31. By reading out, the signals of the pixels of two rows are added on these vertical signal lines 31, and these added signals are supplied to the column circuit 14 in parallel in columns through each of the vertical signal lines 31.

  The column circuit 14 is provided with a unit circuit for each pixel column of the pixel array unit 11, that is, with a one-to-one correspondence with the pixel column, and outputs a signal output from each pixel 20 for one row. Received for each column, the signal is subjected to signal processing such as CDS (Correlated Double Sampling) and signal amplification for removing fixed pattern noise specific to the pixel. It is also possible to adopt a configuration in which the column circuit 14 has an A / D (analog / digital) conversion function.

  The horizontal scanning circuit 15 is configured by a shift register or the like, and sequentially selects a horizontal selection switch (not shown) provided on the output side of each unit circuit of the column circuit 14 in a reading period within 1H (one horizontal period). As a result, signals for one row after signal processing by each unit circuit of the column circuit 14 are sequentially output to the horizontal signal line 18.

  The output circuit 16 performs various signal processing, for example, AGC (Automatic Gain Control) processing, clamping processing, and the like on the signals sequentially supplied from the column circuit 14 through the horizontal signal line 18, and outputs the image signal OUT for one horizontal period. Output as.

  A series of operations in each circuit portion described above, that is, P-phase readout in the horizontal blanking period, D-phase readout and pixel reset, and readout of signals from the column circuit 14 and output circuit 16 by horizontal scanning in the horizontal readout period. Each operation of the signal processing according to is performed in a 1H cycle in one frame period, whereby an image signal of one frame is obtained.

  The timing generator 17 generates a clock signal, a control signal, and the like that serve as a reference for operations of the vertical scanning circuit 12, the column circuit 14, the horizontal scanning circuit 15, and the output circuit 16 based on the vertical synchronizing signal, the horizontal synchronizing signal, and the master clock. It is generated and given to each of these circuits 12, 14-16.

  Here, in the CMOS image sensor 10 having the above-described oblique pixel shift arrangement, consider a one-frame shutter at the time of the operation in the case of the interlaced two-row addition reading method (hereinafter referred to as “interlaced two-row addition reading operation”). Here, the one-frame shutter refers to an operation of performing an electronic shutter and pixel reset once in one frame period.

[Reference example]
First, a general method of scanning in the vertical direction in the diagonal pixel array will be described as a reference example. As the method, as shown in FIG. 4, scanning is performed in the order of 1 → 2 → 3 → 4 →. In FIG. 4, the numerals indicate the line numbers. At this time, in the case of the pixel misalignment arrangement, as shown in FIG. 5, the signals read in the odd rows and the signals read in the even rows are simultaneously read out by scanning with the horizontal scanning circuit 15. It is a feature that is possible.

  Considering this point, from FIG. 6, in the first frame, (1 line + 3 line) and (2 line + 4 line) → (5 line + 7 line) and (6 line + 8 line) → (9 line + 11). (Line) and (10 line + 12 line) →... Are added and read, and in the next second frame, (3 line + 5 line), (4 line + 6 line) → (7 line + 9 line) and (8 line + 10). Interlaced readout is performed by performing addition readout of (row) → (11 row + 13 row) and (12 row + 14 row) →. At that time, the accumulation operation (reset period) is performed between the first frame and the second frame.

  Focusing only on the odd-numbered rows, the reset period between the 3rd row of the first frame and the 3rd row of the 2nd frame is a 1V period (V is a frame period / vertical period). The reset period is (1V-1H), the reset period between the 7th row of the first frame and the 7th row of the second frame is the 1V period, the reset period between the 9th row of the first frame and the 9th row of the second frame is (1V- 1H) period.

  Since even-numbered rows are read simultaneously with odd-numbered rows, if attention is paid only to even-numbered rows, the reset period between the 4th row of the first frame and the 4th row of the second frame is a 1V period, the 6th row of the first frame → the second frame The reset period between the six rows is (1V-1H), the reset period between the 8th row of the first frame → the 8th row of the second frame is the 1V period, the 10th row of the first frame → the reset period between the 10th row of the second frame Is a (1V-1H) period.

  Next, consider the second to third frames. First, focusing only on the odd-numbered rows, the reset period between the 3rd row of the 2nd frame and the 3rd row of the 3rd frame is a 1V period, and the reset period between the 5th row of the 2nd frame and the 5th row of the 3rd frame is a (1V + 1H) period. The reset period between the 7th row of the second frame and the 7th row of the third frame is a 1V period, and the reset period between the 9th row of the second frame and the 9th row of the third frame is a (1V + 1H) period.

  Since even-numbered rows are read simultaneously with odd-numbered rows, if attention is paid only to even-numbered rows, the reset period between the 4th row of the 2nd frame and the 4th row of the 3rd frame is the 1V period, the 6th row of the 2nd frame → the 3rd frame The reset period between the 6th row is (1V + 1H) period, the reset period between the 8th row of the 2nd frame → the 8th row of the 3rd frame is the 1V period, the 10th row of the 2nd frame → the reset period between the 10th row of the 3rd frame is ( 1V + 1H) period.

  As described above, in the CMOS image sensor 10 with the diagonal pixel shift arrangement, as the reference example, 1 → 2 → 3 → 4 →... As scanning is performed, a minimum (1V-1H) and a maximum (1V + 1H), that is, 2H, are output as a difference in the signal charge accumulation time of the pixel 20 between the frames and between the rows within the same frame. Will end up. This difference in accumulation time appears as flickering of images in moving image display during interlaced moving image capturing.

  On the other hand, in the CMOS image sensor 10 according to the present embodiment, the problem that occurs during the interlaced two-row addition reading operation, that is, the difference in the accumulation time of the pixels 20 that occurs between the frames and between the rows within the same frame is solved. Therefore, a configuration is adopted in which pixel reset is executed for pixels in a specific row other than the row (two rows) selected to read out signals from the pixels 20.

  As described above, in the pixels in the row selected for signal readout, the pixel reset operation is also performed at the time of readout. However, in the CMOS image sensor 10 according to the present embodiment, 2 pixels are used to read out signals from the pixels 20. At the same time as selecting a row, pixel reset without readout is executed for each pixel in a specific row. As a result, the signal charge accumulation times of the pixels 20 in all the rows can be made equal, and the flickering of the image in the moving image display caused by the difference in the accumulation times can be eliminated.

[Example]
Such an interlaced two-row addition reading operation, that is, an operation for executing pixel reset for pixels in a specific row other than the row (two rows) selected for reading signals from the pixels 20 is a vertical scanning circuit. 12 is executed under the control of 12.

  A specific example of the vertical scanning circuit 12 for executing the interlaced two-row addition reading operation will be described below. As described above, the vertical scanning circuit 12 executes the P-phase reading by activating the reset pulse RST of the selected row, and executes the D-phase reading by activating the transfer pulse TG. Also, the pixel reset is executed by simultaneously activating the reset pulse RST and the transfer pulse TG.

  Here, the vertical scanning circuit 12 adopts an address decoding method using an address decoder as a scanning selection method, and the address decoding method is limited to one reset row (row for performing a reset operation) within the same frame period. Cannot be selected. Therefore, in the vertical scanning circuit 12 according to the present embodiment, a plurality of address decoders are prepared so that a plurality of reset rows can be selected simultaneously within the same frame.

  FIG. 7 is a block diagram showing an example of the basic configuration of the vertical scanning circuit 12. As shown in FIG. 4, the vertical scanning circuit 12 according to this basic form includes two systems of a reset address decoder 121 for selecting the reset transistor 23 and a reset address decoder 122 for selecting the transfer transistor 22 in the electronic shutter operation. The decoder (A, B) and one decoder (C) of the read address decoder 123 for selecting the reset transistor 23 and the transfer transistor 22 during the actual read operation, and the logical sum of the outputs of the decoders 121 to 123 By selecting (OR), the selected row is determined.

  The read address decoder 123 is a decoder that selects a row from which a signal is read from each pixel 20 of the pixel array unit 11. That is, a certain row is selected as a read row by the read address decoder 123. The read address decoder 123 generates a transfer pulse TG and a reset pulse RST so that P-phase readout, D-phase readout, and pixel reset are performed on each pixel 20 in the selected row.

  On the other hand, the reset address decoders 121 and 122 are decoders that select a row in which only pixel reset is performed. Note that pixel reset is executed immediately after reading in the row where normal reading is performed. On the other hand, in this example, in order to reset the pixels in a specific row other than the row selected for reading (two rows), the reset address decoders 121 and 122 reset the pixels without reading. A line where only is done will occur.

  The number of decoders (121, 122) corresponding to the electronic shutter operation is determined by the specification.

  FIG. 8 is a block diagram showing a specific configuration example of the vertical scanning circuit 12. As described above, two or more reset address decoders are actually provided, but here, only one reset address decoder 121 is shown as a representative for simplification of the drawing. . Here, only the circuit configuration for one row of the n-th row is shown.

(Reset address decoder)
In FIG. 8, the reset address decoder 121 includes a reset row selection decoder 41 and two 2-input NAND circuits 42 and 43 per row.

  The reset row selection decoder 41 is given from the timing generator 17 an address (hereinafter referred to as “reset address”) RST-Ad that designates a row to be reset. The reset row selection decoder 41 has n output terminals corresponding to each row (1 row to n rows) of the pixel array unit 11, and is a row designated by the reset address RST-Ad, that is, n output terminals. The “H” level reset row selection pulses RS1 to RSn are generated from the terminal selected from among the terminals.

  The 2-input NAND circuit 42 has a reset row selection pulse RSn as a first input and a TG control pulse SHTG supplied from the timing generator 17 as a second input. The TG control pulse SHTG defines the pixel reset timing. The 2-input NAND circuit 43 has the reset row selection pulse RSn as a first input and the TG control pulse SHRST supplied from the timing generator 17 as a second input. The TG control pulse SHRST defines the pixel reset timing. The outputs of the NAND circuits 42 and 43 are supplied to the read address decoder 122.

(Read address decoder)
On the other hand, the read address decoder 122 includes a read row selection decoder 51, two 3-input NAND circuits 52 and 53, and inverters 54 and 55, two for each row.

  An address (hereinafter referred to as “read address”) RD-Ad that designates a row to be selected is supplied from the timing generator 17 to the read row selection decoder 51. The read row selection decoder 51 has n output terminals corresponding to each row of the pixel array unit 11, and is a row selected by the read address RD-Ad, that is, a terminal selected from the n output terminals. Therefore, “H” level read row selection pulses RD1 to RDn are generated.

  The 3-input NAND circuit 52 uses the read row selection pulse RDn as the first input, the output of the NAND circuit 42 as the second input, and the TG control pulse TRTG supplied from the timing generator 17 via the inverter 61 as the third input. As an input. The output of the NAND circuit 52 is supplied to the voltage level shift circuit 13 through the inverter 54 as a transfer pulse TG. That is, the TG control pulse TRTG defines the timing for activating the transfer pulse TG for D-phase reading within the horizontal blanking period every 1H period.

  The 3-input NAND circuit 53 has the read row selection pulse RDn as a first input, the output of the NAND circuit 43 as a second input, and a TG control pulse TRRST supplied from the timing generator 17 via the inverter 62 as a third input. As an input. The output of the NAND circuit 53 is supplied to the voltage level shift circuit 13 through the inverter 55 as a reset pulse RST. That is, the TG control pulse TRRST defines the timing at which the reset pulse RST is activated for P-phase reading within the horizontal blanking period every 1H period.

  FIG. 9 shows a timing relationship among the TG control pulse SHRST, the TG control pulse SHTG, the TG control pulse TRRST, the TG control pulse TRTG, the reset pulse RST, and the transfer pulse TG. As is clear from this timing chart, P-phase reading for reading the reset level is performed in the horizontal (H) blanking period, D-phase reading for reading the signal level is performed next, and then the difference between the reset level and the signal level. The difference is output as a signal level after noise removal by horizontal scanning in the readout period (horizontal transfer period).

  Normally, in a one-frame shutter (an operation that performs electronic shutter and pixel reset once in one frame period), the row selected by the read address decoder 123 that becomes active at the time of reading is (1) reset read (reset the FD section 25). → Read) → (2) The transfer transistor 22 is turned on, the signal is read out → (3) Pixel reset (the photodiode 21 is also reset at this time), and each pixel 20 in the selected row is finally reset. Charge is accumulated in the pixel 20, specifically, the photodiode 21 from the time point to the next frame.

  In this operation sequence, as described above, there is a difference in the accumulation time of the pixels 20 between the frames. In order to prevent this difference in storage time, the CMOS image sensor 10 according to the present embodiment is provided with, for example, two reset address decoders (A) 121 and (B) 122, and any one of these decoders is activated. Thus, it is possible to select a row for which a shutter operation is desired.

(Shutter operation to eliminate the difference in accumulation time)
Hereinafter, in the CMOS image sensor 10 according to the present embodiment, a shutter operation (= pixel reset operation) for eliminating the difference in the accumulation time of the pixels 20 in the interlaced two-row addition readout operation will be specifically described with reference to FIG. explain. FIG. 10 shows a state in which a row is selected by a two-row addition reading operation of 1 frame → 2 frame → 3 frame.

(A) 1 to 2 frames (odd matrix)
The accumulation time is 1V (1 frame or 1/60 [second]) at 3 rows, 7 rows, 11 rows,..., And 1 V-1H (= 1/1/5 rows, 9 rows, 13 rows,... 60 [seconds]-(1/60 [seconds] / number of V.) In order to eliminate this difference in accumulation time of -1H, a row that can be accumulated in 1V period is intentionally shortened by 1H period (-1H Then, the shutter operation for setting the accumulation time of all the rows to 1V-1H is performed.

  Specifically, in the first frame, (1) (1 row + 3 rows) is read, and (2) (5 rows + 7 rows) is read, and at the same time, the reset address decoder (A) 121 or (B ) Select at 122 and perform the shutter operation. Next, (3) (7 rows + 9 rows) is read out, and at the same time, the fifth row is selected by the reset address decoder (A) 121 or (B) 122, and a shutter operation is performed. With this operation sequence, the accumulation times of all the rows can be made equal to 1V-1H.

(B) 1 frame to 2 frames (even number matrix)
The accumulation time is 1V (1 frame or 1/60 [second]) at 4th, 8th, 12th,..., And 1V-1H (= 1/1) at 6th, 10th, 14th,. 60 [seconds]-(1/60 [seconds] / number of V.) In order to eliminate this difference in accumulation time of -1H, a row that can be accumulated in 1V period is intentionally shortened by 1H period (-1H Then, the shutter operation for setting the accumulation time of all the rows to 1V-1H is performed.

  Specifically, in the first frame, (1) (2 rows + 4 rows) is read, and (2) (6 rows + 8 rows) is read, and at the same time, the fourth row is reset address decoder (A) 121 or (B ) Select at 122 and perform the shutter operation. Next, (3) (10 rows + 12 rows) is read, and at the same time, the eighth row is selected by the reset address decoder (A) 121 or (B) 122, and a shutter operation is performed. With this operation sequence, the accumulation times of all the rows can be made equal to 1V-1H.

(C) 2 to 3 frames (odd matrix)
The accumulation time is 1V (1 frame or 1/60 [second]) at 3 rows, 7 rows, 11 rows,..., And 1 V + 1H (= 1/60 [= 1] at 5 rows, 9 rows, 13 rows,. Second] + (1/60 [seconds] / number of V.) In order to eliminate this difference in the accumulation time of + 1H, a line that can be accumulated in 1V period is intentionally set to -1H or -2H, and all A shutter operation for setting the row accumulation time to 1V-1H is performed.

  Specifically, in the second frame, (1) (3 rows + 5 rows) is read out, and (2) (7 rows + 9 rows) is read out, and at the same time the third row is read with the reset address decoder (A) 121 or (B ) Select at 122 and perform the shutter operation. Next, (3) (11th row + 13th row) is read out, and at the same time, the fifth and seventh rows are selected by the reset address decoder (A) 121 or (B) 122, and the shutter operation is performed. With this operation sequence, the accumulation times of all the rows can be made equal to 1V-1H.

(D) 2 to 3 frames (even number matrix)
The accumulation time is 1V (1 frame or 1/60 [second]) at 4th, 8th, 12th,..., And 1V + 1H (= 1/60 [= 1] at 6th, 10th, 14th,. Second] + (1/60 [seconds] / number of V.) In order to eliminate this difference in the accumulation time of + 1H, a line that can be accumulated in 1V period is intentionally set to -1H or -2H, and all A shutter operation for setting the row accumulation time to 1V-1H is performed.

  Specifically, in the second frame, (1) (4 rows + 6 rows) is read, and (2) (8 rows + 10 rows) is read, and at the same time, the fourth row is reset address decoder (A) 121 or (B ) Select at 122 and perform the shutter operation. Next, (3) (12 rows + 14 rows) is read out, and at the same time, the sixth and eighth rows are selected by the reset address decoder (A) 121 or (B) 122, and the shutter operation is performed. With this operation sequence, the accumulation times of all the rows can be made equal to 1V-1H.

  Thereafter, the operations (A) / (B) and (C) / (D) are repeated. FIG. 11 shows a timing relationship for performing the shutter operation on the third row when reading out the fifth row + 7th row of the first frame.

  Here, in the first frame, the TG control pulse SHRST, the TG control pulse SHTG, the TG control pulse TRRST, and the TG control pulse TRTG when the third row performs the shutter operation, and the fifth and seventh rows perform the read operation. The timing relationship between the reset pulse RST and the transfer pulse TG is shown. Further, <3>, <5>, <7> in the reset pulse RST and the transfer pulse TG indicate row numbers.

  By the series of shutter operations described above, it is possible to eliminate a problem that occurs during the interlaced two-row addition reading operation, that is, a difference in signal charge accumulation time in the pixels 20 that occurs between the frames and between the rows even within the same frame. That is, the accumulation times of the pixels 20 can be made uniform between the frames and between the rows even in the same frame.

  However, in order to perform the series of shutter operations described above under the control of the reset address decoder (A) 121 / (B) 122, a frame determination circuit (not shown) outside the CMOS image sensor 10 is used. It is determined whether the current frame is an even frame or an odd frame (frame recognition function), and a signal for changing the address switching method according to the determination result is sent to the timing generator 17 that generates the reset address RST-Ad. Given this, it is necessary to select a reset line according to the frame.

  As described above, the CMOS image sensor 10 adopting the interlaced two-row addition readout method and having the oblique pixel shift arrangement configuration performs the above-described series of shutter operations, that is, selects two rows at a time for readout. At the same time, by executing a pixel reset operation that does not involve readout for each pixel in a specific row, the signal charge accumulation time in the pixels in all rows becomes (1V-1H), and all the rows accumulate. Since the time can be equalized, it is possible to eliminate the flickering of the image in the moving image display caused by the difference in the accumulation time when the interlaced moving image is captured.

  In the above embodiment, the interlaced 2-row addition readout method has been described as an example. However, the present invention is not limited to the interlaced 2-row addition readout method, and signals of pixels in a plurality of rows of three or more rows are simultaneously read and added. Even in the case of the interlaced multiple-row addition method, it is assumed that variations in the accumulation time of pixels occur.Therefore, by increasing the number of reset address decoders and appropriately selecting a row for pixel reset operation, The same effect as the embodiment can be obtained.

  In the above embodiment, the CMOS image sensor has been described as an example of the solid-state imaging device, but the present invention is not limited to the application to the CMOS image sensor, and an oblique pixel shift arrangement such as a MOS image sensor, and The present invention is applicable to all solid-state imaging devices configured to read out signals from each pixel in a selected row in a column in parallel while performing pixel selection in units of rows.

  Since the CMOS image sensor 10 according to the above embodiment has a configuration in which each pixel 20 does not have a color filter, it is a single-plate monochrome imaging device that uses one image sensor, or R (red) and G (green). , B (blue), it is applied to a three-plate type color imaging device using an image sensor for each color.

  Here, the imaging device is a solid-state imaging device (image sensor) as an imaging device, an optical system that forms image light of a subject on an imaging surface (light-receiving surface) of the solid-state imaging device, and a signal of the solid-state imaging device A camera module including a processing system and a camera system including the camera module are referred to.

[Application example]
FIG. 12 is a block diagram illustrating a configuration example of an imaging apparatus according to an application example of the present invention, such as a three-plate imaging apparatus. In FIG. 12, an alternate long and short dash line indicates a light beam, and a solid line indicates a signal line.

  In FIG. 12, image light (incident light) from a subject (not shown) passes through an optical system including an imaging lens 61 and enters a three-color separation prism 62. The three-color separation prism 62 includes three prism blocks 62A, 62B, and 62C. A dichroic layer 63A that reflects blue light and transmits red light and green light at the boundary between the blocks 62A and 62B includes a block 62B. A dichroic layer 63B that reflects red light and transmits green light is provided at the boundary portion of 62C.

  The red, green, and blue lights separated by the three-color separation prism 62 are incident on three image pickup devices 64R, 64G, and 64B provided close to the emission surface of the three-color separation prism 62, respectively. As the imaging devices 64R, 64G, and 64B, the solid-state imaging device according to the above-described embodiment, specifically, the CMOS image sensor 10 that employs the interlaced two-row addition readout method and has an oblique pixel shift arrangement configuration is used.

  Under the control of the controller 65, the imaging devices 64R, 64G, and 64B perform an imaging operation according to the operation mode set by the mode setting unit 66, for example, the still image mode or the moving image monitoring mode. Specifically, when the still image mode is set, an operation of independently reading out signals of all pixels is performed, and when the moving image monitoring mode is set, the above-described interlaced two-row addition reading operation is performed.

  By performing the interlaced 2-line addition readout operation in the video monitoring mode, it is possible to eliminate the video flicker caused by the deviation of the center of gravity between the frames, and at the same time as selecting every two rows for readout. Since each pixel in a specific row performs a reset operation that does not involve reading, the accumulation time of all the rows can be made equal, so that an image in a moving image display resulting from a difference in accumulation time during interlaced moving image capturing The flicker can be eliminated.

  The output signals of the imaging devices 64R, 64G, and 64B are subjected to predetermined signal processing by the signal processing circuit 67. Specifically, the signal processing circuit 67 performs correction processing such as defect correction for correcting pixel defects of the imaging devices 64R, 64G, and 64B, shading correction for correcting peripheral light loss of the imaging lens 61, and luminance (Y ) Signal processing for generating signals and color difference signals RY, BY is performed. Further, when the moving image monitoring mode is set, a monitor video signal is supplied from the signal processing circuit 67 to a monitor (liquid crystal display device, EL (electro luminescence) display device, etc.) attached to the imaging apparatus.

It is a block diagram which shows the outline of a structure of the CMOS image sensor which concerns on one Embodiment of this invention. It is a circuit diagram which shows an example of the circuit structure of a pixel. It is explanatory drawing of initialization (reset) of a photodiode and FD part. It is explanatory drawing of the outline | summary of the interlace 2 line addition read operation which concerns on a reference example. It is explanatory drawing of the outline | summary of the row access and signal output in the interlace 2-row addition read operation which concerns on a reference example. It is explanatory drawing of the difference in the accumulation time in the interlace 2 line addition read operation which concerns on a reference example. It is a block diagram which shows the structural example of the basic form of the vertical scanning circuit which concerns on an Example. It is a block diagram which shows the specific structural example of the vertical scanning circuit which concerns on an Example. It is a timing chart which shows the timing relationship of TG control pulse SHRST, TG control pulse SHTG, TG control pulse TRRST, TG control pulse TRTG, reset pulse RST, and transfer pulse TG. It is explanatory drawing of the shutter operation | movement which eliminates the difference in the accumulation time in the interlace 2 line addition read operation. 10 is a timing chart showing a timing relationship for performing a shutter operation on the third row when reading out the fifth row + 7th row of the first frame. It is a block diagram which shows the structural example of the 3 plate-type imaging device which concerns on the application example of this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... CMOS image sensor, 11 ... Pixel array part, 12 ... Vertical scanning circuit, 13 ... Voltage level shift circuit, 14 ... Column circuit, 15 ... Horizontal scanning circuit, 16 ... Output circuit, 17 ... Timing generator, 20 ... Pixel, DESCRIPTION OF SYMBOLS 21 ... Photodiode, 22 ... Transfer transistor, 23 ... Reset transistor, 24 ... Amplification transistor, 31 ... Signal line, 32 ... Transfer control line, 33 ... Reset control line, 121 ... Reset address decoder (A), 122 ... Reset address Decoder (B), 123 ... Read address decoder (C)

Claims (7)

Pixel array including photoelectric conversion elements are two-dimensionally arranged in a matrix, and each pixel is arranged at an offset of ½ of the pixel pitch for each row and for each column;
In order to perform interlaced multiple row addition reading, it comprises vertical scanning means for selectively scanning each pixel of the pixel array section in units of rows,
The solid-state imaging device, wherein the vertical scanning unit performs pixel reset on the pixels in a specific row other than the plurality of rows selected for reading signals from the pixels. The vertical scanning means includes
A read address decoder for selecting the plurality of rows for reading signals from the pixels;
The solid-state imaging device according to claim 1, further comprising: a reset address decoder that selects the specific row for executing the pixel reset. The read address decoder
In the first frame, (1 line + 3 lines) → (5 lines + 7 lines) → (9 lines + 11 lines) →... And simultaneously (2 lines + 4 lines) → (6 lines + 8 lines) → (10 (Line + 12 lines) → Add 2 lines like
Next, in the second frame, (3 lines + 5 lines) → (7 lines + 9 lines) → (11 lines + 13 lines) →... And simultaneously (4 lines + 6 lines) → (8 lines + 10 lines) → (12 lines + 14 lines) → Add 2 lines like
3. The solid-state imaging device according to claim 2, wherein the interlaced two-row addition reading is executed by repeating the two-row addition reading thereafter. 3. The reset address decoder includes a plurality of address decoders, and the pixel reset is simultaneously performed on a plurality of rows in the same frame by row selection by the plurality of address decoders. Solid-state imaging device. The solid-state imaging device according to claim 2, wherein the reset address decoder selects the specific row for executing the pixel reset according to whether the current frame is an odd frame or an even frame. Solid-state imaging comprising a pixel array section in which pixels including photoelectric conversion elements are two-dimensionally arranged in a matrix and each pixel is arranged with a shift of ½ the pixel pitch for each row and for each column. A method for driving an apparatus, comprising:
In order to perform interlaced multiple-row addition readout, while selectively scanning each pixel of the pixel array section in units of rows,
A method for driving a solid-state imaging device, wherein pixel reset is executed for the pixels in a specific row other than the plurality of rows selected for reading signals from the pixels. Pixel array including photoelectric conversion elements are two-dimensionally arranged in a matrix, and each pixel is arranged at an offset of ½ of the pixel pitch for each row and for each column;
In order to perform interlaced multi-row addition readout, each pixel of the pixel array section is selectively scanned in units of rows, and the pixels of a specific row other than the plurality of rows selected to read out signals from the pixels are selected. An imaging apparatus comprising: a solid-state imaging device that includes a vertical scanning unit that performs pixel reset on a pixel.

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