JP2007012972A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

An object of the present invention is to stably manufacture a thin-structure FWD integrated IGBT having good electrical characteristics.
The FWD integrated IGBT of the present invention includes a p ⁺ high concentration collector layer 12 that determines the amount of holes injected, a p ⁻ low concentration collector layer 11 that absorbs variations in the grinding amount of the back surface of the wafer, and p ⁺ high. And an n ⁺ collector short-circuit region 13 penetrating the concentration collector layer 12 and the p ⁻ low concentration collector layer 11. Since the ohmic junction is formed with the p ⁻ low concentration collector layer 11 and the n ⁺ collector short-circuit region 13 by the collector electrode 31 made of, for example, aluminum after the back surface grinding, a high concentration layer for collector contact is separately formed. Ion implantation and heat treatment are not required.
[Selection] Figure 1

Description

  The present invention particularly relates to an insulated gate bipolar transistor (IGBT) integrated with a freewheeling diode (FWD) and a method for manufacturing the same.

  In recent years, it has been known that the trade-off relationship between the on-voltage and the turn-off time is improved by adopting a thin and low-injection efficiency structure in the IGBT collector region. This is because the IGBT can be speeded up without performing lifetime control due to the so-called transparent effect.

  On the other hand, in order to reduce the size and weight of power converters such as inverters, attempts have been made to integrate with FWD by a method such as providing a collector short-circuit region and shorting a drift layer to a collector electrode in an IGBT ( For example, see Patent Document 1 and Patent Document 2.)

  21 to 23 show a general process for forming a thin collector layer in a so-called non-punch through (NPT) type IGBT.

First, a semiconductor substrate 109 corresponding to the n ⁻ drift layer 114 is prepared, and then a MOS gate structure or the like is formed on the surface side of the substrate 109. Subsequently, the substrate 109 is ground to a thickness corresponding to the breakdown voltage class of the element (FIG. 21). Thereafter, p-type impurities are ion-implanted on the back side of the substrate, and the ions are activated by heat treatment (annealing) that does not affect the device structure on the element surface side, thereby forming the p ⁺ collector layer 112 (FIG. 22). . Finally, the collector electrode 131 is formed to complete the device (FIG. 23).

Here, at the time of ion implantation on the back surface, as shown in FIG. 24, an n ⁺ collector short-circuit region 113 is formed by adding a step of implanting an n-type impurity into a region different from that of the p-type impurity. Can also be produced.

  However, in this structure, for example, in the case of an element having a withstand voltage of 1200 V, since the total thickness of the IGBT is an extremely thin structure of about 150 μm, there is a problem that the wafer is easily cracked or chipped in the back surface ion implantation process. . In the case of an element having a withstand voltage of 600V, since the structure is thinner, there is a case where it cannot be processed by a normal ion implantation apparatus.

  Furthermore, in the annealing process after backside ion implantation, the processing temperature can be raised only to the extent that it does not affect the emitter electrode on the element surface side, and the activation rate of implanted ions is low. Therefore, a special apparatus such as a laser annealing apparatus is required for sufficient activation.

  Next, FIGS. 25 and 26 show one of the methods proposed for forming a thin collector layer in a so-called punch-through (PT) type IGBT.

First, a PT type IGBT manufactured using a thick p ⁺ substrate 209 is prepared. Usually, after this, lifetime control by heavy metal diffusion, particle beam irradiation, or the like is performed to complete the IGBT, but this is not performed here. Next, the p ⁺ substrate 209 is ground from the back side to form a p ⁺ collector layer 212 having a predetermined thickness (FIG. 25). Finally, a collector electrode 231 is formed to complete the device (FIG. 26).

  In this structure, there is no need to perform the ion implantation step after the device thickness is reduced, so that the chance of cracking or chipping of the wafer is reduced. Further, since an annealing process accompanying backside ion implantation is not required, an expensive apparatus such as a laser annealing apparatus is not required.

However, in this case, the final thickness of the p ⁺ collector layer 212 changes due to variations in the grinding amount of the back surface. Then, since the thickness of the region with the highest impurity concentration of the p ⁺ collector layer 212 changes, the amount of hole injection changes greatly. As a result, there arises a problem that even if the variation in the grinding amount of the back surface is ± 5 μm, the electrical characteristics of the obtained element deviate from the target value.

To solve this problem, the inventor of the present application has proposed the structure shown in FIG. 27 having a p ⁻ low-concentration collector layer 311 that absorbs variations in the amount of grinding of the back surface of the wafer (see, for example, Patent Document 3). .

  However, in the conventional method of forming the collector layer by back surface grinding, the collector short-circuit region cannot be formed, and it has been difficult to produce an FWD integrated IGBT.

Japanese Patent Laid-Open No. 61-15370 JP 2004-363328 A Japanese Patent Application No. 2004-65633

  As described above, the conventional IGBT having a thin collector layer requires ion implantation and heat treatment after thinning the wafer, and requires a special manufacturing apparatus corresponding to the thin wafer, or cracking the wafer. And has a problem that chipping easily occurs. For this reason, it is difficult to fabricate an FWD integrated IGBT.

  Further, in the conventional structure in which ion implantation is not performed after the wafer is thinned, the collector short-circuit region cannot be formed, and it is difficult to fabricate the FWD integrated IGBT.

  An object of the present invention is to provide a structure and a manufacturing method capable of stably producing a thin FWD integrated IGBT having good electrical characteristics.

  In order to achieve the above object, a semiconductor device according to the present invention has a first conductivity type low concentration collector layer having a relatively low impurity concentration and a relatively low impurity concentration formed on the upper surface of the low concentration collector layer. A high first-concentration type high-concentration collector layer; a second-concentration-type collector short-circuit region penetrating the low-concentration collector layer and the high-concentration collector layer at predetermined positions; and the high-concentration collector layer and the collector short-circuit region Gate structure including a second conductivity type drift layer formed on the top surface of the first conductivity type, a first conductivity type base region formed on the surface region side of the drift layer, a second conductivity type emitter region, and a gate electrode An emitter electrode formed to be electrically connected to the base region and the emitter region, and a collector formed on the lower surface of the low concentration collector layer and the collector short-circuit region It is and a pole.

  Therefore, even if the amount of grinding at the time of thinning the wafer varies, the change in the electrical characteristics of the element is small. Further, it is not necessary to perform ion implantation and heat treatment (annealing) accompanying the wafer after the wafer is thinned.

  According to the present invention, an element having a thin collector layer and uniform electrical characteristics can be obtained. In addition, a special ion implantation apparatus or the like for handling the thin wafer is not required. Further, there is no opportunity for cracking or chipping of the wafer during the annealing process. Accordingly, it is possible to stably manufacture an FWD-integrated IGBT having good and little variation in electrical characteristics at a low cost.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows the configuration of an FWD integrated IGBT according to a first embodiment of the present invention. A p base region 15, an n ⁺ emitter region 16, a gate insulating film 21, an interlayer insulating film 22, a gate electrode 32 and an emitter electrode 33 are formed on the surface region side of the n ⁻ drift layer 14. On the other hand, under the n ⁻ drift layer 14, the p ⁺ high concentration collector layer 12, the n ⁺ collector short-circuit region 13, the p ⁻ low concentration collector layer 11 and the collector electrode 31 are formed.

When the semiconductor device having the above configuration is turned on in the IGBT direction, first, electrons are injected from the n ⁺ emitter region 16 through the inversion layer of the p base region 15 into the n ⁻ drift layer 14, and the n ⁺ collector short-circuit region 13 is changed. Discharged through. Therefore, the first shows the MOSFET operation. Thereafter, when the current increases, the current flowing in the lateral direction on the p ⁺ high concentration collector layer 12 in the n ⁻ drift layer 14 also increases, and the voltage drop at this portion causes the p ⁺ high concentration collector layer 12 to increase. Becomes a forward bias state. As a result, holes are injected from the p ⁺ high-concentration collector layer 12 into the n ⁻ drift layer 14, conductivity modulation occurs, and an IGBT operation is exhibited.

Thus, when shifting from the MOSFET operation to the IGBT operation, a negative resistance characteristic called a so-called snapback as shown in FIG. 28 is shown. However, if this negative resistance region is large, a power loss is caused. Therefore, the negative resistance region needs to be reduced by setting the lateral size of the p ⁺ high concentration collector layer 12 to an appropriate value. The n ⁺ collector short-circuit region 13 is formed at a predetermined position in consideration of this.

Next, when the semiconductor device having the above-described configuration is turned on in the FWD direction, diode characteristics are obtained in which the emitter electrode 33 serves as an anode electrode and the collector electrode 31 serves as a cathode electrode. At this time, the n ⁺ collector short-circuit region 13 operates as the cathode region, but the p-type region electrically connected to the emitter electrode 33 in the portion not shown in the drawing and the p base region 15 operates as the anode region. To do.

2 to 7 show an example of a method for manufacturing the FWD integrated IGBT shown in FIG. First, as shown in FIG. 2, a substrate 9 is prepared, and a p ⁻ low concentration collector layer 11 is formed by epitaxial growth. In this case, the p ⁻ low concentration collector layer 11 can be formed by diffusion or the like, but in order to form the p ⁻ low concentration collector layer 11 having a constant concentration, it is desirable to use an epitaxial growth method. It will be readily understood that the above process can be omitted when the substrate 9 itself has a p-type impurity concentration corresponding to the p ⁻ low concentration collector layer 11.

Next, as shown in FIG. 3, an oxide film 23 having a thickness of 2 μm, for example, is formed on the surface of the p ⁻ low concentration collector layer 11. An opening for forming the n ⁺ collector short-circuit region 13 is formed in the oxide film 23.

Next, as shown in FIG. 4, phosphorus is introduced into the opening of the oxide film 23, and diffusion is performed at 1250 ° C. for about 12 hours. As a result, an n ⁺ collector short-circuit region 13 having a depth of about 30 μm is formed. Here, the oxide film 23 is removed after the introduction of phosphorus, and a thin oxide film (not shown) is formed on the surface of the p ⁻ low concentration collector layer 11 again, and then a high temperature and long time heat treatment is performed. Good. This thin oxide film can be used to prevent phosphorus from diffusing out during high-temperature and long-time diffusion, and also to prevent generation of crystal defects during ion implantation in the next process. Furthermore, since it is preferable that the n ⁺ collector short-circuit region 13 has a high concentration from the viewpoint of ohmic contact with the collector electrode, it is preferable to use a solid diffusion source or a liquid diffusion source for introducing phosphorus rather than an ion implantation method. desirable. Further, as shown in FIG. 8, the n ⁺ collector short-circuit region 13 may reach the substrate 9.

Subsequently, as shown in FIG. 5, after removing the oxide film 23, the p ⁺ high concentration collector layer 12 is formed by ion implantation and heat treatment. At this time, a photographic process may be added to prevent p-type impurities from entering the upper portion of the n ⁺ collector short-circuit region 13, but the process becomes complicated. Therefore, if ion implantation is performed on the entire surface with a dose such that the upper part of the n ⁺ collector short-circuit region 13 does not invert to the p-type, the p ⁺ high concentration collector layer 12 is partially formed without adding a photographic process. Is possible. Although the p ⁺ high concentration collector layer 12 can be formed by epitaxial growth or the like, it is desirable to use an ion implantation method in order to accurately form a high concentration and thin layer.

Next, as shown in FIG. 6, an n ⁻ drift layer 14 is formed on the p ⁺ high concentration collector layer 12 and the n ⁺ collector short-circuit region 13 by epitaxial growth. At this time, as shown in FIG. 9, when the n buffer layer 17 and the n ⁻ drift layer 14 are sequentially formed by epitaxial growth, a punch-through (PT) type element is obtained. However, the impurity concentration and thickness of the n ⁻ drift layer 14 in this case are adjusted to appropriate values for the PT type.

Next, as shown in FIG. 7, a MOS gate structure or the like is formed on the surface region side of the n ⁻ drift layer 14 by a known process. Thereafter, grinding, etching, or the like is performed from the back surface side of the substrate 9, and the n ⁺ collector short-circuit region 13 is exposed to the back surface, and at the same time, the p ⁻ low concentration collector layer 11 having a predetermined thickness is formed.

At this time, the predetermined thickness is determined from the amount of variation in grinding or etching of the back surface of the substrate. Although the p ^- low concentration collector layer 11 has a low impurity concentration, it increases the transparency of the collector layer as the thickness increases. Accordingly, it is desirable that the thickness be as thin as possible. However, if even a part of the p ⁺ high concentration collector layer 12 is removed due to grinding or etching variations on the back surface of the substrate, the electrical characteristics of the device will change significantly. . In order to avoid this, for example, if the amount of variation in grinding and etching of the back surface of the substrate is ± 5 μm, the predetermined thickness of the p ⁻ low-concentration collector layer 11 is set to about 5 μm.

Further, when the substrate 9 itself has a p-type impurity concentration corresponding to the p ⁻ low concentration collector layer 11, a part or all of the predetermined thickness is constituted by the remaining portion of the substrate 9. Also good.

Finally, the collector electrode 31 is formed in the p ⁻ low concentration collector layer 11 and the n ⁺ collector short-circuit region 13, and the FWD integrated IGBT of FIG. 1 is completed.

According to the IGBT having the above configuration, integration with the FWD is achieved by forming the n ⁺ collector short-circuit region 13. Further, even if the substrate back surface grinding amount varies, the thickness of the p ⁺ high concentration collector layer 12 does not change, and only the thickness of the p ⁻ low concentration collector layer 11 varies. Therefore, variation in the amount of injected holes is small. Furthermore, there is no step of ion implantation after thinning the substrate, and the manufacturing process becomes extremely easy.

Here, the collector electrode 31 forms an ohmic junction instead of a Schottky junction with respect to the p ⁻ low-concentration collector layer 11 and the n ⁺ collector short-circuit region 13, whereby the FWD integrated IGBT having the above configuration can be implemented. Become. Various electrode materials satisfying this condition are known, and one of them is aluminum.

For example, in the case of aluminum, as disclosed in Non-Patent Document 1, etc., an ohmic junction is formed on p-type silicon of 1.5 × 10 ¹⁶ cm ⁻³ on the low impurity concentration side. It is known that it does not become a non-ohmic junction for n-type silicon of 0.0 × 10 ¹⁹ cm ⁻³ . Therefore, from the viewpoint of the ohmic junction, the impurity concentration of the p ⁻ low concentration collector layer 11 is desirably 1.5 × 10 ¹⁶ cm ⁻³ or more, and the impurity concentration on the bottom exposed surface of the n ⁺ collector short-circuit region 13 Is preferably higher than 1.0 × 10 ¹⁹ cm ⁻³ . For this reason, the diffusion depth of the n ⁺ collector short-circuit region 13 is set to a considerably large value.

Corona, Power Devices and Power IC Handbook, 24 pages, Table 2.1

Furthermore, the collector electrode 31 is usually formed with a multilayer structure of dissimilar metals. Therefore, in the collector electrode 31 using aluminum, it is necessary that the metal layer in direct contact with the p ⁻ low-concentration collector layer 11 and the n ⁺ collector short-circuit region 13 contains aluminum, and this layer is pure aluminum or aluminum silicon. It is desirable to be an alloy. In addition, after the formation of the metal layer containing aluminum, for example, heat treatment at about 400 ° C. can be performed to further improve ohmic properties.

Next, a second embodiment of the present invention will be described. 10 to 12 show a method of manufacturing a semiconductor device according to the second embodiment of the present invention. First, as shown in FIG. 10, a substrate 9 is prepared, and an oxide film 23 having a thickness of 2 μm, for example, is formed on the surface thereof. Then, phosphorus is introduced into the opening formed in the oxide film 23, and an n ⁺ high concentration region 43 is formed.

Next, as shown in FIG. 11, after removing the oxide film 23, the p ⁻ low concentration collector layer 11 is formed on the surface of the substrate 9 by epitaxial growth, and then heat treatment is performed at 1250 ° C. for about 12 hours. As a result, the impurities in the n ⁺ high concentration region 43 are diffused into the p ⁻ low concentration collector layer 11, and the n ⁺ collector short-circuit region 13 is formed. Here, as in the first embodiment, a thin oxide film may be formed on the surface of the p ⁻ low-concentration collector layer 11 and then heat treatment for a long time at a high temperature may be performed. Thereafter, the FWD integrated IGBT shown in FIG. 12 is completed through the same processes as in FIGS. 5 to 7 of the first embodiment.

In Example 2, the shape of the n ⁺ collector short-circuit region 13 is different from that in Example 1, and as a result, the region of the p ⁻ low concentration collector layer 11 becomes smaller as it approaches the back surface of the wafer. Therefore, even if the amount of grinding or etching of the back surface of the substrate varies, the amount of change in the region of the p ⁻ low-concentration collector layer 11 is small, and an element with more uniform electrical characteristics than in the first embodiment can be obtained.

Subsequently, a third embodiment of the present invention will be described. 13 to 16 show a method of manufacturing a semiconductor device according to the third embodiment of the present invention. First, as shown in FIG. 13, a substrate 9 is prepared, and a first p ^- low concentration collector layer 41 is formed by epitaxial growth. In this case, in the same manner as in Example 1, the first p by diffusion or the like ^- although it is possible to form a low-concentration collector layer 41 a first p constant concentration ^- low concentration collector layer 41 formed For this purpose, it is desirable to use an epitaxial growth method. Further, when the substrate 9 itself has a p-type impurity concentration corresponding to the first p ^- low-concentration collector layer 41, the above process can be omitted as in the first embodiment.

Next, as shown in FIG. 14, an oxide film 23 having a thickness of 2 μm, for example, is formed on the surface of the first p ⁻ low concentration collector layer 41. Then, phosphorus is introduced into the opening formed in the oxide film 23, and an n ⁺ high concentration region 43 is formed.

Next, as shown in FIG. 15, after removing the oxide film 23, a second p ⁻ low concentration collector layer 42 is formed by epitaxial growth on the first p ⁻ low concentration collector layer 41, and then at 1250 ° C. Heat treatment is performed for about 3 hours. As a result, n ⁺ impurity of the high concentration region 43 is a second p ^- low concentration collector layer 42 and at the same time is diffused into the first p ^- diffused in a low concentration collector layer 41, n ⁺ collector short-circuit regions 13 It is formed. Here, as in the first embodiment, a high temperature heat treatment may be performed after a thin oxide film is formed on the surface of the second p ⁻ low concentration collector layer 42. Thereafter, the FWD integrated IGBT shown in FIG. 16 is completed through processes similar to those in FIGS. 5 to 7 of the first embodiment.

In Example 3, the n ⁺ collector short-circuit region 13 is formed by diffusion in both the upper and lower directions from the interface between the first p ⁻ low concentration collector layer 41 and the second p ⁻ low concentration collector layer 42. Therefore, the heat treatment time for forming the n ⁺ collector short-circuit region 13 is significantly shortened as compared with the case of the first and second embodiments. Further, since the amount of lateral diffusion of the n ⁺ collector short-circuit region 13 is also suppressed, the n ⁺ collector short-circuit region 13 can be miniaturized.

Further, if a photographic process is added in the process of FIG. 15 and diffusion and epitaxial growth are repeated as in the method of manufacturing the super junction structure, the diffusion amount in the lateral direction with respect to the depth direction can be increased as shown in FIG. It is also possible to form an extremely small n ⁺ collector short-circuit region 13.

Next, a fourth embodiment of the present invention will be described. FIG. 18 shows the configuration of an FWD integrated IGBT according to a fourth embodiment of the present invention. In contrast to the first embodiment of FIG. 1, an n buffer layer 17 having an impurity concentration higher than that of the n ⁻ drift layer 14 is provided on the p ⁺ high concentration collector layer 12.

By adopting such a configuration, since the IGBT becomes a punch-through (PT) type, the performance is improved. This is because in the NPT-IGBT, the n ⁻ drift layer 14 needs to have a sufficient thickness so that the depletion layer extending from the p base region 15 does not reach the p ⁺ high concentration collector layer 12. because of the n buffer layer 17 in -IGBT, n ^- is because it is sufficient to the minimum thickness required drift layer 14.

On the other hand, in the above configuration, since there is the n buffer layer 17 having a higher impurity concentration than the n ⁻ drift layer 14, the voltage drop due to the current flowing in the lateral direction on the p ⁺ high concentration collector layer 12 is reduced as it is. Therefore, the lateral size of the p ⁺ high concentration collector layer 12 needs to be set so that the negative resistance region in the electrical characteristics shown in FIG. 28 does not become large.

FIG. 19 shows another example of the fourth embodiment. After n buffer layer 17 is formed on the ^{p +} high-concentration collector layer 12 and the ^{n +} collector shorted region 13, n ^- the heat treatment for forming the drift layer 14 and MOS gate structure such as, ^{n +} collector short region This corresponds to the case where 13 is diffused to the n ⁻ drift layer 14 side over the n buffer layer 17.

Subsequently, a fifth embodiment of the present invention will be described. FIG. 20 shows the configuration of an FWD integrated IGBT according to a fifth embodiment of the present invention. In contrast to the first embodiment of FIG. 1, an n buried layer 18 having an impurity concentration higher than that of the n ⁻ drift layer 14 is formed at a position substantially at the bottom of the p base region 15.

With such a structure, p ⁺ high concentration from the collector layer 12 n ^- has the effect of being accumulated inside the drift layer 14 ^- holes injected into the drift layer 14, from the n-buried layer 18 n below As a result, conductivity modulation is promoted and the on-voltage of the IGBT is reduced. In particular, this is effective in the NPT type in which the thickness of the n ⁻ drift layer 14 is increased.

However, in the conventional method in which the concentration is increased to a position deeper than the p base region 15 by diffusion from the surface of the n ⁻ drift layer 14, the breakdown voltage is remarkably reduced, and conditions for double diffusion with the p base region 15 are obtained. There was a problem that it was difficult.

Therefore, in the present invention, during the epitaxial growth of the n ⁻ drift layer 14, the n buried layer 18 having a higher impurity concentration is formed by the epitaxial growth, and the remaining n ⁻ drift layer 14 is formed thereon. It has become.

  Although the planar gate type has been described above as an example, the present invention is not limited to the above-described embodiment, and it is obvious that the same effect can be obtained with the trench gate type. In the FWD integrated IGBT of the present invention, lifetime control such as heavy metal diffusion and particle beam irradiation may be performed in order to adjust the recovery characteristics as FWD. Furthermore, the FWD integrated IGBT of the present invention may be used as a so-called collector short type IGBT without FWD operation.

1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention. FIG. 7 is a cross-sectional view showing a manufacturing step of the semiconductor device shown in FIG. 1. FIG. 3 is a cross-sectional view showing a manufacturing step that follows FIG. 2. FIG. 4 is a cross-sectional view showing a manufacturing process subsequent to FIG. 3. It is sectional drawing which shows the manufacturing process following FIG. FIG. 6 is a cross-sectional view showing a manufacturing process subsequent to FIG. 5. FIG. 7 is a cross-sectional view showing a manufacturing step that follows FIG. 6. FIG. 4 is another cross-sectional view showing the manufacturing process following FIG. 3. FIG. 6 is another cross-sectional view showing the manufacturing process following FIG. 5. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 2nd Example of this invention. It is sectional drawing which shows the manufacturing process following FIG. FIG. 12 is a cross-sectional view showing a manufacturing step that follows FIG. 11. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 3rd Example of this invention. FIG. 14 is a cross-sectional view showing a manufacturing process subsequent to FIG. 13. It is sectional drawing which shows the manufacturing process following FIG. FIG. 16 is a cross-sectional view showing a manufacturing step that follows FIG. 15; FIG. 15 is another cross-sectional view showing the manufacturing process following FIG. It is sectional drawing of the semiconductor device which concerns on the 4th Example of this invention. It is another sectional view of a semiconductor device concerning the 4th example of the present invention. It is sectional drawing of the semiconductor device which concerns on the 5th Example of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device of a conventional structure. FIG. 22 is a cross-sectional view showing a manufacturing step that follows FIG. 21; FIG. 23 is a cross-sectional view showing a manufacturing step that follows FIG. 22; FIG. 22 is another cross-sectional view showing the manufacturing process following FIG. 21. It is sectional drawing which shows the manufacturing method of the semiconductor device of another conventional structure. FIG. 26 is a cross-sectional view showing a manufacturing step following FIG. 25. It is sectional drawing of the semiconductor device of another conventional structure. It is a figure which shows typically the negative resistance area | region in an output characteristic.

Explanation of symbols

9, 109, 209 Substrate 11, 311 Low-concentration collector layer 12, 312 High-concentration collector layer 13, 113 Collector short-circuit region 14, 114, 214, 314 Drift layer 15, 115, 215, 315 Base region 16, 116, 216, 316 Emitter region 17, 217, 317 Buffer layer 18 Buried layer 21, 121, 221, 321 Gate insulating film 22, 122, 222, 322 Interlayer insulating film 23 Oxide film 31, 131, 231, 331 Collector electrode 32, 132, 232 332 Gate electrode 33, 133, 233, 333 Emitter electrode 41 First low concentration collector layer 42 Second low concentration collector layer 43 High concentration region 112, 212 Collector layer

Claims (8)

A low-concentration collector layer of a first conductivity type having a relatively low impurity concentration;
A high-concentration collector layer of a first conductivity type formed on the upper surface of the low-concentration collector layer and having a relatively high impurity concentration;
A collector short-circuit region of a second conductivity type penetrating the low-concentration collector layer and the high-concentration collector layer at a predetermined position;
A drift layer of a second conductivity type formed on the upper surface of the high concentration collector layer and the collector short-circuit region;
A MOS gate structure including a first conductivity type base region formed on the surface region side of the drift layer, a second conductivity type emitter region, and a gate electrode;
An emitter electrode formed to be electrically connected to the base region and the emitter region;
A semiconductor device comprising: the low concentration collector layer; and a collector electrode formed on a lower surface of the collector short-circuit region.   The semiconductor device according to claim 1, wherein the collector electrode contains aluminum.   The semiconductor device further comprises a second conductivity type buffer layer formed on at least an upper surface of the high concentration collector layer of the high concentration collector layer and the collector short-circuit region and having a higher impurity concentration than the drift layer. 3. The semiconductor device according to 1 or 2. Forming a first conductivity type low concentration collector layer having a relatively low impurity concentration on the first surface of the first substrate;
Forming a mask having a part opened at a predetermined position of the low-concentration collector layer;
Diffusing impurities of the second conductivity type in the depth direction of the low-concentration collector layer from the opening of the mask to form a collector short-circuit region;
Removing the mask;
Forming a first conductivity type high concentration collector layer having a relatively high impurity concentration on the low concentration collector layer;
Forming a drift layer of a second conductivity type on the upper surface of the high concentration collector layer and the collector short-circuit region by epitaxial growth;
Forming a MOS gate structure including a first conductivity type base region, a second conductivity type emitter region, and a gate electrode on the surface region side of the drift layer;
Forming an emitter electrode electrically connected to the base region and the emitter region;
The collector short circuit region is formed by removing the first substrate and the low concentration collector layer from a second surface opposite to the first surface of the first substrate until the low concentration collector layer has a predetermined thickness. A step of exposing
Forming a collector electrode on an exposed surface of the low-concentration collector layer and the collector short-circuit region. Forming a mask partially opened at a predetermined position on the first surface of the first substrate;
Diffusing impurities of the second conductivity type from the opening of the mask in the depth direction of the first substrate to form a high concentration region;
Removing the mask;
Forming a low-concentration collector layer of a first conductivity type having a relatively low impurity concentration by epitaxial growth on the first surface of the first substrate;
A heat treatment step of diffusing impurities in the high concentration region into the low concentration collector layer to form a collector short-circuit region;
Forming a first conductivity type high concentration collector layer having a relatively high impurity concentration on the low concentration collector layer;
Forming a drift layer of a second conductivity type on the upper surface of the high concentration collector layer and the collector short-circuit region by epitaxial growth;
Forming a MOS gate structure including a first conductivity type base region, a second conductivity type emitter region, and a gate electrode on the surface region side of the drift layer;
Forming an emitter electrode electrically connected to the base region and the emitter region;
The collector short circuit region is formed by removing the first substrate and the low concentration collector layer from a second surface opposite to the first surface of the first substrate until the low concentration collector layer has a predetermined thickness. A step of exposing
Forming a collector electrode on an exposed surface of the low-concentration collector layer and the collector short-circuit region. Forming a first conductivity type first low-concentration collector layer having a relatively low impurity concentration on the first surface of the first substrate;
Forming a mask having a part opened at a predetermined position of the first low-concentration collector layer;
Diffusing impurities of a second conductivity type from the opening of the mask in the depth direction of the first low-concentration collector layer to form a high-concentration region;
Removing the mask;
Forming a first conductivity type second low concentration collector layer having an impurity concentration substantially the same as that of the first low concentration collector layer on the first low concentration collector layer by epitaxial growth;
A heat treatment step of diffusing the impurities in the high concentration region into the second low concentration collector layer to form a collector short-circuit region;
Forming a first conductivity type high concentration collector layer having a relatively high impurity concentration on the second low concentration collector layer;
Forming a drift layer of a second conductivity type on the upper surface of the high concentration collector layer and the collector short-circuit region by epitaxial growth;
Forming a MOS gate structure including a first conductivity type base region, a second conductivity type emitter region, and a gate electrode on the surface region side of the drift layer;
Forming an emitter electrode electrically connected to the base region and the emitter region;
The first substrate and the first low concentration collector layer are removed from a second surface opposite to the first surface of the first substrate until the first low concentration collector layer has a predetermined thickness. And exposing the collector short-circuit region,
Forming a collector electrode on an exposed surface of the first low-concentration collector layer and the collector short-circuit region.   7. The semiconductor device according to claim 4, wherein the step of forming the drift layer by epitaxial growth comprises a step of sequentially forming a second conductivity type buffer layer having a higher impurity concentration than the drift layer and the drift layer. Production method.   The step of forming the drift layer by epitaxial growth further comprises the step of forming a buried layer of a second conductivity type having an impurity concentration higher than that of the drift layer by epitaxial growth at a position substantially at the bottom of the base region. A method for manufacturing a semiconductor device according to claim 4.

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