JP2007012725A - Semiconductor device - Google Patents

Abstract

[PROBLEMS] To improve package reliability by effectively relieving thermal stress generated at a junction with an insulating substrate while ensuring high heat dissipation by simply changing the structure of a metal base for heat dissipation. To be able to plan.
In a semiconductor device in which a semiconductor chip is mounted on a ceramic insulating substrate and the insulating substrate is bonded (for example, soldered) to a heat radiating metal base (copper material), the upper surface of the heat radiating metal base is formed. The thermal stress reducing groove 1a is formed in the outer peripheral side so as to surround the bonding surface area with the insulating substrate so as not to overlap with the bonding surface area, and the apparent inner peripheral portion of the groove is used as a boundary. The deformation rigidity is lowered, and thermal stress acting on the joint between the metal base and the insulating substrate is reduced by thermal cycling.
[Selection] Figure 1

Description

  The present invention relates to a power semiconductor device having a package structure in which a power semiconductor chip is mounted on an insulating substrate having a conductor pattern formed on both surfaces of a ceramic substrate, and the insulating substrate is mounted and bonded to a heat radiating metal base.

First, a conventional package structure of the head semiconductor device is shown in FIG. In the figure, 1 is a heat-dissipating metal base (heat sink) made of a copper material, 2 is an insulating substrate (for example, Direct Copper Bonding substrate) in which a conductor pattern (copper foil) 4 is formed on both sides of a ceramic substrate 3, 5 Is a semiconductor chip such as IGBT, 6 is a metal base / insulating substrate, a bonding material (for example, solder material) bonded between the insulating substrate / semiconductor chip, 7 is an external terminal, 8 is a bonding wire, 9 is an enclosing case, 10 is a gel filler, 11 is a case lid, and 12 is a sealing resin.
With the above configuration, the heat generated in the semiconductor chip 5 due to energization is transferred to the metal base 1 through the insulating substrate 2, and is radiated outside the system through the radiation fins (not shown).
By the way, in the above semiconductor device, it is constructed by combining components having different thermal expansion coefficients (a copper metal radiating metal base 1 and a ceramic insulating substrate 2). Due to the difference in expansion coefficient, thermal stress is generated at the joint between the parts. Here, when the bonding material is, for example, solder, fatigue failure occurs in the solder layer due to repeated action of thermal stress, cracking, peeling of the solder, and the like, increasing the thermal resistance of the heat transfer path of the package. In addition, heat dissipation may be reduced, and the semiconductor chip may be thermally destroyed. It should be noted that, even in a structure in which the members are directly joined without using solder joining, there is a concern that similar interface deterioration of the joint portion may occur due to thermal stress caused by a difference in thermal expansion coefficient between components.

Next, the generation mechanism of thermal stress generated at the junction between the metal base 1 and the ceramic insulating substrate 2 in the package structure of FIG. 4 will be described with reference to FIG. In FIG. 5, the ceramic substrate is soldered to the metal base for heat dissipation, and the cross section in the stacking direction is simulated as a central object. Here, the linear expansion coefficient α2 (16.5 × 10 ⁻⁶ / ° C.) of the metal base (copper material) 1 is the linear expansion coefficient α1 (7.1 × 10 ⁻⁶ / ° C.) of the ceramic substrate (Al ₂ O ₃ ). ), And the amount of thermal expansion due to the temperature rise (temperature T) due to the heat generation of the semiconductor chip is α2 · T · L> α1 · T · L. A shearing force F from the center of the substrate to the outer peripheral side and a lower surface side interface from the outer peripheral side to the center is applied to the upper surface side interface of 6.
In this case, since the bonding material (solder material) 6 has a lower elastic modulus than the material of the metal base 1 and the ceramic substrate 2, the shear strain acts greatly on the layer of the bonding material 6, and this shear strain is a thermal cycle. If the action is repeated, the joining material 6 is fatigued and causes deterioration of the joint as described above.

On the other hand, since the thermal stress acting on the junction between the metal base and the insulating substrate is caused by the difference in coefficient of thermal expansion of the component as described above, the metal base (heat sink) is made of Cu-W, Cu-Mo, or the like. It is also adopted as a part of a product that is made of a material having a low thermal expansion coefficient and reduces the thermal stress by reducing the difference in thermal expansion coefficient from the ceramic substrate.
Further, although not directly related to the above-described thermal stress mitigation measures for the solder joint portion, in the case of a semiconductor device having a package structure similar to that of FIG. 4, soldering is performed when soldering between the metal base 1 for heat dissipation and the insulating substrate 2. Aiming at preventing the occurrence of defective soldering, solder grooves (for example, groove width 2 mm, groove depth 0) are formed on the upper surface of the metal base at positions along the outer peripheral edge of the lower surface electrode (conductor pattern) of the insulating substrate. .1mm groove), and a part of the molten solder is consciously poured into the solder groove during the solder joining process to prevent unnecessary solder from protruding to the outer periphery. Is known (see, for example, Patent Document 1).
JP-A-9-162237 (FIGS. 2 and 3)

Incidentally, in the semiconductor device having the package structure shown in FIG. 4, as a measure for alleviating thermal stress acting on the joint between the heat-dissipating metal base 1 and the ceramic insulating substrate 2 during the thermal cycle, the metal base is used as described above. In addition to the high cost of components, the configuration employing a material with low thermal expansion coefficient such as Cu-W, Cu-Mo, etc. has a low thermal conductivity as compared with copper material. In order to be applied to a power semiconductor device such as a module, it is necessary to reduce the thickness of the metal base and reduce the thermal resistance against the heat flux from the semiconductor chip to the same level as the copper metal base. However, if the thickness of the metal base is reduced, the heat dispersibility in the surface direction of the heat flux that is transferred from the semiconductor chip to the metal base through the insulating substrate is reduced, so that high heat dissipation can be ensured in total. There is a problem that becomes difficult.
The present invention has been made in view of the above points, and while ensuring high heat dissipation by simply changing the structure of the metal base for heat dissipation without adopting a material having a low coefficient of thermal expansion as described above. Another object of the present invention is to provide an improved semiconductor device that can effectively reduce thermal stress generated at a junction with an insulating substrate and improve the reliability of the package.

In order to achieve the above object, according to the present invention, in a semiconductor device in which an insulating substrate in which a conductor pattern is formed on both sides of a ceramic substrate is bonded to a metal base for heat dissipation,
On the upper surface of the heat dissipating metal base, a thermal stress relief groove is formed on the outer peripheral side of the outer peripheral side so as to surround the joint surface area with the insulating substrate. It shall be formed in the manner as described above.
(1) The thermal stress relaxation groove is a concave groove having a U-shaped section or a V-shaped cross section, and the concave groove is formed at a position close to the outer peripheral side so as not to overlap the bonding surface area with the insulating substrate. Item 2).
(2) The depth of the thermal stress relaxation groove is set to 30% to 50% of the thickness of the metal base (claim 3).
(3) The thermal stress relaxation groove is recessed in an inner and outer double.

As described above, a thermal stress relief groove is formed on the surface of the metal base for heat dissipation so as to surround the joint portion (including solder joint and direct joint) with the insulating substrate, so that the inner periphery of the heat sink relief groove The area between the joint surface area on the side and the area on the outer peripheral side is divided. In addition, the notch effect due to the groove formation is added, and the apparent deformation rigidity of the inner peripheral side of the groove is reduced (lower elastic modulus) compared to the solid metal base that does not form the groove, and the acting force in the surface direction reduces the groove The inner peripheral side portion is easily slipped and deformed.
As a result, in the assembled state of the semiconductor device in which the ceramic insulating substrate on which the semiconductor chip is mounted is bonded onto the metal base, the difference between the thermal expansion coefficient between the metal base and the ceramic substrate causes a difference between the metal base and the insulating substrate during the thermal cycle. Even if thermal stress acts on the joint, shearing strain generated in the joint is reduced by the function of the groove, and interface deterioration of the joint can be effectively suppressed, and the durability and reliability of the package are improved.

In addition, by defining the depth of the thermal stress relaxation groove in the range of 30 to 50% of the thickness of the metal base, it is possible to ensure high heat dissipation and heat dispersibility required for the heat sink of the power semiconductor device.
In addition, by forming the thermal stress relief groove in the inner and outer double, when the metal base and the insulating substrate are soldered, a part of the molten solder is unexpectedly formed in the inner circumferential groove during the soldering process. Even if the groove is filled and the groove is buried and the thermal stress relaxation function of the groove does not sufficiently function, the outer peripheral groove (empty groove) can serve as a backup groove to ensure the thermal stress relaxation function.

  DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below based on the examples shown in FIGS. In the drawings of the respective embodiments, the same reference numerals are given to members corresponding to those in FIG. 4 and description thereof is omitted.

1A and 1B, the upper surface of the heat-dissipating metal base 1 on which the ceramic insulating substrate 2 is mounted in the package structure of FIG. 4 includes a bonding surface area (solder bonding and direct bonding) with the insulating substrate 2. ) Is provided on the outer peripheral side of the metal base 1 and the metal base 1 including the joint surface area is divided between the inner peripheral side and the outer peripheral side, and no groove is formed. Compared to a solid body, the apparent deformation rigidity of the inner peripheral side area is reduced.
Here, the thermal stress relaxation groove 1a is a groove having a U-shaped section (or a V-shaped section), and the depth of the groove is set in a range of 30 to 50% of the plate thickness of the metal base 1, for example, When the plate thickness is 3 mm, the thermal stress relaxation groove 1 a having a groove depth of 0.9 to 1.5 mm and a groove width of 0.5 mm is 0 along the outer periphery of the joint surface (in the case of solder joint, the outer periphery including the solder fillet). It is formed in an outer peripheral range of ˜1 mm (a position 0.5 mm away from the outer peripheral edge of the joint surface so that the solder does not flow into the groove in consideration of the spread of the solder fillet).

Next, the thermal stress relieving function by the above structure will be described with reference to FIGS. First, FIG. 3A is an enlarged view schematically showing the main structure of FIG. 1 in a module assembly state (normal temperature), and the bonding material 6 between the metal base 1 and the insulating substrate 2 is solder. It is a material. It should be noted that when the solder is joined to the thermal stress mitigating groove 1a beyond the joint surface area with the insulating substrate 2 and the groove is filled, the thermal stress mitigating function does not work effectively, so the amount of solder is appropriate. It is preferable to take measures to prevent the spread of the molten solder before the projection by forming a dam-like projection along the inner peripheral side of the groove.
Regarding the groove structure described above, in Patent Document 1 described above, solder grooves are formed on the upper surface of the metal base so as to surround the periphery of the solder joint portion with the insulating substrate. At this time, a flux is applied to the solder groove so that a part of the molten solder is actively drawn into the solder groove. The purpose and function of the thermal stress relaxation groove 1a formed in the metal base 1 in the embodiment of the present invention is as follows. Is different.

  Then, when the temperature of the metal base 1 and the ceramic insulating substrate 2 rises from the state of FIG. 3 (a) in the thermal cycle accompanying the energization / non-energization of the semiconductor chip, as shown in FIG. Thermal stress is generated at the bonding interface of the bonding material 6 due to the difference in thermal expansion coefficient between the ceramic material of the substrate 2 and the thermal expansion of the metal base 1 at the interface between the metal base 1 and the bonding material 6 in this case. Since the stress acts to counteract the above, the inner peripheral side portion (low deformation rigidity) of the metal base 1 divided by the thermal cycle relaxation groove 1a is slip-deformed as shown in FIG. To do. As a result, the shear strain acting on the upper and lower interfaces of the bonding material 6 due to the difference in thermal expansion is reduced, and the interface deterioration of the bonded portion between the metal base and the insulating substrate is effectively suppressed. According to the analysis result conducted by the inventor about this point, by forming a thermal stress relaxation groove having a groove depth of 1.5 mm and a groove width of 5 mm on a metal base having a thickness of 3 mm, the bonding solder layer is formed during thermal cycling. It has been confirmed that the applied thermal stress is reduced by about 25% compared to the conventional structure.

  Even when the metal base 1 / insulating substrate 2 are directly bonded without using solder bonding, the thermal stress acting on the bonded portion can be alleviated and deterioration of the bonding interface can be prevented as described above.

FIGS. 2A and 2B are configuration diagrams of an embodiment corresponding to claim 4 of the present invention. As the thermal stress relaxation groove described in the first embodiment, the metal base 1 has two inner and outer surfaces. Heavy grooves 1a and 1b are formed.
With this configuration, when the insulating substrate 2 is soldered to the metal base 1, the outer peripheral groove 1 b is backed up even if a part of the molten solder flows into the inner peripheral thermal stress reducing groove 1 a and fills the groove. Thus, the thermal stress mitigating function of the joint can be maintained.

BRIEF DESCRIPTION OF THE DRAWINGS It is principal part structure drawing of the semiconductor device corresponding to Example 1 of this invention, (a) is a top view, (b) is XX sectional drawing of the arrow of (a). FIG. 7 is a structural diagram of a principal part of a semiconductor device corresponding to Example 2 of the present invention, where (a) is a plan view and (b) is a cross-sectional view taken along line XX in (a). FIG. 2 is an explanatory diagram of a thermal stress mitigation function by the structure of FIG. 1, and (a) and (b) are diagrams schematically showing states at normal temperature and elevated temperature, respectively. Sectional drawing of the conventional assembly structure of the semiconductor device used as the implementation object of this invention Explanatory drawing of the generation mechanism of thermal stress generated at the junction between the metal base and the insulating substrate at the time of temperature rise in the structure of FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Metal base for heat dissipation 1a, 1b Thermal stress relaxation groove | channel 2 Insulation board | substrate 3 Ceramic board | substrate 4 Conductor pattern 5 Semiconductor chip 6 Joining material (solder material)

Claims (4)

In a semiconductor device in which an insulating substrate having a conductor pattern formed on both sides of a ceramic substrate is joined to a metal base for heat dissipation,
A semiconductor device characterized in that a heat stress relaxation groove is provided on the outer peripheral side of the upper surface of the heat dissipating metal base so as to surround a joint surface area with an insulating substrate. 2. The semiconductor device according to claim 1, wherein the thermal stress relaxation groove is a concave groove having a U-shaped section or a V-shaped cross section, and the concave groove is positioned close to the outer peripheral edge so as not to overlap with a bonding surface area with the insulating substrate. A semiconductor device formed. 3. The semiconductor device according to claim 1, wherein the depth of the thermal stress relaxation groove is set to 30% to 50% of the thickness of the metal base. 4. The semiconductor device according to claim 1, wherein the thermal stress relief grooves are recessed in an inner and outer double.

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