JP2007011938A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent collective erasure of a non-volatile memory in an undesiredly large address range. <P>SOLUTION: This semiconductor integrated circuit has the non-volatile memory having electrically rewritable non-volatile memory cells. The non-volatile memory performs the erasure of storage information to the non-volatile memory cells in erasure block units having different size. The non-volatile memory has an endian conversion circuit 25 capable of selecting exchange between an upper bit and a lower bit to all bits of an address signal a0-ai inputted from an address input terminal. When it is possible to perform the exchange between the upper bit and the lower bit to all the bits of the inputted address signal even if endian of the non-volatile memory and endian of an access subject thereof differ, address allocation directions to a data area are equalized in both of the non-volatile memory and the access subject. Even if the erasure block size differs according to an address area, an address map of the erasure block does not differ between the non-volatile memory and the access subject. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an endian conversion technique in a semiconductor integrated circuit, for example, a technique effective when applied to a data processor including a flash memory and a central processing unit.

  There are two modes for address assignment to the data area. One is a little endian that assigns a small address to the lower side of the data area, and the other is a big endian that assigns a large address to the lower side of the data area. Considering the form of data transfer from the lower address side on the data bus, for example, when transferring multiple bytes of data over the bus in multiple batches, little endian sequentially transfers from the lower byte, and big endian sequentially transfers the upper byte. Will be transferred from. Therefore, if the endian recognition does not match between the bus master and the bus slave, a malfunction occurs.

  With respect to the endian difference, the technique described in Patent Document 1 performs a big-endian operation for data transfer on a data bus having a bus width of 32 bits or less by performing an exclusive OR operation on the lower 2 bits of an address with an endian mode signal. And support for both little endian. Patent Document 2 describes that the same means is taken for the lower 1 bit of the address. Both descriptions are positioned as endian converters arranged in the middle of an address bus connecting a multi-chip memory and a CPU.

JP 2004-355432 A JP 2001-26150 A

The present inventor has extensively studied not only endian matching at the transfer source and transfer destination in data transfer but also endian matching for the data area such as the storage area of the flash memory. For example, for the allocation of the CPU logical address to the storage area of the flash memory, even if the same access address from the CPU depends on whether the physical address map of the flash memory is big endian or little endian, The physical area of the specified flash memory will be different. At this time, some flash memories have different erase block sizes, which are used as a batch erase unit, depending on the address area. Then, there are cases where the sizes of erase blocks including the same erase address designated in the erase operation are different between those having different endian in the physical address map of the flash memory. As a result, between the CPU and the flash memory having different endians, there is a possibility that batch erasure is performed undesirably in a wide address range when rewriting stored information. As a result, information written in the flash memory may be erased undesirably. Conversely, when the CPU was scheduled to perform batch erasure over a wide address range, the erase block in the narrow address range of the flash memory is targeted for erasure, and as a result, the information written in the flash memory is not erased. There is a possibility that the writing to the flash memory is not guaranteed. Therefore, it is necessary to perform a batch erase operation a plurality of times.
In order to deal with these problems, it is not sufficient to simply invert the logical value of the lower address bits in accordance with the bus width such as endian matching on the data bus.

  In addition, when designing a semiconductor integrated circuit by putting a plurality of circuit modules on-chip, the byte of the internal data bus is used for a minority circuit module having a different endian in response to a difference in endian in the plurality of circuit modules. Connections with lower addresses corresponding to the number of address bits necessary to express the width can be corrected each time. However, even for endian matching in data transfer, such a countermeasure not only increases the design man-hours and verification man-hours, but also increases the types of circuit modules as design components each time, and circuit modules as design assets. Data management is also complicated.

  An object of the present invention is to prevent batch erasure of a non-volatile memory from an undesirably large address range, or to perform erasure multiple times in an undesirably narrow address range. A semiconductor integrated circuit capable of preventing the failure to be provided is provided.

  Another object of the present invention is to provide a semiconductor integrated circuit that can contribute to avoiding an increase in design man-hours and verification man-hours due to endian matching and an increase in the types of circuit modules as design parts. It is in.

  Still another object of the present invention is to provide a semiconductor integrated circuit that can cope with endian change regardless of the number of parallel bits of input / output data.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  [1] A semiconductor integrated circuit (1) according to the present invention includes a nonvolatile memory (4) including a plurality of nonvolatile memory cells (13) that can electrically rewrite stored information. The nonvolatile memory erases stored information in the nonvolatile memory cells in units of erase blocks (EB0 to EB4) having different sizes. The non-volatile memory has an endian conversion circuit capable of selecting logical value inversion for all bits of an address signal input from the address input terminal.

  From the above, when the endian of the nonvolatile memory is different from the endian of the access subject, the logical value inversion for all the bits of the input address signal may be performed by the endian conversion circuit. As a result, the address allocation direction for the data area becomes equal in both the nonvolatile memory and the access subject. Therefore, even if the size of the erase block as a batch erase unit in the nonvolatile memory is different depending on the address area, the address map for the erase block having a different size is different between the nonvolatile memory and the access subject. Absent. Therefore, it is possible to prevent batch erasing from an undesirably large address range to a non-volatile memory, or to perform erasing multiple times in an undesirably narrow address range. Can be prevented.

  Furthermore, when designing a semiconductor integrated circuit by making a plurality of circuit modules on-chip, even if the nonvolatile memory is a minority circuit module different from the endian of another circuit module, the nonvolatile memory is an endian conversion circuit. Therefore, it is not necessary to modify the address wiring pattern in the nonvolatile memory and replace the bits. It is only necessary to select address replacement for the endian conversion circuit held in the nonvolatile memory. It is not necessary to increase the types of non-volatile memories as design parts for endian matching.

  In the above, since the logical values of all address bits can be inverted, it is possible to cope with the case where the minimum data word specified by the lower address is the minimum erase unit. The upper and lower arrangement and transfer order of data transferred in a plurality of times on the data bus can be aligned regardless of the number of bits of the data bus.

  In the above, when the number of address bits to be inverted by the endian conversion circuit is minimized in consideration of the minimum size of the erase unit and the data bus width, the following is performed. That is, the endian conversion circuit generates all address bits higher than the lower address corresponding to the number of bits necessary to represent the minimum number of data words of the erase block in the address signal input from the address input terminal of the nonvolatile memory. And all the lower-order addresses corresponding to the number of bits necessary to represent the number of parallel data words input / output at the data input / output terminal of the nonvolatile memory among the address signals input from the address input terminal of the nonvolatile memory. Any logic inversion with respect to the address bits can be selected.

  As one specific form of the present invention, a predetermined nonvolatile memory cell in the nonvolatile memory serves as a storage area for control data for selecting a logical value inversion of an address bit in the endian conversion circuit. At this time, for example, the non-volatile memory may read the control data from a predetermined non-volatile memory cell in response to a reset instruction and set it in the endian conversion circuit.

  Even when the physical endian of the CPU and the flash memory match, the allocation of the erase unit size in the logical address space of the program executed by the CPU is the same as the physical erase unit of the flash memory. Even in different cases, the endian conversion circuit may be provided in order to replace the address of the flash memory. As a result, it is possible to assign an appropriate erasing unit without modifying an existing program.

  [2] A semiconductor integrated circuit according to another aspect of the present invention can access the non-volatile memory together with a non-volatile memory having a plurality of non-volatile memory cells that can electrically rewrite stored information. It has a data processing unit. The nonvolatile memory erases stored information from the nonvolatile memory cells in units of erase blocks having different sizes. The semiconductor integrated circuit includes the endian conversion circuit capable of selecting logical value inversion for all bits of an address signal transmitted from the data processing unit to the nonvolatile memory via an internal address bus.

  From the above, when the endian of the nonvolatile memory and the endian of the data processing unit are different, the logic value inversion for all bits of the input address signal may be performed by the endian conversion circuit. As a result, the address allocation direction for the data area is equal in both the nonvolatile memory and the data processing unit. Therefore, even if the size of the erase block as a batch erase unit in the nonvolatile memory is different depending on the address area, the address map for the erase block having a different size is different between the nonvolatile memory and the data processing unit. Absent. Therefore, it is possible to prevent batch erasing from being performed in an undesirably large address range with respect to the nonvolatile memory.

  In the above, since the logical values of all address bits can be inverted, it is possible to cope with the case where the minimum data word specified by the lower address is the minimum erase unit. The upper and lower arrangement and transfer order of data transferred in a plurality of times on the data bus can be aligned regardless of the number of bits of the data bus.

  In the above, when the number of address bits to be inverted by the endian conversion circuit is minimized in consideration of the minimum size of the erase unit and the data bus width, the following is performed. That is, the endian conversion circuit generates all address bits higher than the lower address corresponding to the number of bits necessary to represent the minimum number of data words of the erase block in the address signal input from the address input terminal of the nonvolatile memory. And all the lower-order addresses corresponding to the number of bits necessary to represent the number of parallel data words input / output at the data input / output terminal of the nonvolatile memory among the address signals input from the address input terminal of the nonvolatile memory. Any logic inversion with respect to the address bits can be selected.

  As one specific form of the present invention, a predetermined nonvolatile memory cell in the nonvolatile memory serves as a storage area for control data for selecting a logical value inversion of an address bit in the endian conversion circuit. At this time, for example, the non-volatile memory may read the control data from a predetermined non-volatile memory cell in response to a reset instruction and set it in the endian conversion circuit.

  As a more specific form of the present invention, the nonvolatile memory or the data processing unit includes the endian conversion circuit. As a result, when designing a semiconductor integrated circuit by making a plurality of circuit modules on-chip, for the minority circuit modules having different endians, the number of bits required to represent the byte width of the internal data bus is obtained. It is not necessary to replace the lower address by modifying the wiring pattern. It is only necessary to select the logical value inversion of the address bits for the endian conversion circuit possessed by the nonvolatile memory or the data processing unit. It is not necessary to increase the types of nonvolatile memories and data processing units as design parts for endian matching.

  [3] A semiconductor integrated circuit according to still another aspect of the present invention includes an internal bus and a bus master module and a bus slave module coupled to the internal bus on a semiconductor substrate. The bus master module or the bus slave module has an endian conversion circuit. This endian conversion circuit can selectively switch between a little endian that assigns a small address to the lower side of the data area and a big endian that assigns a large address to the lower side of the data area for address assignment to the data area of the bus slave module. To.

  Since the bus master module or the bus slave module has an endian conversion circuit, when trying to design this semiconductor integrated circuit, a minority circuit module having a different endian is used to lower the number of bits corresponding to the byte width of the internal data bus. It is not necessary to replace the side address for the correction of the wiring pattern. It is only necessary to select endian switching for the endian conversion circuit held in the nonvolatile memory or the data processing unit. It is not necessary to increase the types of bus master modules or bus slave modules as design parts for endian matching.

  As one specific form of the present invention, the endian conversion circuit can select logical value inversion for all bits of an address signal transmitted through an internal bus. As a result, the address allocation direction for the data area is equal in both the bus master module and the bus slave module.

  As another specific form of the present invention, the endian conversion circuit includes, on the lower side, the number of address bits necessary to represent the number of parallel data words transmitted on the internal bus among the address signals transmitted on the internal bus. The logical value inversion of all address bits of the address can be selected. It is possible to easily cope with the case where the upper and lower orders of data transferred in multiple times via the internal bus are reversed.

  As yet another specific form of the present invention, the bus slave module is a non-volatile memory including a plurality of non-volatile memory cells in which stored information can be electrically rewritten. The bus master module is a data processing unit that can access the nonvolatile memory. The nonvolatile memory erases stored information from the nonvolatile memory cells in units of erase blocks having different sizes. The endian conversion circuit transmits all the address bits higher than the lower address corresponding to the number of bits required to represent the minimum number of data words of the erase block among the address signals transmitted on the internal bus, and is transmitted on the internal bus. It is possible to select logical value inversion with respect to all address bits of lower addresses corresponding to the number of bits necessary to represent the number of parallel data words transmitted through the internal bus. As a result, even if the size of the erase block as a batch erase unit in the nonvolatile memory is different depending on the address area, the address map for the erase block having a different size is different between the nonvolatile memory and the access subject. There is no. Therefore, it is possible to prevent batch erasing from being performed in an undesirably large address range with respect to the nonvolatile memory.

  As a more specific form of the present invention, a predetermined nonvolatile memory cell in the nonvolatile memory serves as a storage area for control data for selecting logical value inversion of address bits in the endian conversion circuit. At this time, the nonvolatile memory may read the control data from a predetermined nonvolatile memory cell in response to a reset instruction and set it in the endian conversion circuit.

  As a more specific form of the present invention, a minority module having a different endian among the bus slave module and the bus master module in which big endian and little endian are mixed has the endian conversion circuit.

  [4] A semiconductor integrated circuit according to still another aspect of the present invention includes a non-volatile memory (4) having a plurality of non-volatile memory cells, and a plurality of non-volatile memories accessible via an address bus and a data bus. Circuit module. The first circuit module (2) outputs first address information to the address bus for accessing the first nonvolatile memory cell via the data bus. The second circuit module (3) outputs second address information to the address bus for accessing the first nonvolatile memory cell via the data bus. And it has a converter (25A) which performs control which converts the 2nd address information into the 1st address information according to the 1st status signal, and does not convert according to the 2nd status signal.

  As a specific form, the first circuit module outputs the second state signal, and the second circuit module outputs the first state signal.

  As a specific form, the non-volatile memory may generate the first non-volatile memory from first row address information and first column address information included in the first address information in response to input of the first address information. Select a memory cell.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, it is possible to prevent the batch erase from being performed in an undesirably large address range with respect to the nonvolatile memory.

  This can contribute to avoiding an increase in design man-hours and verification man-hours due to endian matching, and an increase in the types of circuit modules as design parts.

  Since all the bits of the address signal can be exchanged between upper and lower, it is possible to cope with endian changes regardless of the number of parallel bits of input / output data.

  FIG. 2 shows a data processor as an example of a semiconductor integrated circuit. The circuit elements constituting the data processor are formed on a single semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit technology such as a CMOS (complementary MOS transistor) or a bipolar transistor.

  The data processor (MPU) 1 has a central processing unit (CPU) 2 and a direct memory access controller (DMAC) 3 which are representatively shown as a bus master module. As a bus slave module, the data processor 1 typically includes a flash memory (FLASH) 4, a random access memory (RAM) 5, a timer (TMR) 6, a phase-locked loop circuit (PLL) 7, which are typically shown as nonvolatile memories. Port circuits (PRT) 8 and 9 are provided. These circuit modules 2 to 9 share the internal bus 10. The internal bus 10 is a set of signal lines for address, data, and bus control signals.

  The CPU 2 includes an instruction control unit that controls an instruction execution procedure, and an instruction execution unit that executes a command by performing memory access or calculation based on a control signal from the instruction control unit. The RAM 5 is used as a work area for the CPU 2 or a temporary storage area for data. The DMAC 3 performs access control for memory access and the like based on the initial setting by the CPU 2. The PLL 7 generates an operation reference clock for the CPU 2 or the like based on the original oscillation generated by the vibrator connected to the terminals XTAL / EXTAL. The port circuits 8 and 9 are used for an interface with the outside. The timer 6 performs a timer operation such as counting up or input capture. The flash memory 4 is used for holding programs and data. Vcc is an external power supply terminal, Vss is an external ground terminal, STBY is a standby signal, and RES is a reset signal.

  FIG. 3 shows an example of the flash memory 4. The flash memory 4 has a memory array (MARY) 12 in which a large number of nonvolatile memory cells are arranged in a matrix. In the figure, one nonvolatile memory cell 13 is typically shown. The non-volatile memory cell 13 illustrated in the figure is configured by an insulated gate n-channel field effect transistor having a two-layer gate structure, although not particularly limited. The nonvolatile memory cell 13 has, for example, a floating gate on a channel formation region between a source and a drain through a thin gate oxide film as a tunnel insulating film, and a control gate on the insulating gate. Is provided. This information writing operation to the non-volatile memory cell 13 is realized, for example, by applying a high voltage to the control gate and drain and injecting electrons from the drain side to the floating gate by avalanche injection. By this writing operation, the threshold voltage of the nonvolatile memory cell viewed from the control gate is made higher than the threshold voltage in the erased state where the writing operation is not performed. On the other hand, the erase operation is realized, for example, by applying a high voltage to the source and extracting electrons from the floating gate to the source side by a tunnel phenomenon. The threshold voltage seen from the control gate of the nonvolatile memory cell is lowered by the erase operation. The read operation is performed by giving the control gate a word line selection level between the threshold voltage distribution of the nonvolatile memory cell in the erased state and the threshold voltage distribution of the nonvolatile memory cell in the written state.

  The drain of the nonvolatile memory cell 13 is connected to the bit line BL for each column, and the control gate is connected to the word line WL in units of rows. The source of the nonvolatile memory cell is connected to a common source line SL for each erase block which is a batch erase unit. In FIG. 3, one word line WL, one bit line BL, and one source line SL are shown, but in actuality, a large number are arranged as desired in the memory array 12.

  The driver circuit (DRV) 14 performs voltage driving for the source line SL and the word line WL. The address decoder 15 receives a row address signal from the address bus ABUS included in the internal bus 10, decodes the row address signal, and selects a word line WL to be driven by the driver circuit 14 and a source line SL.

  The bit line BL is connected to a sense amplifier array (SAA) 17 via a column switch array (CSWA) 16 on one side and to a write latch circuit (PLAT) 18 on the other side. The sense amplifier array 17 is connected to a data input / output circuit (DIO) 19. The address decoder 15 receives a column address signal from the address bus ABUS included in the internal bus 10 and decodes the column address signal to form a selection signal for the column switch array 16. The column switch array 16 conducts the bit line BL selected by the column selection signal to the sense amplifier array 17. The sense amplifier array 17 senses and amplifies the information selected by the column switch array 16 among the storage information read from the nonvolatile memory cells to the bit lines in the read operation. The storage information sensed and amplified by the sense amplifier array 17 is output from the data input / output circuit 19 to the data bus DBUS of the internal bus 10. Write data input from the data bus DBUS to the data input / output circuit 19 is latched by the write latch circuit 18 via the bit line selected by the column switch array 16. The write operation is performed in units of word lines based on the data latched by the write latch circuit 18.

  A voltage generation circuit (VPPG) 21 boosts the power supply voltage Vcc to generate a high voltage necessary for erasing and writing. A memory control circuit (MCNT) 22 receives an access command from the data bus DBUS, and supplies power, address decoding, data input / output, and data latch necessary for each of erase, write, and read operations according to an instruction by the command. The operation procedure is controlled. 23 is a generic name for control signals for that purpose.

  Here, endian will be described. For example, little endian is to assign a small address to the lower side of the physical area of the data area. Big endian is to assign a large address to the lower side of the physical area of the data area. For example, assume the data area of FIG. The data area may be either a storage such as a memory area or a bus signal line. For example, a case where data H′01234567 is stored in an area starting from the address H′0000 is taken as an example. In the big endian, a large address H′0003 is assigned to the lower area (data H′67) LSB. In the little endian, a large address H'0003 is assigned to the upper area (data H'01) MSB.

  When the address assignment for the data area is big endian, as shown in FIG. 5, if the logical value of the access address for the data area is inverted for all bits, the address assignment for the data area is apparently the same as little endian. .

  The endian for the storage area of the memory array of the flash memory 4 will be described. For example, as shown in FIG. 6, the erase blocks of the flash memory 4 are designated as EB0 to EB4. Let EB0 be the lower area. The logical address map of the flash memory 4 as viewed from the CPU 2 is, for example, little endian. In short, the CPU 2 recognizes address assignment for the data area as little endian. Although not specifically illustrated, there is naturally a big endian CPU that recognizes address assignment to a data area. At this time, the physical address map of the flash memory 4 may be little endian and may be big endian.

In particular, it should be noted that the size of the erase block differs between the CPU 2 as the bus master and the flash memory 4 as the bus slave in addition to the arrangement of data on the data bus DBUS. For example, when the data bus DBUS is 32 bits, the data arrangement with respect to the byte address is reversed between big endian and little endian. Therefore, in order for the order of data accompanying data transfer to coincide between the transfer source and the transfer destination, the endian needs to be unified on both sides. There is no problem with writing to and reading from the flash memory 4 as long as the endian recognition regarding the arrangement of data on the data bus matches between the bus master and the bus slave. When an erase block is designated by an address, an erase block including an address accompanying an erase command or a rewrite command is set as a batch erase target. At this time, if the endian of the CPU 2 and the endian of the flash memory 4 do not match, there is a possibility that the erasure is performed in a wider range than the erasure range assumed by the CPU 2. For example, in the example of FIG. 6, when the endian of the CPU 2 and the endian of the flash memory 4 do not match, even if the CPU 2 designates the erase address of the erase block EB0, the erase address corresponds to the erase block EB4 on the flash memory 4. Thus, erasure is undesirably performed in the range of addresses H′2000 to H′8000.
In the opposite case, even if the CPU 2 designates the erase address of the erase block EB4, the erase address corresponds to the erase block EB0 on the flash memory 4, and the CPU 2 intends to erase the addresses H'0000 to H'8000. Only the addresses H'0000 to H'2000 on the flash memory 4 are erased, and H'2000 to H'8000 remain unerased. Even if the CPU 2 recognizes that the address H'3000 has been erased and tries to write data, the address H'3000 of the flash memory 4 has not been erased, so even if data was written there, it was written. Data will not be guaranteed. Therefore, the CPU 2 needs to erase each of the remaining erase blocks EB1 to EB3.
Further, not only when the reason why the logical address map of the CPU 2 and the physical address map of the flash memory 4 do not match is the endian mismatch, the logical erase block allocation in the program executed by the CPU 2 is the physical address of the flash memory 4. It is also possible that it does not match the map. Even if the endian of the entire logical address of the CPU 4 and the endian of the physical address of the flash memory 4 match, the endian does not match as long as it is limited to the local logical address assigned to the flash memory 4 by the CPU 4. It can be considered that there is an inconvenience in allocation of erase blocks.

  In order to eliminate the inconvenience when the sizes of the batch erase blocks are different, for example, the flash memory 4 includes an endian conversion circuit (EDCVT) 25 as illustrated in FIG. The endian conversion circuit 25 enables selection between high-order and low-order replacement for all bits of the address signal input from the address bus to the address input terminal.

  FIG. 1 shows an example of the endian conversion circuit 25. The endian conversion circuit 25 has a two-input exclusive OR gate (EXOR) 26 provided corresponding to all the address bits a0 to ai. In the figure, a configuration of three bits a0 to a2 is typically illustrated. A corresponding address bit is input to one input of the exclusive OR gate (EXOR) 26, and an endian control signal φES is input to the other input in common. When the endian control signal φES is a logical value 0, the outputs b0 to bi are made equal to a0 to ai. When the endian control signal φES is a logical value 1, each bit of the outputs b0 to bi is an inverted signal of each bit of a0 to ai. The address decoding logic of the address decoder 15 shown in FIG. 1 is, for example, big endian. X0 to X7 are word lines WL, and X0 is assigned from the lower side of the data area. Accordingly, the flash memory 4 is set to big endian when the endian control signal φES is a logical value 0 and is set to little endian when the logical value 1 is 1. FIG. 7 illustrates an operation mode of the endian conversion circuit 25 in accordance with FIG.

  By adopting the endian conversion circuit 25, when the endian of the flash memory 4 is different from the endian of the CPU 2 which is the main subject of access, the endian conversion circuit 25 replaces the upper and lower bits for all bits of the input address signal. Just do it. Thereby, both the flash memory 4 and the CPU 2 have the same address allocation direction for the data area. Therefore, even if the size of the erase block as a batch erase unit in the flash memory 4 is different depending on the address area, the address map for the erase block having a different size does not differ between the flash memory 4 and the CPU 2. Therefore, it is possible to prevent batch erasure from being performed on the flash memory 4 in an undesirably wide address range or from being performed in an undesirably narrow address range.

  Further, when the data processor 1 is designed by on-chip a plurality of circuit modules, even if the flash memory 4 is a minority circuit module that is different from the endian of another circuit module, the flash memory 4 is an endian conversion circuit. Therefore, it is not necessary to modify the address wiring pattern in the flash memory 4 and replace the address bits. It is only necessary to select the logical value inversion of the address bits for the endian conversion circuit 25 held in the flash memory 4. It is not necessary to increase the types of flash memory as design parts for endian matching. When the endian conversion circuit 25 is not employed, it is necessary to separately prepare a flash memory having the address decoder of FIG. 8 for the big endian and a flash memory having the address decoder of FIG. 9 for the little endian.

  In the example of the endian conversion circuit 25, the logical value can be inverted for all the bits of the input addresses a0 to ai. Can do. The upper and lower arrangement orders of the byte data on the 32-bit data bus DBUS can be aligned regardless of the number of bits of the data bus DBUS.

  FIG. 10 shows an example in which only the minimum necessary address bits are selectively inverted. The example of FIG. 10 is an example in which the minimum size of the erase block is 2 kilobytes (KB) and the data bus width is 64 bits. The address is a 32-bit byte address a0 to a31. Address bits necessary to represent 2 kilobytes (KB), which is the minimum size of the erase block, are 11 bits a0 to a10 of the address. Addresses required to represent byte data on a 64-bit (8-byte) data bus DBUS are 3-bit addresses a0 to a2. In this case, the address bits to be inverted in accordance with the endian conversion may be the address bits a11 to a31 higher than the addresses a0 to a10 and all the address bits a0 to a2. As a result, in a flash memory having a minimum erase block size of 2 kilobytes (KB) and a data bus width of 64 bits or less, the data transfer order on the data bus DBUS is not changed between big endian and little endian. It is possible to suppress erroneous erasure that exceeds the minimum erase block size of 2 KB. This can be realized by address inversion with the minimum number of bits. In FIG. 10, the symbol “˜” means inversion of each address bit in the address range to which it is attached.

  The endian control signal φES described with reference to FIG. 1 is output by a control latch (LAT) 30 of the memory controller 22 as shown in FIG. The control latch 30 latches endian control data held in a predetermined nonvolatile memory cell 13. When the reset operation is instructed by the reset signal RES, the memory controller 22 starts the operation of reading the predetermined nonvolatile memory cell 13 in response to this, and the endian held by the predetermined nonvolatile memory cell 13 Control data is internally transferred to the control latch 30. The internally transferred endian control data is supplied to the endian conversion circuit 25 as an endian control signal φES.

  FIG. 11 illustrates a flowchart for writing endian control data. This writing operation is performed by connecting an external writing device such as an EPROM writer to the port circuit 8 and directly accessing the flash memory 4. At this time, the writing device transfers commands and data in accordance with the endian of the flash memory 4. First, when a write command accompanied by endian control data and its write address is issued, the flash memory 4 latches the write address of the endian control data in the address decoder 15 (S1), and the endian control data is written to the write data latch 18. (S2). Thereafter, the memory control circuit 22 applies a write high voltage according to the write data (S3). Next, verify data is read (S4), rewrite data is calculated based on the verify data (S5), and write completion is determined depending on whether the rewrite data is different from the write data (S6). If there is, return to step S3 again and repeat the high voltage application. If the rewrite data does not match the write data, the process is terminated as writing completion. Endian control data has an initial value in the manufacturing stage. When the initial value specifies big endian, writing according to the flowchart of FIG. 11 is performed when selecting little endian.

  FIG. 12 illustrates a flowchart for reading endian control data. When the reset signal RES is set to the logical value 1 (RES = 1) and the reset operation is instructed (T1), the flash memory 4 selects the predetermined nonvolatile memory cell 13 and stores the stored information in the control latch 30. Transfer internally (T2). Thereafter, the reset signal RES is set to a logical value 0 (RES = 0), thereby terminating the process (T3).

  FIG. 13 shows an example in which the CPU 2 has an endian conversion circuit 25A. The endian conversion circuit 25A of the CPU 2 receives the address signals a0 to an output from the execution unit (EXEC) 31, selectively inverts the signals by the endian control signal φESA, and outputs the address signals b0 to bn to the address bus ABUS. .

  In the data processor 1 shown in FIG. 2, it is assumed that none of the on-chip circuit modules includes an endian conversion circuit, and a circuit module in which big endian and little endian are mixed is on-chip. At this time, a minority module having a different endian among the on-chip circuit modules may have the endian conversion circuit. When the endian of the flash memory is minor endian, the data processor 1 may be configured using the flash memory 4 provided with the endian conversion circuit 25. When the endian of the CPU is minor endian, the data processor 1 may be configured by adopting the CPU 2 provided with the endian conversion circuit 25A.

  Consider a case where both the CPU 2 and the DMAC 3 are provided with the endian conversion circuit 25A of FIG. At this time, if the endian of the CPU 2 is a minor endian and the endian of the DMAC 3 is a major endian, the endian conversion circuit 25A of the DMAC 3 may not perform the conversion operation. Therefore, the control signal φESA of the CPU 2 may be set to the conversion enable level, and the control signal φESA of the DMAC 3 may be set to the conversion disable level.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

  For example, the nonvolatile memory cell is not limited to a floating gate structure having a two-layer gate structure. A structure including a charge trapping film such as silicon nitride in a charge storage region, a split gate structure including an assist gate together with a memory transistor, or the like may be used. Further, writing and erasing are not limited to avalanche injection and FN tunneling to the source. Writing may be performed by hot electron injection and erasure may be performed by hot hole injection. Alternatively, writing may be performed by hot electron injection, and erasing may be performed by emitting electrons to the substrate through an FN tunnel.

  The circuit module including the endian conversion circuit may be a bus slave module other than the flash memory, for example, a peripheral circuit such as a RAM or a timer. The bus master module including the endian conversion circuit may be a DMAC other than the CPU.

  The endian conversion circuit is not limited to a configuration using an exclusive logic gate, and other configurations such as an exclusive negative OR gate can naturally be adopted. The number of parallel bits and the erase block size of the data bus can be changed as appropriate.

  The present invention is not limited to data processors. The present invention can be widely applied to various semiconductor integrated circuits such as a semiconductor integrated circuit having a single flash memory and a semiconductor integrated circuit having a single CPU.

It is a logic circuit diagram showing an example of an endian conversion circuit. 1 is a block diagram of a data processor that is an example of a semiconductor integrated circuit. FIG. It is a block diagram which shows an example of flash memory. It is a conceptual explanatory view of big endian and little endian. It is explanatory drawing which shows the significance of all bit inversion of an address signal. It is explanatory drawing which shows the relationship between the block erase block from which size differs in flash memory, and endian. It is explanatory drawing which shows the operation | movement form of the endian conversion circuit based on FIG. It is a logic circuit diagram of an address decoder dedicated to big endian when no endian conversion circuit is employed. FIG. 5 is a logic circuit diagram of a little endian dedicated address decoder when an endian conversion circuit is not employed. It is explanatory drawing which shows the relationship between a target address bit and an endian in the case of selectively inverting only a minimum necessary address bit in an endian conversion circuit. It is a write-in flowchart of endian control data. It is a read flowchart of endian control data. It is a logic circuit diagram which illustrates the composition of the endian conversion circuit with which CPU is provided.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Data processor 2 Central processing unit 3 Direct memory access controller 4 Flash memory 8, 9 Port circuit 10 Internal bus RES Reset signal 12 Memory array 13 Non-volatile memory cell SL Source line WL Word line BL Bit line 14 Driver circuit 15 Address decoder 25 , 25A Endian conversion circuit φES, φESA Endian control signal 30 Control latch 31 Execution unit

Claims (19)

A non-volatile memory having a plurality of non-volatile memory cells that can electrically rewrite stored information;
The nonvolatile memory erases stored information in the nonvolatile memory cells in units of erase blocks having different sizes,
The nonvolatile memory is a semiconductor integrated circuit having an endian conversion circuit capable of selecting logical value inversion for all bits of an address signal input from an address input terminal. A non-volatile memory having a plurality of non-volatile memory cells that can electrically rewrite stored information;
The nonvolatile memory erases stored information in the nonvolatile memory cells in units of erase blocks having different sizes,
All address bits higher than lower addresses corresponding to the number of address bits necessary to represent the minimum number of data words of an erase block among address signals input from the address input terminal of the nonvolatile memory, and the nonvolatile memory Logic for all address bits of the lower address for the number of address bits required to represent the number of parallel data words input / output at the data input / output terminal of the non-volatile memory among the address signals input from the address input terminal A semiconductor integrated circuit having an endian conversion circuit capable of selecting value inversion.   3. The semiconductor integrated circuit according to claim 1, wherein a predetermined nonvolatile memory cell in the nonvolatile memory serves as a storage area for control data for selecting logical value inversion of an address bit in the endian conversion circuit.   4. The semiconductor integrated circuit according to claim 3, wherein the non-volatile memory reads the control data from a predetermined non-volatile memory cell in response to a reset instruction and sets the control data in the endian conversion circuit. A semiconductor integrated circuit comprising: a nonvolatile memory having a plurality of nonvolatile memory cells that can electrically rewrite stored information; and a data processing unit capable of accessing the nonvolatile memory,
The nonvolatile memory erases stored information in the nonvolatile memory cells in units of erase blocks having different sizes,
A semiconductor integrated circuit having the endian conversion circuit capable of selecting logical inversion for all bits of an address signal transmitted from the data processing unit to the nonvolatile memory via an internal address bus. A semiconductor integrated circuit comprising: a nonvolatile memory having a plurality of nonvolatile memory cells that can electrically rewrite stored information; and a data processing unit capable of accessing the nonvolatile memory,
The nonvolatile memory erases stored information in the nonvolatile memory cells in units of erase blocks having different sizes,
All address bits higher than the lower address corresponding to the number of bits necessary to represent the minimum number of data words of the erase block among the address signals transmitted from the data processing unit to the nonvolatile memory via the internal address bus; Of the address signals transmitted on the internal address bus, lower-order addresses corresponding to the number of bits necessary to represent the number of parallel data words transmitted on the internal data bus to connect the data processing unit and the nonvolatile memory. A semiconductor integrated circuit having an endian conversion circuit capable of selecting logical inversion with respect to all address bits.   7. The semiconductor integrated circuit according to claim 5, wherein a predetermined nonvolatile memory cell in the nonvolatile memory serves as a storage area for control data for selecting a logical value inversion of an address bit in the endian conversion circuit.   8. The semiconductor integrated circuit according to claim 7, wherein the non-volatile memory reads the control data from a predetermined non-volatile memory cell in response to a reset instruction and sets the control data in the endian conversion circuit.   The semiconductor device according to claim 8, wherein the nonvolatile memory or the data processing unit includes the endian conversion circuit. A semiconductor integrated circuit having an internal bus and a bus master module and a bus slave module coupled to the internal bus on a semiconductor substrate,
The bus master module or the bus slave module has an endian conversion circuit,
The endian conversion circuit can selectively switch between a little endian that assigns a small address to the lower side of the data area and a big endian that assigns a large address to the lower side of the data area, with respect to address assignment to the data area of the bus slave module. A semiconductor integrated circuit.   11. The semiconductor integrated circuit according to claim 10, wherein the endian conversion circuit can select logic value inversion for all bits of an address signal transmitted through an internal bus.   The endian conversion circuit selects logical value inversion of all the address bits of the lower address for the number of address bits necessary to represent the number of parallel data words transmitted on the internal bus from among the address signals transmitted on the internal bus. The semiconductor integrated circuit according to claim 10, which is possible. The bus slave module is a non-volatile memory including a plurality of non-volatile memory cells that can rewrite stored information electrically.
The bus master module is a data processing unit capable of accessing the nonvolatile memory;
The nonvolatile memory erases stored information in the nonvolatile memory cells in units of erase blocks having different sizes,
The endian conversion circuit transmits all the address bits higher than the lower address corresponding to the number of bits required to represent the minimum number of data words of the erase block among the address signals transmitted on the internal bus, and is transmitted on the internal bus. 11. The semiconductor integrated circuit according to claim 10, wherein logical value inversion with all address bits of the lower address corresponding to the number of bits necessary to represent the number of parallel data words transmitted through the internal bus can be selected.   14. The semiconductor integrated circuit according to claim 13, wherein a predetermined nonvolatile memory cell in the nonvolatile memory serves as a storage area for control data for selecting logical value inversion of an address bit in the endian conversion circuit.   15. The semiconductor integrated circuit according to claim 14, wherein the nonvolatile memory reads the control data from a predetermined nonvolatile memory cell in response to a reset instruction and sets the control data in the endian conversion circuit.   The semiconductor integrated circuit according to claim 10, wherein a minority module having a different endian among the bus slave module and the bus master module in which big endian and little endian are mixed has the endian conversion circuit. A non-volatile memory including a plurality of non-volatile memory cells, and a plurality of circuit modules accessible to the non-volatile memory via an address bus and a data bus,
The first circuit module outputs first address information to the address bus for accessing the first nonvolatile memory cell via the data bus;
A second circuit module for outputting second address information to the address bus to access the first nonvolatile memory cell via the data bus;
A semiconductor integrated circuit comprising: a converter that converts the second address information into the first address information in response to a first state signal and performs control not to perform conversion in response to a second state signal. The first circuit module outputs the second state signal;
The semiconductor integrated circuit according to claim 17, wherein the second circuit module outputs the first state signal.   The non-volatile memory selects the first non-volatile memory cell from first row address information and first column address information included in the first address information in response to an input of the first address information. Item 18. The semiconductor integrated circuit according to Item 17.

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