JP2007006563A - Single-phase motor driving circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a single-phase motor driving circuit for achieving a low noise, a low vibration and a low power consumption. <P>SOLUTION: The motor driving circuit supplies a first driving voltage from one end to the other end of a motor coil for a first period, and supplies a second driving voltage from the other end to one end of the motor coil for a second period. A voltage comparing circuit compares a voltage corresponding to a current flowing in the motor coil with a reference voltage for setting a target of the current flowing in the motor coil. A rotation controlling circuit generates a PWM signal having a pulse width controlled based on a comparison output from the voltage comparing circuit, and outputs it to the motor driving circuit. The reference voltage is decreased so as to make the current be zero at a cross point of tails of the first and second periods in which the first and second driving voltages are supplied. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a single-phase motor drive circuit, for example, a technique effective when applied to a single-phase motor drive circuit that requires low noise and low vibration.

Japanese Patent Application Laid-Open No. 2004-153921 has been proposed as a single-phase motor driving device in which vibration, noise, and power consumption are reduced. In this single-phase motor drive device, when the drive current flowing through the motor coil is switched, only the lower bipolar transistor is turned on to form a regeneration path to reduce the motor coil current over time to zero. A period for turning off the lower bipolar transistor is provided so that the direction of the driving current of the single-phase motor is switched by soft switching.
JP 2004-153921 A

  In Patent Document 1, the driving current of the motor coil is decreased with time to zero for a certain period before and after the zero cross point. As is clear from the waveform diagram of the drive current in FIG. 4 of the document 1, the current direction is not switched at the zero cross point. As a result, the torque becomes zero before and after the zero cross point, and smooth rotation cannot be performed at a constant speed. For this reason, even lower noise and vibration, such as cooling fan motors mounted on electronic devices, are required. It is unsuitable for what is done.

  An object of the present invention is to provide a single-phase motor drive circuit that realizes low noise, low vibration, and low power consumption. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The outline of a typical invention among the inventions disclosed in the present application will be briefly described as follows. That is, the motor drive circuit supplies the first drive voltage from one end of the motor coil to the other end in the first period, and supplies the second drive voltage from the other end of the motor coil to the one end in the second period. The voltage comparison circuit compares a voltage corresponding to the current flowing through the motor coil with a reference voltage for setting a target value of the current flowing through the motor coil. The rotation control circuit generates a PWM signal whose pulse width is controlled by the comparison output of the voltage comparison circuit and inputs the PWM signal to the motor drive circuit. The reference voltage is decreased so that the rear portions of the first and second periods for supplying the first and second driving voltages become zero at the cross point.

  Further low noise and low vibration can be realized by soft switching of the drive current at the cross point.

  FIG. 1 shows a circuit diagram of an embodiment of a single-phase motor driving circuit according to the present invention. The motor coil drive circuit includes N-channel MOSFETs M1 and M3 as lower power switch elements and P-channel MOSFETs M2 and M4 as upper power switch elements. The MOSFETs M1 and M2 operate as CMOS output circuits when the input signal outpb is supplied to their gates. The MOSFETs M2 and M4 operate as a CMOS output circuit when an input signal outnb is supplied to their gates. The output terminals of these two CMOS output circuits are connected to one end P and the other end N of the motor coil to form a so-called bridge circuit. In the figure, the motor coil is represented by an equivalent circuit such as a reverse voltage B-emf, an inductance, and a resistance as indicated by a dotted line portion in the figure.

  A power supply voltage VCC is supplied to the sources of the P-channel MOSFETs M2 and M4. The sources of the N-channel MOSFETs M1 and M3 are connected in common, and a resistor RNF is provided between the circuit ground potential GND. The resistor RNF converts the current flowing through the motor coil into a voltage signal Vrnf. The voltage signal Vrnf and the reference voltage Vref for setting the motor driving current are supplied to the voltage comparison circuit VC1. The output signal of the voltage comparison circuit VC1 is input to the following rotation control circuit, and input signals outpb and outnb to be input to the motor coil drive circuit are generated by the rotation control circuit.

  The Hall element H forms a sine wave signal corresponding to the rotational position of the single phase motor and inputs it to the control circuit CONT. In the control circuit CONT, the sine wave signal from the Hall element H is wave-shaped to form the polarity instruction signal DIR. Further, the control circuit CONT uses the polarity instruction signal DIR and the like so that the voltage becomes zero corresponding to the zero cross point at the rear of the half rotation period as shown as the internal reference waveform in FIG. A reference voltage Vref is formed. In the rotation control circuit, the voltage comparison circuit VC1 compares the voltage signal Vrnf with the reference voltage Vref to form a PWM signal such that the voltage signal Vrnf is the same as the reference voltage Vref. This PWM signal is input to the motor coil drive circuit as input signals outpb and outnb.

  The clock CLK1 is not particularly limited, but is an oscillator included in the control circuit CONT or a reference clock supplied from the outside, and has a relatively high frequency. The clock CLK2 is formed by dividing the clock CLK1 by 1 / N in a frequency dividing circuit provided in the control circuit CONT, and is a signal corresponding to the PWM frequency. The clock CLK2 is supplied to the clock input CK of the flip-flop circuit FF1. A high level (logic 1) signal is constantly supplied to the data input D of the flip-flop circuit FF1. The output signal of the OR gate circuit G1 is supplied to the reset input R of the flip-flop circuit FF1.

  The output signal Q of the flip-flop circuit FF1 is converted into a PWM signal and supplied to one input of the OR gate circuits G2, G4 and NAND gate circuits G3, G5. The inverted output signal QB of the flip-flop circuit FF1 is supplied to the reset input R of the flip-flop circuit FF2 through the inverter circuit N1. The clock CLK1 is supplied to the clock input CK of the flip-flop circuit FF2. The data input of the flip-flop circuit FF2 is constantly supplied with a high level (logic 1) signal. The output signal of the voltage comparison circuit VC1 is supplied to one input of the OR gate circuit G1. An inverted signal QB of the flip-flop circuit FF2 is supplied to the other input of the OR gate circuit G1. The flip-flop circuit FF2 is provided to form a noise mask signal to be described later.

  The polarity instruction signal DIR is supplied to the data input of the flip-flop circuit FF4. The clock CLK2 is inverted and supplied to the clock input CK of the flip-flop circuit FF4 through the inverter circuit N3. The output Q and the inverted output QB of the flip-flop circuit FF4 are used as selection signals for the input signals outpb and outnb supplied to the motor coil driving circuit in response to the polarity instruction signal DIR. That is, the output Q of the flip-flop circuit FF4 is used as a gate control signal for the OR gate circuit G2 and the NAND gate circuit G3. The inverted output QB of the flip-flop circuit FF4 is used as a gate control signal for the OR gate circuit G4 and the NAND gate circuit G5. Output signals of the OR gate circuit G2 and the NAND gate circuit G3 are input to the NAND gate circuit G8. The gate circuit G8 forms an input signal outpb at the gates of the MOSFETs M1 and M2. Output signals of the OR gate circuit G4 and the NAND gate circuit G5 are input to the NAND gate circuit G11. The gate circuit G11 forms an input signal outnb at the gates of the MOSFETs M3 and M4.

  FIG. 2 is a waveform diagram for explaining the PWM control operation in the rotation control circuit of FIG. A clock CLK2 is formed by dividing the reference clock CLK1. The clock CLK2 is divided by 1 / N from the clock CLK. As shown in the figure, among N clocks CLK1, N-1 CLK1 is set to a high level during one CLK1, and one CLK1 is set to a low level. In FIG. 1, the output Q of the flip-flop circuit FF1 is set to the high level by the high level of the clock CLK2.

  For example, when the polarity instruction signal DIR is at a low level, the output Q of the flip-flop circuit FF4 is set to a low level (logic 0), and the inverted output QB is set to a high level (logic 1). When the output Q of the flip-flop circuit FF1 is set to a high level due to the high level of the inverted output QB, the NAND gate circuit G5 outputs a low level (logic 0), and the output signal outnb of the NAND gate circuit G11 becomes a high level. Then, the other end N of the motor coil is fixed to the low level. Since the NAND gate G3 outputs a high level by the low level (logic 0) of the output Q of the flip-flop circuit FF4, it is synchronized with the high level corresponding to the output Q of the flip-flop circuit FF1 of the OR gate circuit G2. As a result, the output signal outpb of the NAND gate circuit G8 becomes a low level, the output signal OUTP is formed, and the one end P of the motor coil is set to the high level. As a result, a current flows from one end P to the other end N of the motor coil, which is detected by the resistor RNF.

  The flip-flop circuit FF2 is supplied with the reset input R after the inverted output QB of the flip-flop circuit FF1 is delayed through the inverter circuit N1. Therefore, at the rising timing of the first clock CLK1, it is forcibly reset by the low level of the inverted output QB of the flip-flop circuit FF1, and the inverted output signal QB of the flip-flop circuit FF1 is maintained at the high level. Then, at the next rise of the clock CLK1, the high level of the data input D is taken into the flip-flop circuit FF2, and the inverted output QB becomes the low level.

  Thus, the high level of the inverted output QB of the flip-flop circuit FF2 is input to the reset input R of the flip-flop circuit FF1 through the OR gate circuit G1 only for the first one clock period of the clock CLK. Is the mask period tksk of the output signal of the voltage comparison circuit VC1. That is, when the output OUTP rises to a high level corresponding to the low level of the output signal outpb, a noise (whisker) that temporarily exceeds a reference voltage Vref occurs when a large current flows, so that an incorrect voltage comparison is performed. The output of PWM signal is invalidated by the inverted output QB of the flip-flop circuit FF2.

  When the output signal OUTP is at a high level, the drive current increases corresponding to the time constant in the motor coil, and when the reference voltage Vref is reached, the voltage comparison circuit VC1 forms a low-level output signal, so that the OR gate circuit G1 The output signal becomes low level and the flip-flop circuit FF1 is reset. Thereby, in synchronization with the low level corresponding to the output Q of the flip-flop circuit FF1, the output signal outpb of the NAND gate circuit G8 becomes high level, and the output signal OUTP becomes low level.

  FIG. 3 shows a waveform diagram of a PWM control operation for a plurality of cycles. In the figure, when the polarity instruction signal DIR is at a low level, the output OUTN at the other end N of the motor coil is set at a low level (strictly, it is higher than the GND level by the voltage drop of the resistor RNF). The motor drive current in which OUTP is a pulse signal corresponding to the PWM is controlled so as to become a predetermined current. At this time, noise (whisker) generated in the monitor voltage Vrnf at the rise of the output signal OUTP at one end P is substantially removed by the mask period tmsk.

  FIG. 4 is a waveform diagram of each part for explaining the operation of the single-phase motor driving circuit according to the present invention. B-emf is a counter electromotive voltage generated in the motor coil, and the sine wave waveform formed by the Hall element H is also the same waveform. In this embodiment, the half cycle T is divided into a front portion T1 and a rear portion T2, and T2 is set to any one of, for example, about 50% to 25% of the half cycle T, and the reference voltage Vref is set to zero toward the zero cross point. Reduce to be. For this reason, in the period T2, the PWM pulse width is also sequentially reduced in response to the decrease in the reference voltage Vref. By the PWM control as described above, it is possible to perform soft switching of the current corresponding to the zero cross point like the drive current Io indicated by the thick dotted line L1 in FIG.

  The drive current Io is a positive current from the one end P to the other end N of the motor coil, and a negative current from the other end N to the one end P. In the figure, the negative current Io flows during a half cycle in which the polarity instruction signal DIR is at a high level. That is, in the rotation control circuit of FIG. 1, the output Q of the flip-flop circuit FF4 is set to high level (logic 1), and the inverted output QB is set to low level (logic 0). Due to the high level of the output Q of the flip-flop circuit FF4, the output signal of the OR gate circuit G2 is at a high level. When the output Q of the flip-flop circuit FF1 is set to high level, the NAND gate circuit G3 outputs low level (logic 0), the output signal outpb of the NAND gate circuit G8 becomes high level, and one end P of the motor coil is set to low level. Secure to. Since the NAND gate circuit G5 forms a high level output signal by the low level of the inverted output QB, the NAND gate circuit G11 is synchronized with the high level corresponding to the output Q of the flip-flop circuit FF1 of the OR gate circuit G4. Output signal outnb becomes low level, and the output signal OUTN is formed to bring the other end N of the motor coil to high level. Thus, a negative current Io flows from the other end N of the motor coil toward the one end N, and this is detected by the resistor RNF.

  The positive / negative switching of the drive current Io as described above can correspond to the zero cross point of the sine wave signal that is the position detection signal formed by the Hall element H. As a result, since the motor coil drive current Io is switched by soft switching at the zero cross point, rotation control at a smooth and constant speed is possible, and a low noise and low vibration motor drive circuit can be realized.

  The inventor of the present application has studied to increase the number of turns of the motor coil to reduce power consumption and to reduce the current accordingly. When the number of turns of the motor coil is increased in this way, the inductance component increases accordingly. As described above, in the rear period T2 of the half cycle T of the motor rotation, the reference voltage Vref is reduced to zero toward the zero cross point, and the PWM pulse width may be narrowed correspondingly. It has been found that the time constant L / R at 1 becomes larger, and the motor drive current Io cannot be lowered corresponding to the reference voltage Vref.

  Thus, if the motor drive current Io does not decrease, a current in the reverse direction flows through the motor coil even when the polarity is switched. In other words, an effect of suddenly braking the motor rotation is brought about. Then, the polarity of the drive current Io is switched after the zero cross point, and immediately after that, it must operate so as to rapidly recover the rotational speed dropped by braking with the reverse current as described above, which is necessary. As the drive current increases, rotation unevenness occurs. Therefore, in the motor drive circuit of FIG. 1, the time constant (L / R) of the motor coil is limited to a relatively small motor.

  FIG. 5 shows a circuit diagram of another embodiment of the single-phase motor driving circuit according to the present invention. This embodiment is directed to improving the embodiment circuit of FIG. In other words, the circuit of this embodiment is devised to enable low vibration with low noise even if the number of turns of the motor coil is increased to reduce power consumption and the current is reduced accordingly.

  In this embodiment, a flip-flop circuit FF3, gate circuits G6, G7 and G9, G10 whose output signal Q is controlled, and inverter circuits N2, N4, N5 are provided. That is, the output signal of the voltage comparison circuit VC1 is inverted and supplied to the data input D of the flip-flop circuit FF3 by the inverter circuit N2. The output signal Q of the flip-flop circuit FF2 is supplied to the clock input CK of the flip-flop circuit FF3. The clock CLK2 is supplied to the reset input R of the flip-flop circuit FF3. The output Q of the flip-flop circuit FF3 is used as the gate control signal for the NAND gate circuits G6 and G9, and the signal inverted by the inverter circuits N4 and N5 is used as the gate control signal for the NAND gate circuits G7 and G10.

  The NAND gate circuits G6 and G7 invert the output signals of the OR gate circuit G2 and the NAND gate circuit G3 in response to the gate control signal, and transmit the signal to the input of the NAND gate circuit G8 that outputs the input signal outpb of the motor drive circuit. Configure the route. The NAND gate circuits G9 and G10 invert the output signals of the OR gate circuit G4 and the NAND gate circuit G5 in response to the gate control signal and transmit the inverted signal to the input of the NAND gate circuit G11 that outputs the input signal outnb of the motor drive circuit. Configure the signal path.

  FIG. 6 is a waveform diagram for explaining an example of the operation of the embodiment circuit of FIG. This figure shows a state where the polarity instruction signal DIR is at a low level and the reference voltage Vref is decreasing toward the zero cross point. As described above, when the inductance component of the motor coil is large, the one cycle period of the clock CLK1 at the rising edge of the clock CLK2 is set to the mask time tmsk, and the PWM pulse width of the output signal OUTP is minimized during this period.

  When the inductance of the motor coil is small, Vrnf <Vref as shown in FIG. 3, and the output current can be attenuated by decreasing the PWM on-duty. However, in the case of a motor having a large inductance, the output current is not easily attenuated only by reducing the PWM pulse width duty, and the detected voltage Vrnf becomes the reference voltage after the mask time tmsk ends as shown in Vrnf> Vref shown in FIG. It is higher than Vref. Accordingly, the flip-flop circuit FF1 is reset by the output of the voltage comparison circuit VC1, the output OUTP is correspondingly set to the low level, the data input D of the flip-flop circuit FF3 is set to the high level, and the output Q of the flip-flop circuit FF2 is set. The output Q of the flip-flop circuit FF3 is set to the high level in synchronization with the rising to the high level, that is, the end timing of the mask time tmsk. As a result, the output OUTN becomes a high level, and a reverse voltage is applied to the motor coil to rapidly attenuate the current.

  FIG. 7 is a waveform diagram of each part for explaining an example of the operation of the embodiment circuit of FIG. The attenuation of the output current Io can be reduced toward the zero cross point by flowing the reverse current in addition to reducing the PWM pulse width duty by the reverse current as described above. In FIG. 7, during the period T2, the PWM pulse width is sequentially reduced in response to a decrease in the reference voltage Vref (Iref), and the PWM operation is alternately performed on the motor drive output signals OUTP and OUTN. Thus, even in a motor having a large inductance as described above, the positive / negative switching of the drive current Io as described above corresponds to the zero cross point of the sine wave signal that is a position detection signal formed by the Hall element H. Can do.

  In this embodiment, since the motor coil drive current Io is switched by the soft switching at the zero cross point as described above, rotation control at a smooth and constant speed is possible, and a low noise and low vibration motor drive circuit is provided. Can be realized. Since the inductance of the motor coil is large, the motor can be rotated with a small driving current, and the power consumption can be reduced.

  Thus, at the end of the mask time tmsk, the output Q of the flip-flop circuit FF2 is determined as the clock input CK of the flip-flop circuit FF3, and the output signal of the voltage comparison circuit VC1 is determined by the inverter circuit N2 as the data of the flip-flop circuit FF3. By inputting to the input D, the output of the voltage comparison circuit VC1 is latched by the flip-flop circuit FF3, and whether the current output current Io is Vrnf <Vref or Vrnf> Vref is determined to be low level or high level from the latched data. .

  When the output Q of the flip-flop circuit FF3 is at a high level, it is determined that Vrnf <Vref, that is, it is determined that the motor has a small inductance, and the PWM control as shown in FIG. Try to reduce the drive current. On the other hand, when the output Q of the flip-flop circuit FF3 is at a low level, it is determined that Vrnf> Vref, that is, it is determined that the motor has a large inductance, and the PWM control and motor coil as shown in FIG. By driving a reverse voltage with respect to B-emf, it is possible to promote rapid attenuation of the output current Io and to reduce the drive current corresponding to the zero cross point.

  FIG. 8 shows a circuit diagram of still another embodiment of the single-phase motor driving circuit according to the present invention. This embodiment is a modification of the embodiment circuit of FIG. In this embodiment, the resistor RNF that detects the drive current Io is omitted. Instead of the resistor RNF, the source-drain voltage Vron of the MOSFETs M1, M3 corresponding to the ON resistances of the N-channel MOSFETs M1, M3 is supplied to the voltage comparison circuit VC1 through the selector SEL controlled by the polarity instruction signal DIR. With this configuration, the resistor RNF can be omitted and wasteful power consumption that occurs here can be suppressed.

  Although the invention made by the inventor has been specifically described based on the above embodiment, the present invention is not limited to the above embodiment, and various modifications can be made without departing from the scope of the invention. For example, the specific configuration of the rotation control circuit of FIGS. 1, 5, and 8 may be anything as long as it performs the same operation as described above. In addition, the circuit for detecting the drive current is a circuit in which a gate and a source are shared with the MOSFETs M1 and M3, a dummy MOSFET having a size smaller than that of the MOSFETs M1 and M3 is formed, and a current flowing therethrough is used. May be. The power switch elements M1 to M4 can use bipolar transistors in addition to MOSFETs. The present invention can be widely used as a single-phase motor drive circuit.

1 is a circuit diagram showing an embodiment of a single-phase motor driving circuit according to the present invention. FIG. It is a wave form diagram for demonstrating the PWM control operation | movement in the rotation control circuit of FIG. FIG. 2 is a waveform diagram of a PWM control operation for a plurality of cycles in the rotation control circuit of FIG. 1. It is each part waveform diagram for demonstrating operation | movement of the single phase motor drive circuit based on this invention. It is a circuit diagram which shows another Example of the single phase motor drive circuit based on this invention. FIG. 6 is a waveform diagram for explaining an example of the operation of the single-phase motor drive circuit of FIG. 5. FIG. 6 is a waveform diagram of each part for explaining the operation of the single-phase motor drive circuit of FIG. 5. It is a circuit diagram which shows another one Example of the single phase motor drive circuit based on this invention.

Explanation of symbols

FF1 to FF4: flip-flop circuit, G1 to G11: gate circuit, VC1: voltage comparison circuit, CONT ... control circuit, RNF ... resistor, H ... Hall element.

Claims (5)

In the first period, the first upper power switch element is turned on, the second lower power switch element is turned on, and the first drive voltage is supplied from one end of the motor coil to the other end. In the second period, the first drive voltage is supplied. A motor coil drive circuit that turns on a lower power switch element and turns on a second upper power switch element to supply a second drive voltage from the other end of the motor coil to one end;
A voltage comparison circuit that compares a voltage corresponding to the current flowing through the motor coil with a reference voltage for setting a target value of the current flowing through the motor coil;
Rotation control for generating a PWM signal whose pulse width is controlled by a comparison output of the voltage comparison circuit and generating switch control signals for the first upper and lower power switch elements and the second upper and lower power switch elements With circuit,
The single-phase motor driving circuit according to claim 1, wherein the reference voltage is decreased so that a rear portion of the first and second periods becomes a zero potential at a cross point. In claim 1,
The rotation control circuit is
A circuit for supplying the second or first drive voltage when it is determined that an output signal of the voltage comparison circuit is larger than the reference voltage except for noise generated when the first or second drive voltage is applied; A single-phase motor drive circuit, further comprising: In claim 2,
Resistance means is provided between the first and second lower power switch elements and the ground potential of the circuit, and a voltage generated by the resistance means is applied to the voltage comparison circuit as a voltage corresponding to a current flowing through the motor coil. A single-phase motor drive circuit characterized by being supplied. In claim 3,
A first clock and a second clock obtained by dividing the first clock;
The rising timing of the first or second driving voltage is set by the second clock,
A single-phase motor characterized in that one period of the first clock at the rise of the first or second drive voltage is a mask signal for removing noise generated when the first or second drive voltage is applied. Driving circuit. In claim 4,
The first and second upper power switch elements are constituted by P-channel power MOSFETs,
The single-phase motor drive circuit according to claim 1, wherein the first and second lower power switch elements are constituted by N-channel power MOSFETs.

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