JP2007005627A - Manufacturing method of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To manufacture a semiconductor device for forming a stress control film for generating stress in a channel formation region of a field effect transistor formed on a substrate surface so that the intrinsic stress can be changed after the stress control film is formed. To do.
[Solution]
A stress control film is formed on the field effect transistor, and a heat treatment or plasma treatment with ammonia or hydrogen is performed to change the material of the entire stress control film or a part thereof, thereby changing the intrinsic stress of the stress control film. A method of manufacturing a semiconductor device having a process.
[Selection] Figure 4

Description

  The present invention relates to a method for manufacturing a semiconductor device having a field effect transistor having a MIS structure (Metal Insulator Semiconductor).

  A MOSFET (Metal Oxide Semiconductor Field Effect Transistor) using an oxide film as an insulating film among transistors having a MIS structure has been put into practical use. MOSFETs are widely used as LSI devices because they consume less power and can be miniaturized, highly integrated, and operated at high speed.

  In recent years, information communication means have been developed, and the performance required for this type of MOSFET has been increased. Therefore, an operation speed-up technique for intentionally applying stress to the channel formation region of the MOSFET and distorting the crystal of the semiconductor substrate to increase carrier mobility has been studied. Among them, Dual Stress Liner technology (hereinafter referred to as DSL technology) in which a film that generates tensile stress in the channel formation region of the nMOSFET and a film that generates compression stress in the channel formation region of the pMOSFET are formed on each MOSFET. A semiconductor device used is known (see, for example, Patent Document 1).

  FIG. 11 is a schematic cross-sectional view in the middle of a semiconductor device manufacturing process using a conventionally known DSL technique. A source region 103 and a drain region 104 are formed in the p-type semiconductor region 102 of the semiconductor substrate 101. There is a difference in which current flows between the source region and the drain region, and there is no difference in the basic structure. A channel formation region 105 is formed in the vicinity of the substrate surface of the p-type semiconductor region 102 between the source region 103 and the drain region 104. A gate insulating film 106 and a gate electrode 107 are formed on the channel formation region 105, and a sidewall 111 is formed on the side wall of the gate electrode 107. Silicides 108, 109, and 110 are formed on the source region 103, the drain region 104, and the gate electrode 107 to form an nMOSFET. A first stress control film 112 is formed on the nMOSFET to generate stress in the channel formation region 105. The carrier mobility in the channel formation region is affected by the magnitude of the generated stress. In general, the material, film thickness, and the like of the first stress control film 112 are selected so that tensile stress is generated in the nMOSFET.

  Isolated by the element isolation region 124, the n-type semiconductor region 113 of the semiconductor substrate 101 includes a source region 114, a drain region 115, a channel formation region 116, a gate insulating film 117, a gate electrode 118, a sidewall 119, a silicide 120, 121 and 122 are formed to constitute a pMOSFET. A second stress control film 123 is formed on the pMOSFET to generate stress in the channel formation region 116. In general, the material, film thickness, and the like of the second stress control film 123 are selected so that compressive stress is generated in the pMOSFET.

In the above known example, the stress generated by the first stress control film 112 or the second stress control film 123 in the channel formation region can be controlled by changing the thickness of the film, changing the film formation conditions, or the type of film. There are known methods such as changing. For example, when a silicon nitride film is used as the stress control film, the tensile stress increases as the film thickness increases (see, for example, FIG. 4 of Patent Document 1). Therefore, in order to generate a desired stress in the channel formation region, the film thickness is determined in advance, or the film formation conditions and film type are determined, and once formed, the stress applied to the channel formation region is not adjusted. A semiconductor device was manufactured.
JP 2003-86708 A

  However, in the conventional example, once the stress control film is formed, the stress of the film itself (hereinafter referred to as intrinsic stress) cannot be changed unless the film is replaced.

  In addition, the intrinsic stress of the stress control film is affected by the individual film forming conditions, processing conditions, and manufacturing process history, and there is a problem that it becomes difficult to adjust the film stress as the semiconductor device is manufactured.

  Further, the nMOSFET and the pMOSFET have different stresses so as to be generated in a channel formation region for improving the characteristics of the transistor. Therefore, it is difficult to apply the stress control film formed in the same process to both the nMOSFET and the pMOSFET at the same time. For this purpose, different stress control films must be individually formed under different film formation conditions. There was a problem that the manufacturing process increased.

  In order to solve the above problems, the present invention has taken the following measures.

  In the present invention according to claim 1, a step of forming a transistor on a substrate, a step of forming a stress control film for generating stress in the transistor, and a heat treatment on the stress control film after forming the stress control film Or a step of adjusting the stress of the stress control film by performing plasma treatment.

  According to a second aspect of the present invention, in the semiconductor device manufacturing method according to the first aspect, the heat treatment is a heat treatment at a temperature exceeding at least 500 ° C.

  In the present invention according to claim 3, the transistor is a field effect transistor, the stress control film is a stress control film for generating stress in a channel formation region of the field effect transistor, and the step of performing the heat treatment includes 3. The method of manufacturing a semiconductor device according to claim 1, wherein the stress control film is a step of adjusting a stress in a direction in which a tensile stress increases.

  In the present invention according to claim 4, forming a first conductivity type field effect transistor having a first channel formation region and a second conductivity type field effect transistor having a second channel formation region on a semiconductor substrate; Forming a stress control film for generating stress in the first channel formation region and the second channel formation region on the first conductivity type field effect transistor and the second conductivity type field effect transistor; and A step of forming a mask layer on the substrate, a step of removing the mask layer on the second conductivity type field effect transistor, and a step of performing a plasma treatment on the stress control film in a portion where the mask layer is removed. A method for manufacturing a semiconductor device having

  According to a fifth aspect of the present invention, in the semiconductor device manufacturing method according to the first or fourth aspect, the plasma treatment is a plasma treatment using a gas containing ammonia or hydrogen.

  In the present invention according to claim 6, the step of performing the plasma treatment is a step of adjusting the stress of the stress control film in a direction in which the tensile stress decreases. The manufacturing method of the semiconductor device described in the above.

  According to the present invention, after a stress control film for generating stress is formed on a transistor, heat treatment or plasma treatment is performed to increase or relieve stress (hereinafter referred to as intrinsic stress) of the stress control film itself. it can. Therefore, even if the intrinsic stress of the stress control film varies depending on the film formation conditions and other processing conditions during the manufacturing process, it is possible to change the stress without changing the formed film itself. Can be generated in the transistor.

  Further, according to the present invention, a stress control film is formed on the first conductivity type field effect transistor and the second conductivity type field effect transistor, and then plasma treatment is performed on the film on the second conductivity type field effect transistor. Thus, different stresses can be independently generated in different channel formation regions of different field effect transistors using the same stress control film. Therefore, the manufacturing process can be simplified, and the performance of each field effect transistor can be improved while mitigating fluctuations caused by the formation conditions of the stress control film and other processing conditions during the manufacturing process.

  In the method for manufacturing a semiconductor device according to an embodiment of the present invention, a transistor is first formed on a substrate. As the substrate, a semiconductor substrate made of single crystal silicon can be used. Alternatively, an SOI (Silicon On Insulator) substrate in which single crystal silicon is vapor-phase grown or bonded to an oxide can be used. A field effect transistor can be used as the transistor. The field effect transistor is formed as follows, for example. A gate electrode is selectively formed on the main surface of the semiconductor substrate through a gate insulating film, and impurities are ion-implanted using the gate electrode as a mask to form a source region and a drain region, and between the source region and the drain region. A channel formation region is formed immediately below the gate insulating film.

  Next, a stress control film is deposited on the gate electrode. As the stress control film, an insulating film such as a silicon nitride film or a silicon oxide film can be used. In addition to these films, other insulating films, composite films combining insulating films and conductive films, or films composed of a plurality of layers may be used as long as they generate necessary stress in the channel formation region. Can do. Next, heat treatment or plasma treatment with ammonia or hydrogen gas is performed. The heat treatment is desirably performed at a temperature of 500 ° C. or higher. By performing this heat treatment after depositing the stress control film and performing necessary processing, it is possible to change the stress generated in the channel formation region, for example, the tensile stress. Further, plasma treatment is performed by generating a plasma of a gas mixed with ammonia or hydrogen and exposing the stress control film to the plasma. By performing this plasma treatment, the intrinsic stress of the stress control film changes, and the stress generated in the channel formation region, for example, the tensile stress can be reduced.

  According to another embodiment of the present invention, there is provided a method of manufacturing a semiconductor device. First, a first conductivity type field effect transistor having a first channel formation region on a main surface of a semiconductor substrate and a second conductivity type having a second channel formation region. And a field effect transistor. An n-channel field effect transistor can be formed as the first conductivity type field effect transistor, and a p-channel field effect transistor can be formed as the second conductivity type field effect transistor. Further, the first conductivity type field effect transistor may be a p-channel type field effect transistor and the second conductivity type field effect transistor may be an n-channel type field effect transistor depending on the material and characteristics of the stress control film to be formed.

  Next, a stress control film is deposited on the first conductivity type field effect transistor and the second conductivity type field effect transistor. Next, a mask layer is formed on the first conductivity type field effect transistor, and then the mask layer on the second conductivity type field effect transistor is removed by photolithography and etching techniques. If a photoresist is used as the mask layer, the manufacturing process can be further simplified. Alternatively, a silicon oxide film, a silicon nitride film, or the like can be used.

  Next, plasma treatment using ammonia or hydrogen is performed on the semiconductor substrate, and the stress control film on the second conductivity type field effect transistor is exposed to the plasma. As a result, the stress control film on the first conductivity type field effect transistor and the stress control film on the second conductivity type field effect transistor have different intrinsic stresses, respectively. Different stresses can be generated in the second channel formation region.

  Hereinafter, the manufacturing method of the semiconductor device according to the present embodiment will be described in detail with reference to FIGS.

  FIG. 1 is a schematic cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor device in the present embodiment. A semiconductor substrate 1 is prepared. A silicon single crystal substrate is used as the semiconductor substrate.

  An element isolation region 2 is formed on the main surface of the semiconductor substrate 1. First, a silicon nitride film is deposited on the surface of the semiconductor substrate 1 by low pressure CVD (Low Pressure Chemical Vapor Deposition), and the silicon nitride film and the semiconductor substrate 1 in the region to be the element isolation region 2 are sequentially selected by photolithography and etching. Is removed to form a shallow trench. Next, a silicon oxide film is deposited in the trench by low pressure CVD to fill the trench. Thereafter, chemical mechanical polishing (CMP) is performed and planarized, and then thermal oxidation is performed in an oxygen atmosphere to densify the oxide film, thereby forming the element isolation region 2.

Next, the gate insulating film 3 and the gate electrode 4 are formed. The gate insulating film 3 is formed by thermally oxidizing the surface of the semiconductor substrate 1, and polysilicon is deposited thereon by low pressure CVD. Next, the polysilicon is selectively removed by photolithography and etching to form the gate electrode 4. Next, ion implantation is performed using the gate electrode 4 as a mask to perform LDD (Lightly).
A Doped Drain) region is formed. Arsenic (As) or phosphorus (P) is ion-implanted in the case of an n-channel field effect transistor, and boron (B) is ion-implanted in the case of a p-channel field effect transistor. Next, a silicon nitride film and a silicon oxide film are deposited by plasma CVD, and anisotropic etching is performed to form gate side walls 5 on the gate electrode 4. Next, ion implantation is performed using the gate electrode 4 and the gate sidewall 5 as a mask to form a source region 6 and a drain region 7. Arsenic is ion-implanted in the case of an n-channel field effect transistor, and boron is ion-implanted in the case of a p-channel field effect transistor. Next, cobalt is deposited on the entire surface of the semiconductor substrate 1 by sputtering, and then a rapid thermal annealing (RTA) is performed to silicide the cobalt on the source region 6, the drain region 7, and the gate electrode 4 ( A conductive layer 8 made of (CoSi) is formed.

  In this manner, a field effect transistor is formed on the main surface of the semiconductor substrate 1. A channel formation region 9 is formed in the vicinity of the surface of the semiconductor substrate 1 immediately below the gate electrode 4 and between the source region 6 and the drain region 7.

  FIG. 2 is a schematic cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor device in which the stress control film 10 is formed on a field effect transistor. A silicon nitride film was used as the stress control film 10. The silicon nitride film was formed by thermal decomposition using an organic source gas. More specifically, a film was formed by a low pressure thermal chemical vapor deposition (CVD) method using BTBAS (bis (tert-butylamino) silane) and ammonia as raw materials. In addition to BTBAS, a film such as silane (SiH 4) and ammonia (NH 3) may be used to form a film by a thermal CVD method, a low pressure CVD method, a PCVD (Plasma Chemical Vapor Deposition) method, or the like.

Next, the silicon nitride film that is the stress control film 10 is subjected to a heat treatment to change the intrinsic stress of the silicon nitride film. FIG. 3 shows a change in the intrinsic stress of the silicon nitride film due to the heat treatment. Graph 11 shows the tensile stress at each temperature when the temperature is raised, and graph 12 shows the tensile stress at each temperature when the temperature is lowered. As the temperature rises from room temperature to 600 ° C., the tensile stress of the film increases from around the temperature of 500 ° C., and the tensile stress of about 1750 MPa (megapascal: 10 ⁶ N / m ² ) at room temperature is a maximum of 2500 MPa. Has reached. Thereafter, when the temperature was lowered to room temperature, the tensile stress decreased, but stabilized at 2050 MPa which was 1.2 times larger than the initial tensile stress. Thus, the stress can be changed by heat-treating the stress control film 10. The heat treatment temperature is desirably a temperature exceeding 500 ° C. Further, the stress can be further increased by performing the heat treatment at 600 ° C.

  Next, an embodiment will be described in which the silicon nitride film which is the stress control film 10 is subjected to plasma treatment instead of the heat treatment to change the intrinsic stress of the silicon nitride film.

  FIG. 4 is a schematic cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor device in which the stress control film 10 is subjected to plasma treatment. The stress control film 10 is a silicon nitride film formed in the same manner as described above. Plasma treatment is performed by exposing the stress control film 10 to a plasma 13 of a gas into which ammonia or hydrogen is introduced. In the plasma treatment of ammonia, for example, 1600 sccm (standard cc / min, 1 atm) of ammonia gas and 1600 sccm of nitrogen as a carrier gas are introduced into the chamber, and RF (Radio Frequency) plasma power is supplied from 700 watts (W) to 1000 W. Create a plasma. The hydrogen plasma treatment is performed, for example, by introducing 1000 sccm of hydrogen gas into the chamber and supplying RF plasma power from 300 W to 700 W to generate plasma.

  FIG. 5 shows changes in tensile stress when the silicon nitride film is exposed to ammonia plasma. The horizontal axis represents plasma power and the vertical axis represents tensile stress. Graph 14 shows the tensile stress before treatment, and graph 15 shows the tensile stress after treatment. From this figure, it can be understood that the tensile stress can be reduced by performing the plasma treatment, and the tensile stress is greatly reduced as the plasma power is increased.

  FIG. 6 shows the change in tensile stress when hydrogen is exposed to plasma. The horizontal axis represents plasma power, and the vertical axis represents tensile stress. Graph 16 shows the tensile stress before treatment, and graph 17 shows the tensile stress after treatment. From FIG. 6, it can be understood that the tensile stress of the stress control film 10 decreases by performing the plasma treatment, and the decrease in the tensile stress increases as the plasma power increases.

  As described above, by performing heat treatment or plasma treatment on the stress control film, the intrinsic stress can be changed after the film formation. The stress control film generates a stress in a region located below the stress control film. That is, if the intrinsic stress of the stress control film changes, the stress generated in the channel formation region of the field effect transistor located thereunder also changes. Generally, when the intrinsic stress of the stress control film is a tensile stress, the tensile stress is also generated in the channel formation region of the field effect transistor. Thus, the stress in the channel formation region of the transistor can be changed after the stress control film is formed.

  FIG. 7 is a schematic cross-sectional view of a semiconductor substrate showing another method for manufacturing a semiconductor device in the present embodiment. In the present embodiment, an n-channel field effect transistor (hereinafter referred to as nFET) and a p-channel field effect transistor (hereinafter referred to as pFET) are formed on the main surface of a semiconductor substrate, and a stress control film is applied. is there.

  First, a silicon nitride film is deposited on the main surface of the semiconductor substrate 21 by low pressure CVD, and the silicon nitride film and the semiconductor substrate 21 in the region to be the element isolation region 22 are selectively removed sequentially by photolithography and etching to be shallow. A trench is formed. Next, a silicon oxide film is deposited in the trench by low pressure CVD to fill the trench. Thereafter, chemical mechanical polishing is performed to flatten the surface, followed by thermal oxidation in an oxygen atmosphere to densify the oxide film, thereby forming an element isolation region 22.

  Next, gate insulating films 23 and 24 and gate electrodes 25 and 26 are formed. The gate insulating films 23 and 24 are formed by thermally oxidizing the surface of the semiconductor substrate 21, polysilicon is deposited thereon by low-pressure CVD, and selectively removed by photolithography and etching to form a gate electrode 25 made of polysilicon. , 26 are formed. Next, phosphorus is ion-implanted into the nFET region on the left side of the surface of the semiconductor substrate 21 using the gate electrode 25 as a mask to form an LDD (Lightly Doped Drain) region. Similarly, the pFET region on the right side of the surface of the semiconductor substrate 21 Then, boron is ion-implanted using the gate electrode 26 as a mask to form an LDD region. Next, a silicon nitride film and a silicon oxide film are deposited by plasma CVD, and anisotropic etching is performed to form gate side walls 27 and 28 on the gate electrodes 25 and 26. Next, arsenic ions are implanted into the nFET region using the gate electrode 25 and its gate sidewall 27 as a mask to form a source region 29 and a drain region 30. Similarly, boron is ion-implanted into the pFET region using the gate electrode 26 and its gate sidewall 28 as a mask to form a source region 31 and a drain region 32.

  Next, cobalt is deposited on the entire surface of the semiconductor substrate 21 by sputtering, and then an instantaneous heat treatment (RTA: Rapid Thermal Anneal) is performed to form the source regions 29 and 31 and the drain regions 30 and 32, and from polysilicon. Conductive layers 33 and 34 in which cobalt is silicided (CoSi) on the gate electrodes 25 and 26 are formed. The cobalt on other regions, for example, the element isolation region 22 is removed.

  In this way, nFETs and pFETs are formed on the main surface of the semiconductor substrate 21. Note that an nFET n-channel formation region 40 is formed in the semiconductor substrate 21 between the source region 29 and the drain region 30 under the gate insulating film 23, and between the source region 31 and the drain region 32 under the gate insulating film 24. The pFET p-channel formation region 41 is formed on the semiconductor substrate 21.

  FIG. 8 is a schematic cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor device in which a stress control film 35 is deposited on the nFET and pFET. As the stress control film 35, a silicon nitride film is deposited by a thermal CVD method or a low pressure CVD method. More specifically, the silicon nitride film is formed by thermal decomposition using an organic source gas. A film can be formed by a low pressure thermal CVD method using BTBAS and ammonia as raw materials. In addition to BTBAS, a film such as silane and ammonia can be used to form a film by a thermal CVD method, a low pressure CVD method, a PCVD method, or the like. In addition to the silicon nitride film, a silicon oxide film and other materials can be used.

  FIG. 9 is a schematic cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor device in which a mask layer is selectively formed on the stress control film 35. A photoresist was used as the mask layer 36. A photoresist is applied and then dried, the photoresist on the pFET is removed by a photolithography technique, the surface of the stress control film 35 is exposed, and a mask layer 36 is formed. As the mask layer, a silicon oxide film, a silicon nitride film, or the like can be used instead of the photoresist. This is because it is only necessary to have a function of blocking the stress control film 35 on the nFET so as not to be exposed to plasma in the plasma processing performed later.

  FIG. 10 is a schematic cross-sectional view of a semiconductor substrate showing a method for manufacturing a semiconductor device in which the semiconductor substrate 21 on which the mask layer 36 is formed is subjected to plasma treatment. The plasma treatment is performed with an ammonia or hydrogen plasma 37. The plasma treatment of ammonia is performed, for example, by introducing 1600 sccm of ammonia gas and 1600 sccm of nitrogen as a carrier gas into the chamber and supplying RF (Radio Frequency) plasma power from 700 watts (W) to 1000 W to generate plasma. The hydrogen plasma treatment is performed, for example, by introducing 1000 sccm of hydrogen gas into the chamber and supplying RF plasma power from 300 W to 700 W to generate plasma.

  The mask layer 36 blocks the entry of particles generated by plasma to the stress control film 35 on the nFET, and the stress control film 35 on the pFET is subjected to plasma processing. The intrinsic stress of the stress control film 35 subjected to the plasma treatment is changed in the direction in which the tensile stress decreases.

  As a result, the tensile stress generated in the p channel formation region can be relaxed with respect to the tensile stress generated in the n channel formation region 40. In general, nFETs have higher carrier mobility and higher performance when the tensile stress generated in the n-channel formation region is larger. On the other hand, in the pFET, when the tensile stress generated in the p-channel formation region is relaxed, the carrier mobility is increased and the performance is improved.

  That is, according to the manufacturing method of the semiconductor device in the present embodiment, since the plasma treatment can be performed on the necessary portion of the stress control film, the characteristics of both the nFET and the pFET are improved by the single stress control film. be able to. Therefore, the manufacturing process can be simplified.

  Although the present embodiment has been described in detail above, the effects of the present invention can be obtained by performing heat treatment before plasma processing and then performing plasma processing in the above embodiment.

It is typical sectional drawing which shows the manufacturing process of the semiconductor device in this Embodiment. It is typical sectional drawing which shows the manufacturing process of the semiconductor device in this Embodiment. The graph which shows the relationship between heat processing temperature and tensile stress. It is typical sectional drawing which shows the manufacturing process of the semiconductor device in this Embodiment. The graph which shows the relationship between the plasma power and the tensile stress by the plasma processing containing ammonia. The graph which shows the relationship between the plasma power and the tensile stress by the plasma processing containing hydrogen. It is typical sectional drawing which shows the manufacturing process of the semiconductor device in this Embodiment. It is typical sectional drawing which shows the manufacturing process of the semiconductor device in this Embodiment. It is typical sectional drawing which shows the manufacturing process of the semiconductor device in this Embodiment. It is typical sectional drawing which shows the manufacturing process of the semiconductor device in this Embodiment. FIG. 10 is a schematic cross-sectional view showing the middle of a semiconductor device manufacturing process using a conventionally known DSL technique.

Explanation of symbols

1, 21 Semiconductor substrate 2, 22 Element isolation region

3, 23, 24 Gate insulating films 4, 25, 26 Gate electrodes 5, 27, 28 Gate sidewalls 6, 29, 31 Source regions 7, 30, 32 Drain regions 8, 33, 34 Conductive layer 9 Channel formation region 10 Stress Control film 13, 37 Plasma 35 Stress control film 36 Mask layer 40 n-channel formation region 41 p-channel formation region

Claims (6)

Forming a transistor on the substrate;
Forming a stress control film for generating stress in the transistor;
And a step of adjusting the stress of the stress control film by performing a heat treatment or a plasma treatment on the stress control film after forming the stress control film.   The method for manufacturing a semiconductor device according to claim 1, wherein the heat treatment is a heat treatment at a temperature exceeding 500 ° C. at least.   The transistor is a field effect transistor, and the stress control film is a stress control film that generates stress in a channel formation region of the field effect transistor, and the step of performing the heat treatment includes the stress of the stress control film, 3. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is adjusted in a direction in which the tensile stress increases. Forming a first conductivity type field effect transistor having a first channel formation region and a second conductivity type field effect transistor having a second channel formation region on a semiconductor substrate;
Forming a stress control film for generating stress in the first channel formation region and the second channel formation region on the first conductivity type field effect transistor and the second conductivity type field effect transistor;
Forming a mask layer on the stress control film;
Removing the mask layer on the second conductivity type field effect transistor;
Applying a plasma treatment to the stress control film in a portion where the mask layer has been removed.   The method for manufacturing a semiconductor device according to claim 1, wherein the plasma treatment is a plasma treatment using a gas containing ammonia or hydrogen. 5. The method of manufacturing a semiconductor device according to claim 1, wherein the step of performing the plasma treatment is a step of adjusting a stress of the stress control film in a direction in which a tensile stress decreases.

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