JP2007093460A - Semiconductor testing apparatus and method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor testing method capable of simultaneously performing a function test and a power supply voltage test. <P>SOLUTION: A semiconductor testing apparatus is composed of a testing board 1 mounting an LSI 11 to be tested and an LSI testing apparatus 2. A power supply pin to be a monitoring object of the LSI 11 is connected to a monitor waveform point 122 of a window comparator 12. A power supply part 22 of the LSI testing apparatus 2 supplies power supply voltage to the LSI 11 and a reference voltage waveform point 121. When the power supply voltage of the LSI 11 is within a prescribed voltage range, it is output from a comparator output point 123 at a high-level, and when not within the prescribed voltage range, it is output at a low level. The test pattern output from the function test pattern output part 21 is input into the LSI 11. The output of the LSI 11 in response to the test pattern, together with the output of the window comparator 12, is processed by a function test result determination part 23. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor test apparatus and a semiconductor test method for testing a semiconductor device such as an LSI.

Conventionally, in an LSI (Large Scale Integrated Circuits) test, a function test for inspecting whether the LSI operates normally as a logic circuit, and a power supply voltage test for inspecting whether an abnormality has occurred in the power supply voltage of the LSI And was done independently. Note that Patent Documents 1 to 5 are known as prior art references related to the present application.
Japanese Patent No. 3558964 JP 07-003458 A Japanese Patent Laid-Open No. 07-072224 Japanese Patent Laid-Open No. 10-068476 JP 2004-128759 A

  However, in the method of performing the function test and the power supply voltage test independently, the time for performing the test for each test is required separately, and the time required for the test becomes long. In addition, since the function test is performed on the assumption that the power supply voltage of the semiconductor device to be tested is normal, the tester confirms that the power supply voltage of the semiconductor device is normal using a measuring instrument such as an oscilloscope. It was necessary to monitor constantly.

If an abnormal phenomenon such as an abnormal current or latch-up due to a surge in the power supply voltage or a short circuit inside the semiconductor device under test occurs during the function test, the test is interrupted and an error occurs. However, when the tester detects a power supply voltage abnormality using a measuring instrument or the like, the test cannot be interrupted immediately after the abnormality is detected.

  The present invention has been made in consideration of the above circumstances, and an object thereof is to provide a semiconductor test apparatus capable of performing a function test and a power supply voltage test simultaneously.

  The present invention has been made to solve the above problems, and the invention according to claim 1 generates a test pattern for a function test and outputs the test pattern to a semiconductor device to be tested, Power supply voltage determination means for determining whether the power supply voltage of the semiconductor device is within a predetermined voltage range; power supply means for supplying power to the semiconductor device and the power supply voltage determination means; and for the input test pattern A semiconductor comprising: result determination means for determining a test result from the response output of the semiconductor device and the output of the power supply voltage determination means; and storage means for holding the test result of the result determination means Test equipment.

  According to a second aspect of the present invention, in the first aspect of the present invention, the power supply voltage determining unit includes an adjusting unit that adjusts the voltage range.

  The invention according to claim 3 is the current mirror circuit according to claim 2, wherein the adjusting means is a current mirror circuit capable of adjusting the voltage range by changing a resistance value of a variable resistor. It is said.

  According to a fourth aspect of the present invention, there is provided a connection procedure for connecting a power supply terminal of a semiconductor device to be tested and a power supply voltage determination means for determining whether the power supply voltage is within a predetermined voltage range, A power supply procedure for supplying a power supply voltage to the semiconductor device and the power supply voltage determination means; a test pattern input procedure for inputting a test pattern for a function test to the semiconductor device; and a response output of the semiconductor device to the input test pattern And a determination procedure for determining a test result from the output of the power supply voltage determination means.

  The invention according to claim 5 is the invention according to claim 4, further comprising an adjustment procedure for adjusting the voltage range of the power supply voltage determination means.

  According to the present invention, both the test pattern output means for performing the function test and the power supply voltage determination means for monitoring (testing) the power supply voltage are provided, and the function test and the power supply voltage test can be performed simultaneously. The test time can be shortened as compared with the conventional technique in which the function test and the power supply voltage test need to be performed separately. In addition, it is possible to monitor the power supply voltage during the function test and store the power supply voltage monitoring result in the storage means, so that the tester does not monitor the power supply voltage using a measuring instrument during the function test. The function test result measured with normal power supply voltage can be obtained.

  In addition, since it is possible to detect an abnormality in the power supply voltage of the semiconductor device during the function test, the function test is interrupted when the abnormality in the power supply voltage occurs, and the tester can clarify the cause. Furthermore, it is possible to identify the test pattern input to the semiconductor device at the time when the power supply voltage abnormality occurs by examining the function test result stored when the power supply voltage abnormality occurs. It can be used to elucidate the cause of

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an outline of a semiconductor test apparatus according to an embodiment of the present invention. In FIG. 1, an LSI test board 1 is a board for mounting an LSI to be tested. The LSI test apparatus 2 is an apparatus that performs various tests on the LSI mounted on the LSI test board 1. The semiconductor test apparatus in the claims refers to the LSI test board 1 and the LSI test apparatus 2 in the present embodiment.

  The LSI 11 on the LSI test board 1 is an LSI to be tested. The LSI 11 operates by inputting power from one or a plurality of power supply terminals, performs a predetermined logical operation on data input from the input terminal, and outputs the operation result from the output terminal. The window comparator 12 (power supply voltage determination means) is a window comparator circuit that monitors the power supply voltage in the LSI 11. A reference voltage waveform point 121 in the window comparator 12 is a point to which a power supply voltage supplied from the LSI test apparatus 2 is input.

  The monitor waveform point 122 is a point that is connected to the power supply terminal of the LSI 11 and monitors the power supply voltage in the LSI 11. The comparator output point 123 is an output of the window comparator 12 and is connected to the LSI test apparatus 2.

  A function test pattern output unit (test pattern output means) 21 in the LSI test apparatus 2 generates a test pattern and outputs it to the LSI 11 when a function test of the LSI 11 is performed. The power supply unit (power supply means) 22 supplies a power supply voltage serving as a reference during the test to the LSI 11 and the reference voltage waveform point 121.

  The function test result determination unit (result determination unit) 23 is an expected pattern expected as a normal LSI 11 response output to the test pattern output from the function test pattern output unit 21, and an output pattern actually output from the LSI 11 during the test. Are compared. Further, the output from the comparator output point 123 of the window comparator 12 is inputted and stored in the storage unit 24 together with the output pattern from the LSI 11 described above.

  The storage unit 24 (storage unit) is a memory that stores the output pattern from the LSI 11 determined by the function test result determination unit 23 and the result of the power supply voltage.

  FIG. 2 is a circuit diagram showing a circuit of the window comparator 12. In FIG. 2, the resistor R1 has one end connected to the power supply VCC and the other end connected to the collector of the transistor Q1 and the bases of the transistors Q1, Q2, and Q3. The window width adjustment volume R2 (adjustment means) is a variable resistor for adjusting the window width of the window comparator 12, and has one end connected to the emitter of the transistor Q1 and the other end connected to the power supply VEE.

  The resistor R3 has one end connected to the emitter of the transistor Q2 and the other end connected to the power source VEE. The resistor R4 has one end connected to the emitter of the transistor Q3 and the other end connected to the power supply VEE.

  The positive input terminal of the operational amplifier OP1 is connected to the monitor waveform point 123, and the negative input terminal and the output terminal are short-circuited. The output terminal of the operational amplifier OP1 is connected to one end of the resistor R6 and the + input terminal of the comparator CP1, and operates as a voltage follower (buffer).

  The + input terminal of the operational amplifier OP2 is connected to the reference voltage waveform point 121, the − input terminal and the output terminal are short-circuited, and operate as a voltage follower (buffer). The output terminal of the operational amplifier OP2 is connected to one end of the resistor R5 and the + input terminal of the comparator CP2.

  The negative input terminal of the comparator CP1 is connected to the resistor R5 and the collector of the transistor Q2. The negative input terminal of the comparator CP2 is connected to the other end of the resistor R6 and the collector of the transistor Q3.

  The resistor R7 has one end connected to the output terminal of the comparator CP1 and the output terminal of the comparator CP2, and the other end connected to the input terminal of the operational amplifier OP3. The output terminal of the operational amplifier OP3 is connected to the comparator output point 123.

  Next, the operation of the above-described embodiment will be described with reference to FIG. In FIG. 2, the circuits of transistors Q1, Q2, Q3, resistors R1, R3, R4 and window width adjustment volume R2 have a current mirror circuit configuration. Current I2 flows into the collector of transistor Q2 and current flows into the collector of transistor Q3. I3 is equal to the current I1 flowing into the collector of the transistor Q1.

  When the resistance value of the window width adjustment volume R2 is changed, the current I1 is changed, and the current I2 and the current I3 are also changed through the current mirror circuit. As the current I2 changes, the amount of voltage drop due to the resistor R5 changes, and the voltage applied to the negative input terminal of the comparator CP1 changes. Similarly, when the current I3 changes, the amount of voltage drop due to the resistor R6 changes, and the voltage applied to the negative input terminal of the comparator CP2 changes.

  When the voltage at the monitor waveform point 122 is set to Vin, the voltage at the output terminal of the operational amplifier OP1 operating as a voltage follower becomes the same Vin. At this time, the voltage at the + input terminal of the comparator CP1 is Vin, and the voltage at the − input terminal of the comparator CP2 is Vin−R6 × I3.

  When the voltage at the reference voltage waveform point 121 is set to Vref, the voltage at the output terminal of the operational amplifier OP2 operating as a voltage follower becomes the same Vref. At this time, the voltage at the + input terminal of the comparator CP2 is Vref, and the voltage at the − input terminal of the comparator CP1 is Vref−R5 × I2.

  Accordingly, the output of the comparator CP1 becomes High when Vin> Vref−R5 × I2, and conversely becomes Low when Vin <Vref−R5 × I2. On the other hand, the output of the comparator CP2 becomes High when Vref> Vin−R6 × I3 (that is, Vin <Vref + R6 × I3), and conversely, when Vref <Vin−R6 × I3 (that is, Vin> Vref + R6 × I3). Becomes Low.

  The comparators CP1 and CP2 are both open drain type outputs, and the voltage input to the operational amplifier OP3 via the resistor R7 is High only when both the output of the comparator CP1 and the output of the comparator CP2 are High. The operational amplifier OP3 amplifies and outputs the input voltage according to the voltage range that can be input by the LSI test apparatus.

  As described above, when the voltage Vin falls within a predetermined voltage range, that is, Vref−R5 × I2 <Vin <Vref + R6 × I3, the output from the comparator output point 123 of the window comparator 12 becomes High, and Vin <Vref. When −R5 × I2 or Vref + R6 × I3 <Vin, the output of the window comparator 12 is Low.

  Next, the procedure of the LSI test method will be described with reference to FIGS. When testing the LSI 11, first, one power supply terminal of the LSI 11 to be tested is selected and connected to the monitor waveform point 122 of the window comparator 12. Subsequently, power is supplied from the power supply unit 22 of the LSI test apparatus 2 to the reference voltage waveform point 121 of the LSI 11 and the window comparator 12.

  After the power is supplied, the window width adjustment volume R2 of the window comparator 12 is adjusted, and the voltage width at which the input to the operational amplifier OP3 of the window comparator 12 becomes High is adjusted. Specifically, the voltage at the reference voltage waveform point 121 is fixed, the power supply voltage supplied to the LSI 11 is varied, and the voltage at which the output of the window comparator 12 is inverted from High to Low or from Low to High (threshold voltage). Is detected.

  If the detected threshold voltage does not match the threshold voltage required for the power supply of the LSI 11, the window width adjustment volume R2 is adjusted, and the threshold voltage is detected again by the same method. This procedure is repeated until the detection threshold voltage matches the threshold voltage required for the power supply of the LSI 11.

  After the adjustment of the window width, the window comparator 12 outputs a high level when the power supply voltage of the LSI 11 is within a specified voltage range, and the window comparator 12 outputs a low level when it is outside the specified voltage range. To do.

  When the adjustment of the window width adjustment volume R2 is completed, the expected value of the output from the window comparator 12 is set to the aforementioned expected pattern held by the function test result determination unit 23.

  In setting the expected value, for example, the last bit of the expected value pattern of the function test shown in FIG. In the present embodiment, since the High level is output from the window comparator 12 to the function test result determination unit when the power supply voltage of the LSI 11 is within a predetermined range, the last 1 of the expected value pattern is output. High is set in the bit.

  Subsequently, the test pattern is output from the function test pattern output unit 21 to the input terminal of the LSI 11, and the response output of the LSI 11 with respect to the test pattern output from the output terminal of the LSI 11 is acquired by the function test result determination unit 23. The function test result determination unit 23 captures the output from the window comparator 12 simultaneously with the acquisition of the function test result.

  The function test result determination unit 23 determines whether the output of the window comparator 12 is High level or Low level, and adds the determination result to the last 1 bit of the response output pattern output from the LSI 11. Thereafter, the function test result determination unit 23 stores the pattern after the addition of the window comparator determination result in the storage unit 24.

  The function test result determination unit 23 compares the pattern after the output of the window comparator 12 is added with the above-described expected value pattern, and determines that the power supply voltage is abnormal if the last one bit is different. Thus, in this embodiment, it is possible to simultaneously monitor the power supply voltage and perform the function test.

  Therefore, the test can be interrupted immediately after it is determined that there is an abnormality in the power supply voltage, and the tester can investigate the cause, and the test can be continued with the abnormality in the power supply voltage as before. Disappear. Further, since the power supply voltage is automatically monitored by the LSI test apparatus 2, it is not necessary for the tester to constantly monitor the power supply voltage with an oscilloscope or the like.

  Furthermore, by referring to the history of function test results stored in the storage unit 24, it is possible to specify what test pattern is input to the LSI 11 when the power supply voltage abnormality occurs. Furthermore, it is possible to specify in which process of the test pattern processing performed by the LSI 11 the abnormality of the power supply voltage has occurred.

  As mentioned above, although embodiment of this invention was explained in full detail, the concrete structure is not restricted to this embodiment, The design change etc. of the range which does not deviate from the summary of this invention are included.

  The present invention is suitable for use in a semiconductor test apparatus for testing a semiconductor such as an LSI.

It is the block diagram which showed the outline | summary of the semiconductor testing apparatus concerning embodiment of this invention. FIG. 2 is a circuit diagram illustrating a circuit of the window comparator 12 in FIG. 1. An example of an expected value pattern held by the function test result determination unit 23 of FIG. 1 is shown.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... LSI test board, 2 ... LSI test apparatus, 11 ... LSI, 12 ... Window comparator (power supply voltage determination means), 21 ... Function test pattern output part (test pattern output means), 22 ... Power supply part, 23 ... Function test Result determination unit (result determination unit), 24 ... storage unit (storage unit), R2 ... window width adjustment volume (adjustment unit)

Claims (5)

Test pattern output means for generating a test pattern for function test and outputting it to a semiconductor device to be tested,
Power supply voltage determination means for determining whether the power supply voltage of the semiconductor device is within a predetermined voltage range;
Power supply means for supplying power to the semiconductor device and the power supply voltage determination means;
A result determination means for determining a test result from a response output of the semiconductor device with respect to the input test pattern and an output of the power supply voltage determination means;
Storage means for holding the test result of the result determination means;
A semiconductor test apparatus comprising:   The semiconductor test apparatus according to claim 1, wherein the power supply voltage determination unit includes an adjustment unit that adjusts the voltage range.   3. The semiconductor test apparatus according to claim 2, wherein the adjusting means is a current mirror circuit capable of adjusting the voltage range by changing a resistance value of a variable resistor. A connection procedure for connecting a power supply terminal of a semiconductor device to be tested and a power supply voltage determination means for determining whether the power supply voltage is within a predetermined voltage range;
A power supply procedure for supplying a power voltage to the semiconductor device and the power voltage determination means;
Test pattern input procedure for inputting a test pattern for function test to the semiconductor device,
A determination procedure for determining a test result from a response output of the semiconductor device with respect to the input test pattern and an output of the power supply voltage determination means;
A semiconductor test method comprising:   The semiconductor test method according to claim 4, further comprising an adjustment procedure for adjusting the voltage range of the power supply voltage determination unit.

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