JP2007041868A - Timing constraint generating device of logic synthesis, and logic synthesizing method and program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To generate an RTL (register transfer level) and timing constraints, to unify management and to prevent of the occurrences of errors, such as correction omission and mismatching. <P>SOLUTION: A constraint generating device 110 is provided with a means which inputs a hardware descriptive sentence from a storing means that stores hardware description (RTL) described in a hardware description language to scan the hardware descriptive sentence, checks whether or not a predetermined keyword exists in a comment field of an input/output terminal declarative statement, extracts a parameter corresponding to the keyword when the keyword exists, and generates from the keyword and the parameter timing constraint information which corresponds to the keyword and is adapted to a syntax format to be used by a logic synthesizer for performing logic synthesis from hardware description, and the logic synthesizer 102 synthesizes logic circuits so as to satisfy the timing constraint information to the hardware description. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an automatic design apparatus and method for a semiconductor integrated circuit device, and more particularly to an apparatus and method suitable for use in automatic generation of logic synthesis timing constraints and a program.

  A logic synthesizer used in the design process of a semiconductor integrated circuit inputs a hardware description statement describing a logic circuit using a hardware description language (HDL) such as a register transfer level (RTL), for example, and manufactures a predetermined semiconductor. Automatically generate the best netlist for your technology. As is well known, for example, VHDL, Verilog, etc., RTL is a hardware description that expresses logic as a register and a logic function between registers, and a logic synthesizer inputs an RTL file and inputs a chip area and delay. Optimize to meet time constraints.

  FIG. 4 is a diagram showing an overall configuration of a conventional logic synthesis system that performs logic synthesis. The logic synthesis device 102 inputs the RTL hardware description 101 stored in the storage device, inputs the timing constraint 103 stored in the storage device, and other design constraints (for example, chip area, power consumption, etc.) Logic synthesis is performed to satisfy the constraint conditions. The logic synthesis apparatus 102 normally performs logic expansion to the gate level independent of semiconductor manufacturing technology, such as assignment of states to state machines, assignment of flip-flops, and generation of combinational logic, and depends on semiconductor manufacturing technology. Logic optimization is performed within a range not to be performed (for example, the number of logic stages is adjusted so as to satisfy the delay time constraint). Then, mapping to a specific semiconductor manufacturing technology is performed. That is, the logic gate and flip-flop are replaced with a library cell of a specific semiconductor manufacturing technology.

  For an apparatus that performs logic synthesis in consideration of constraint information at the time of logic synthesis, refer to Patent Document 1 for an apparatus that generates a delay constraint value for logic synthesis.

JP 2000-215224 A

  In the conventional logic synthesis system described with reference to FIG. 4, timing constraints are created manually and supplied to the logic synthesis device 102 separately from the RTL.

  For this reason, when a terminal name is changed or a terminal is added in the RTL hardware description, the timing constraint needs to be corrected. In the above conventional logic synthesis system, the creation of RTL and timing constraints and the management of the created information are performed separately, and timing constraint omissions and timing constraint mismatches (for example, original timing constraint values) Error) may occur.

  In addition, it is necessary for a designer or the like to create a timing constraint separately while looking at the description contents of the RTL file, and the design TAT (Turn Around Time) becomes long.

  Persons in charge of managing the contents of the RTL file and the timing constraint file are required, and it is difficult to reduce manpower and man-hours.

  The invention disclosed in the present application has the following configuration in order to solve the above problems.

  The apparatus according to the present invention scans by inputting a hardware description sentence from a hardware description file in which a logic circuit is described in a hardware description language, and a predetermined keyword exists in the comment column of the hardware description sentence. If the keyword is present in the annotation column, an extraction means for extracting a parameter set corresponding to the keyword from the annotation column, and the keyword and the parameter are used to determine the keyword. Conversion means for automatically generating constraint information corresponding to a format used in a logic synthesis device that performs logic synthesis from the hardware description sentence.

  In the present invention, the extraction means includes a keyword predetermined as a timing constraint for the input terminal and / or the output terminal in the comment column of the declaration statement of the input terminal and / or the output terminal in the hardware description sentence. In this case, a numerical parameter defined in association with the keyword is extracted in the annotation column, and the conversion unit is configured to input the input terminal name and / or output terminal name, the keyword, and the numerical parameter, Timing constraint information related to the input terminal and / or the output terminal is generated.

  The apparatus according to the present invention includes a logic synthesis device that reads the hardware description sentence from the hardware description file and synthesizes a logic circuit so as to satisfy the constraint information.

According to the method of the present invention, the hardware description sentence is inputted and scanned from a storage means storing a hardware description sentence in which a logic circuit is described in a hardware description language, and predetermined in an annotation column of the hardware description sentence. A first step of extracting a parameter corresponding to the keyword from the annotation field;
A second step of generating constraint information corresponding to the keyword from the keyword and the extracted parameter and storing the constraint information in a storage unit;
including.

The computer program according to the present invention inputs and scans the hardware description sentence from the storage means storing the hardware description sentence in which the logic circuit is described in the hardware description language, and stores it in the annotation column of the hardware description sentence in advance. Checking whether a defined keyword exists, and if the keyword exists, a first process of extracting a parameter corresponding to the keyword from the annotation field;
It comprises a program for causing a computer to execute a second process of generating constraint information corresponding to the keyword from the keyword and the extracted parameter and storing it in a storage means.

  According to the present invention, RTL and timing constraints are centrally managed, so that timing constraint errors, setting omissions, and the like are prevented, thereby contributing to a reduction in design TAT.

  The above-described present invention will be described with reference to the accompanying drawings in order to explain in more detail. In the present invention, regarding a hardware description statement that describes a semiconductor integrated circuit (logic circuit) to be designed in a hardware description language, an annotation (comment) portion of a declaration statement of an input terminal and / or an output terminal is used as a timing constraint. Predetermined predetermined keywords and parameters (numerical data) are defined using an editor or the like.

  The constraint generation apparatus according to the present invention inputs a hardware description sentence, and in the case of a declaration statement of an input terminal and / or an output terminal, whether or not a predetermined keyword predetermined as a timing constraint exists in the comment field. If a predetermined keyword exists, the parameter corresponding to the keyword is extracted from the annotation column, and the grammar format used by the logic synthesis device that performs logic synthesis from the hardware description based on the extracted keyword and parameter Timing constraint information conforming to (syntax form) is generated, and the generated timing constraint information is stored in the storage means. The logic synthesis device synthesizes the logic circuit so as to satisfy the hardware description and the generated timing constraint. Hereinafter, description will be made with reference to examples.

  FIG. 1 is a diagram for explaining the system configuration of an embodiment of the present invention. A statement declaring the input / output terminal of the hardware description at the RTL level is defined as one terminal per line as follows.

input A;
output B;
input C;

  The symbol “;” is a comment (comment) symbol, and the part from “;” to the line feed code is the comment (comment) part.

In this embodiment, the annotation part (comment part), for example,
// XXX = 200 or
// YYY = 100
Describe the keyword and parameter pair.

For example, an input terminal declaration statement,
input A; // XXX = 200
, “// XXX” in the comment part after the symbol “;” is a keyword (a pseudo instruction indicating an input terminal timing constraint) indicating a timing constraint of the input terminal. Further, “= 200” following this keyword “// XXX” indicates that the value of the timing constraint is 200. That is, “// XXX = 200”, which is a comment statement in the declaration statement of the input terminal (terminal name A), indicates that the timing constraint of the input terminal A is 200 units.

Also, output terminal declaration statement
output B; // YYY = 100
, “// YYY” in the comment part after the symbol “;” is a keyword (a pseudo instruction indicating an output terminal timing constraint) indicating a timing constraint of the output terminal. Further, “= 100” following this keyword “// YYY” indicates that the value of the timing constraint is 100. That is, “// YYY = 100”, which is a comment in the declaration statement of the output terminal (terminal name B), indicates that the timing constraint of the output terminal B is 100 units.

input A; // XXX = 200 <line feed>
output B; // YYY = 100 <line feed>
For example, the RTL file with timing constraint information added to the comment part is created at any time before the logic synthesis even when the original RTL file is created or after the RTL file is created. May be.

  The keywords “// XXX” and “// YYY” in the comment part are limited to “// XXX” and “// YYY” as long as they are keywords determined with the constraint generation device 110. Instead, any keyword can be used.

  The constraint generation device 110 reads an RTL file with timing constraint information added to the comment portion of the terminal declaration statement, and extracts the keywords and numerical parameters added to the terminal from the annotation (comment) portion of the terminal declaration portion. The extraction unit 111 includes an automatic conversion unit 112 that generates syntax timing constraint information used in the logic synthesis device 102 based on the extracted keyword and numerical value, and stores the generated timing constraint information in the storage device 103 that stores the timing constraint.

For example, a one-line declaration statement
input A; // XXX = 200
From the timing constraint information,
set_input_delay 200 A
Is generated.

One line of declaration statement
output B; // YYY = 100
From the timing constraint information,
set_output_delay 100 B
Is generated.

  FIG. 2 is a flowchart showing a processing procedure (program processing procedure by a computer) of the constraint generation device 110 of FIG.

  The read extraction unit 111 of the constraint generation device 110 reads one line from the RTL file (step S11).

  If the read extraction unit 111 does not read the line as a result of the read and detects the end of file (EOF) (YES in step S12), the process ends.

  When the line can be read (when it is not EOF) (NO in step S12), the read extraction unit 111 checks whether or not it is an input / output terminal declaration statement (step S13).

  If it is not an input / output terminal declaration statement (NO in step S13), the process proceeds to step S11. In the case of an input / output terminal declaration statement (YES in step S13), the read extraction unit 111 extracts the terminal name of the input / output terminal (step S14).

  The read extraction unit 111 advances the character pointer in one line to the comment symbol “;” (step S15).

  If the end of one line (EOL) (YES in step S16), that is, if there is no comment, the process proceeds to step S11.

  When there is a comment (NO in step S16), the read extraction unit 111 checks whether there is a keyword (for example, // XXX, // YYY) (step S17).

  If there is no keyword (NO in step S17), since it is a normal comment, the process proceeds to step S11.

  When there is a keyword (YES in step S17), the read extraction unit 111 extracts numerical data after the symbol “=”. When there is a keyword, the read extraction unit 111 identifies which timing constraint is input or output depending on the keyword type (// XXX, // YYY).

  If the parameter is not defined (NO in step S18), that is, if there is no numerical data after the symbol “=”, the read extraction unit 111 outputs a syntax error and proceeds to step S11.

  If there is a parameter (YES in step S18), the read extraction unit 111 extracts numerical data following the symbol “=” (step S19).

Then, the automatic conversion unit 112 of the constraint generation device 110 is based on the timing constraint information (numerical data), which is the timing constraint of input or output based on the terminal name, keyword acquired by the read extraction unit 111
set_input_delay number, terminal name,
Or
set_output_delay A numerical value and a terminal name are generated (step S20), the generated timing constraint information is stored in a storage device referred to by the logic synthesis device 102 (step S21), and the process proceeds to step S11.

  FIG. 3A is a diagram illustrating an example of a connection relationship between the input terminals A, B, and C. FIG. The input / output terminal declaration corresponding to FIG. 3A is as shown in FIG. Timing constraint information as shown in FIG. 3C is generated from the comment portion of the input / output terminal declaration in FIG.

  According to the present embodiment, since the timing constraint is described in the comment portion of the terminal declaration statement, it is possible to prevent timing constraint errors and omissions. In addition, timing constraints that have been created manually can be automatically generated, reducing the number of man-hours.

  Furthermore, timing constraints inconsistencies can be detected by reading and checking a plurality of modules. For example, the timing constraint mismatch is detected from the connection relationship between the input terminal and the output terminal. In the configuration of FIG. 3A, matching is performed when the timing constraints of the output terminal (OUTPUT B) of the circuit 201, the input terminal (INPUT A) of the circuit 202, and the input terminal (INPUT C) of the circuit 203 are not all the same value. It will be lacking sex. According to the present embodiment, inconsistency is detected when the set values of timing constraints should be the same or different from the connection relation of the circuits.

  Further, timing constraint information for a logic synthesis device (tool) of another vendor can be created by changing the method of keyword conversion. By changing the syntax of the constraint information generated on the constraint generation device side, it is possible to support a plurality of logic synthesis devices, and correction on the logic synthesis device side is unnecessary.

  As described above, according to the present embodiment, by defining the definition of the timing constraint in the RTL file, the RTL and the timing constraint can be centrally managed.

  Although the present invention has been described with reference to the above embodiment, the present invention is not limited to the configuration of the above embodiment, and various modifications that can be made by those skilled in the art within the scope of the present invention. Of course, modifications are included.

It is a figure which shows the system configuration | structure of one Example of this invention. It is a flowchart which shows the process sequence of one Example of this invention. It is a figure explaining one Example of this invention. It is a figure which shows the conventional system configuration.

Explanation of symbols

DESCRIPTION OF SYMBOLS 101 RTL file 102 Logic synthesis apparatus 103 Timing restrictions 104 Other restrictions 105 Netlist 110 Constraint generation apparatus 111 Reading extraction part 112 Automatic conversion part 201-203 Circuit

Claims (9)

Whether or not there is a predetermined keyword in the annotation column of the hardware description sentence by inputting and scanning the hardware description sentence from the storage means storing the hardware description file in which the logic circuit is described in the hardware description language And when the keyword is present in the annotation column, an extraction means for extracting a parameter set corresponding to the keyword from the annotation column;
Conversion means for automatically generating constraint information corresponding to the keyword based on the keyword and the parameter and adapted to a format used in a logic synthesis device that performs logic synthesis from the hardware description sentence;
A constraint generation device characterized by comprising: In the hardware description sentence, the extraction means includes a keyword predetermined as a timing constraint of the input terminal and / or the output terminal in the comment column of the declaration sentence of the input terminal and / or the output terminal. In the comment field, extract the numeric parameter defined in association with the keyword,
The conversion unit generates timing constraint information related to the input terminal and / or the output terminal based on the input terminal name and / or the output terminal name, the keyword, and the numerical parameter. The constraint generation device according to claim 1. The constraint generation device according to claim 1 or 2,
Storage means for storing the hardware description file;
A logic synthesizer that automatically synthesizes a logic circuit so as to satisfy the constraint information by reading a hardware description from the hardware description file;
A logic synthesis system characterized by comprising: Whether or not a predetermined keyword exists in the comment column of the hardware description sentence by inputting and scanning the hardware description sentence from the storage means storing the hardware description file describing the logic circuit in the hardware description language And when the keyword is present in the annotation column, a first step of extracting a parameter set corresponding to the keyword from the annotation column;
A second step of automatically generating constraint information corresponding to the keyword based on the keyword and the parameter, the constraint information conforming to a format used in a logic synthesis tool for performing logic synthesis from the hardware description sentence; ,
A logic synthesis method characterized by comprising: In the first step, when a keyword predetermined as a timing constraint of the input terminal and / or the output terminal exists in the comment column of the declaration statement of the input terminal and / or the output terminal in the hardware description sentence In the annotation field, a numerical parameter defined in association with the keyword is extracted,
The second step generates timing constraint information related to the input terminal and / or the output terminal based on the input terminal name and / or output terminal name, the keyword, and the numerical parameter. The logic synthesis method according to claim 4.   6. The logic synthesis method according to claim 4, further comprising a step of reading the hardware description sentence from the storage means storing the hardware description file and synthesizing a logic circuit so as to satisfy the constraint information. . Whether or not a predetermined keyword exists in the comment column of the hardware description sentence by inputting and scanning the hardware description sentence from the storage means storing the hardware description file describing the logic circuit in the hardware description language And when the keyword is present in the annotation field, a first process for extracting a parameter set corresponding to the keyword from the annotation field;
A second processing step of automatically generating constraint information corresponding to the keyword based on the keyword and the parameter, the constraint information conforming to a format used in a logic synthesis tool for performing logic synthesis from the hardware description sentence; When,
A program that causes a computer to execute. The program according to claim 7, wherein
In the first processing, when a keyword predetermined as a timing constraint of the input terminal and / or the output terminal exists in the comment column of the declaration statement of the input terminal and / or the output terminal in the hardware description sentence In the annotation field, a numerical parameter defined in association with the keyword is extracted,
The second process generates timing constraint information related to the input terminal and / or the output terminal based on the input terminal name and / or output terminal name, the keyword, and the numerical parameter. Program. The program according to claim 7, wherein
A program for causing the computer to execute a process of reading out the hardware description sentence from the storage means storing the hardware description file and synthesizing a logic circuit so as to satisfy the constraint information.

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