JP2007041621A - Mask pattern correction system for semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To correct a process-induced proximity effect due to an etching transfer difference occurring when a plurality of gate materials are etched in one device. <P>SOLUTION: In the mask pattern correction system, respective regions according to materials or processes are extracted by a region extracting unit 22a from mask pattern data preliminarily stored in a pattern data storing unit 21, adjacent pattern distances including other materials of the mask pattern are calculated in the extracted regions by a control unit 20. A plurality of correction values of the mask pattern for each material are memorized in a correction table 24. The extracted region and the memorized correction values of the mask pattern for each material are referred and selected in a correction table referring unit 23a. The mask pattern data stored in the pattern data storing unit 21 are corrected for each material or a process in a correction pattern merging unit 26 based on the selected correction values. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a mask pattern correction system for an exposure mask used in a lithography process in manufacturing a semiconductor device.

  In recent years, with the advancement of semiconductor devices, demands for higher speed and higher integration of transistors have become stricter year by year. As an example of a high-speed transistor, a buried channel type MOS transistor as shown in FIG. 7, for example, is generally known.

  In the buried channel MOS transistor, as shown in FIG. 7, a shallow n-type layer 2 having a conductivity type opposite to that of the substrate 1 is formed on the semiconductor surface by ion implantation or the like. However, since the depletion type MOS transistor is formed only by forming the n-type layer, the enhancement type embedded channel MOS transistor is usually cut by using the work function difference or the like.

The enhancement type is often used such that a p ⁺ type polycrystalline Si gate electrode 3 is used for an n channel element and an n ⁺ type polycrystalline Si gate electrode is used for a p channel element. In this method, the gate material is changed depending on the type of transistor.

  In such a MOS transistor, as shown in FIG. 8, a channel through which a current passes is formed at a position slightly inside the semiconductor surface. Therefore, the electrons in the channel are not affected by surface scattering and can move with a mobility close to that of the bulk. Further, since the depletion layer spreads on the surface of the n-type layer on the drain side, the gate-drain capacitance is also reduced. Therefore, it is possible to expect an increase in device speed and an improvement in current driving capability.

  In addition, since there is no pn junction between the channel region and the source and drain, there is an advantage that avalanche collapse hardly occurs and characteristic variation due to hot carrier injection, which is a big problem in a short channel MOS device, is small.

As described above, when an embedded channel type transistor having great advantages in various aspects is applied to both an n channel transistor and a p channel transistor in the same device, as described above, the p ⁺ type polycrystalline Si is applied to the n channel element. A method using a gate electrode and an n ⁺ type polycrystalline Si gate electrode for a p-channel device is generally used.

Here, as shown in FIG. 9, consider a case where etching after lithography of two gate materials is performed simultaneously. As shown in FIG. 9A, a gate oxide film 6 is formed on the substrate 5, and p ⁺ polycrystalline Si 7a is formed on the n channel region, and n ⁺ polycrystalline Si 7b is formed on the P channel region. The After the gate underlayer is thus formed, resist patterns 8a and 8b are formed on the p ⁺ polycrystalline Si 7a and the n ⁺ polycrystalline Si 7b, as shown in FIG. 9B. Thereafter, a gate material as shown in FIG. 9C is obtained by a gate etching and resist stripping process.

In addition, techniques such as Patent Documents 1 to 3 below are known.
JP 08-32450 A JP 05-267251 A Japanese Patent Application Laid-Open No. 07-235673

  However, although the above two gate materials are both polycrystalline Si, since the impurity elements in the polycrystalline Si and their concentrations are different, the etching processing characteristics (shape after etching and etching conversion difference) are different for each gate material. ing.

  FIG. 10 is a process diagram showing an example in which etching is performed separately in order to make the etching processing characteristics the same for both gate materials.

First, as shown in FIG. 10A, a gate base is formed in each channel region, and then, as shown in FIG. 10B, a resist 9a is formed on p ⁺ polycrystalline Si 7a and n ⁺ polycrystalline Si 7b. And 9b are applied to form the gate pattern of the n-channel transistor. Thereafter, after n-channel transistor gate etching and resist stripping are performed as shown in FIG. 10 (c), resists 10a and 10b are applied and p-channel is applied as shown in FIG. 10 (d). A gate pattern of the transistor is formed. Then, as shown in FIG. 10E, after the gate etching of the p-channel transistor is performed, the resist is stripped to obtain two gate materials.

  However, even if etching is separately performed in such two channels, it is difficult to make the above-described etching characteristics completely the same.

  On the other hand, with the miniaturization of semiconductor devices, the problem of proximity effect (0PE: optical proximity effect) due to the process has become significant in recent years. Hereinafter, this proximity effect will be described.

  In a semiconductor device, process conditions are tuned so that a portion having the smallest process margin in the design circuit is as desired (as designed). This location is generally where the design dimension is the finest. For example, in the case of a semiconductor memory element, this corresponds to the memory cell portion having the highest pattern density. Here, when the process conditions are matched with the memory cell portion having a dense pattern, the peripheral circuit portion having a relatively sparse pattern is subjected to the proximity effect due to the process and does not necessarily conform to the design dimension. This phenomenon is referred to as proximity effect (OPE), and the causes of the phenomenon are the optical image after passing through the exposure mask, the latent image in the resist, the resist coating / developing process, the formation of the underlying film, the underlying film The effects of etching, post-treatment such as cleaning and oxidation, and the exposure mask process are intricately intertwined.

  This proximity effect is not necessarily caused only by optical factors. In order to solve the above-mentioned proximity effect, researches on OPC (Optical proximity correction) technology for correcting a design dimension on a mask have been made in many organizations. According to academic papers, current OPC is often a correction method using optical image simulation.

  However, as described above, some OPEs are caused by mask / wafer processes other than optical factors. Therefore, in order to realize high-precision correction, the OPE on a wafer that has undergone an actual total process is investigated, and the mask is processed. The above dimensions need to be corrected.

  As a one-dimensional gate pattern correction method considering this total process, the Bucket method (L. Liebman et al, SPl Vol. 2322 Photomask Technology and Management (1994) 229) is known. This is because the finished dimension measurement TEG (Test Element Group) called ACLV (Across the Chip Linewidth Variation) is used on the wafer that has undergone the total process, and the finished dimension bias (the difference between the finished dimension and the desired dimension) The relationship between the distances to adjacent patterns (pattern density dependence) is corrected to the design circuit by the finished dimension bias by using the density dependence of the pattern dimension variation obtained by electrical measurement as shown in FIG. It is a method to apply.

  That is, if the correction area is extracted, the adjacent space distances of all patterns are calculated. For example, if adjacent patterns are arranged as shown in FIG. 12, each pattern GC has a space distance a, b, c, d, e as shown.

  The correction table shown in FIG. 13 is referred to for these adjacent space distances a to e. Here, to which space on the correction table each adjacent space distance a to e is extracted, the pattern is corrected with the corresponding correction amount.

As described above, in the conventional OPC technology, when there is a transistor using a plurality of gate materials (p ⁺ -type polycrystalline Si gate and n ⁺ -type polycrystalline Si gate in the above-described conventional example) on the same device. It is impossible to realize highly accurate OPC for each gate material.

  In the future, devices that have multiple gate materials in the same gate pattern will require a mask pattern correction method that corrects the gate mask pattern for each gate material in order to achieve high-precision correction. It becomes. Further, Patent Document 1 to Patent Document 3 do not describe that such mask pattern correction is satisfied.

  Accordingly, an object of the present invention is to realize a highly accurate correction for each gate material when there are transistors using a plurality of different gate materials on the same device, and to correct the mask pattern of the gate for each gate material. It is an object of the present invention to provide a mask pattern correction system for a semiconductor device that does not perform.

  That is, the present invention provides a pattern data storage means for storing mask pattern data given in advance, and a plurality of areas for extracting each area for each material or processing process from the mask pattern data output from the pattern data storage means. Corresponding to the mask pattern data given in advance to the extraction means, the calculation means for calculating the adjacent pattern distance including other materials of the mask pattern in the plurality of extracted areas, and the pattern data storage means Correction value storage means for storing a plurality of mask pattern correction values for each material, areas extracted by the plurality of area extraction means, adjacent pattern distances calculated by the calculation means, and correction value storages Refer to the correction value of the mask pattern for each material stored in the means, and correct the area. Based on correction values selected by the plurality of correction value reference means and the correction value selected by the plurality of correction value reference means, the mask pattern data stored in the pattern data storage means is corrected for each material or processing process. And a correction pattern synthesis unit.

  In the present invention, preliminarily provided mask pattern data is stored in the pattern data storage means, and from the mask pattern data output from the pattern data storage means, a plurality of region extraction means are used for each material or processing process. Are extracted. Then, in the extracted plurality of regions, the adjacent pattern distance including other materials of the mask pattern is calculated by the calculation means. Further, a plurality of mask pattern correction values for each material are stored in the correction value storage means in correspondence with the mask pattern data given in advance to the pattern data storage means. Then, in the plurality of correction value selection means, the mask pattern correction value is selected and selected for each region extracted by the plurality of region extraction means and the material stored in the correction value storage means. The Based on the correction values selected by the plurality of correction value reference means, the mask pattern data stored in the pattern data storage means is corrected by the correction pattern synthesis unit for each material or processing process.

  According to the present invention, when there are transistors using a plurality of gate materials on the same device, high-precision OPC is realized for each gate material, and the mask pattern of the gate is corrected for each gate material. A mask pattern correction system for a semiconductor device can be provided. Thereby, transistor characteristics close to the design specifications can be realized.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 2 is a block diagram schematically showing a mask pattern correction system for executing a mask pattern correction method according to an embodiment of the present invention.

  In FIG. 2, a pattern data storage unit 21 for storing pattern data given by a semiconductor device designer is connected to the control unit 20 of the mask pattern correction system. The pattern data storage unit 21 is connected to region extraction units 22a, 22b, 22c,... For extracting the region for each gate material or process. In these region extraction units 22a, 22b, 22c,..., The region of the measurement pattern is extracted, and is extracted according to the interval between adjacent patterns such as 0.25 μm and 0.3 μm.

  The extracted data output from the region extraction units 22a, 22b, 22c,... Are supplied to correction table reference units 23a, 23b, 23c,. The correction table reference units 23a, 23b, 23c,... Refer to the correction table 24 provided outside the control unit 20 and storing correction values prepared in advance according to the extracted data. The correction value is output to the correction pattern acquisition units 25a, 25b, 25c,.

  The correction values output from the correction pattern acquisition units 25a, 25b, 25c,... Are supplied to the correction pattern merge unit 26 so that the design pattern is corrected for each gate material based on the correction values. It has become.

  Further, a display unit 28 such as a CRT display and an input unit 28 such as a keyboard are connected to the control unit 20.

By the way, as the correction of the gate pattern in the one-dimensional direction, the above-described Bucket method is well known. This embodiment shows a mask pattern correction method in which the present invention is applied to the Bucket method in a transistor in which a plurality of gate materials are used. As a transistor gate material is used more, p ⁺ -type polycrystalline Si gate electrode, assuming that n ⁺ -type polycrystalline Si buried channel CMOS transistor gate electrodes are used for p-channel devices for n-channel devices is doing.

  FIG. 3 is a diagram showing a pattern dimension measurement TEG called ACLV.

  The TEG in FIG. 3 shows that the density of the pattern adjacent to the electrical characteristic measurement pattern is 50%, but any other TEG can be used as long as the relationship between the pattern density and the finished dimension bias can be grasped. It doesn't matter. For example, the density of the adjacent pattern may be 100%.

A TEG as shown in FIG. 3 is formed with each gate material (p ⁺ -type polycrystalline Si gate electrode for n-channel device and n ⁺ -type polycrystalline Si gate electrode for p-channel device). As shown in FIG. 4, the relationship between pattern density and finished dimensional bias can be acquired.

As shown in FIG. 4, the impurity element and its concentration in the polycrystalline Si are different between the p ⁺ -type polycrystalline Si gate electrode and the n ⁺ -type polycrystalline Si gate electrode. And etching conversion difference) are different between the two. Therefore, the relationship between the pattern density and the finished dimensional bias is different for each gate material.

  Then, based on the characteristic diagram shown in FIG. 4, a rule correction table as shown in FIG. 6 is prepared. This correction table is a table in which the relationship between pattern density (distance to an adjacent pattern in the case of FIG. 6) and the correction amount of design data are associated with each other. This correction amount is added to the design pattern edge, and its value is an integral multiple of the mask drawing minimum grid.

  FIG. 5 is a diagram showing an example of the correction area.

  In FIG. 5, when the distance from the adjacent pattern of the n-type measurement pattern GCN is obtained, it is calculated including the p-type measurement pattern GCP. This is because if the measurement pattern GCP is not included, the distance between the adjacent patterns on the left edge of the pattern A in the drawing is erroneously set to q even though it is correctly p.

  Thus, a correction value is selected from the correction table shown in FIG. 6 based on the distance from the adjacent pattern.

As is clear from the characteristic diagram of FIG. 4, the distance from the adjacent pattern differs depending on whether the n ⁺ type or p ⁺ type polycrystalline Si gate is used. Therefore, an appropriate correction amount is selected according to the n-type and p-type types.

  Next, the operation of this mask pattern correction system will be described with reference to the flowchart of FIG.

First, in step S1, a correction area as shown in FIG. 5 is extracted. Next, in step S2, an n ⁺ type polycrystalline Si gate layer indicated by a measurement pattern GCN in FIG. 5 is extracted.

Next, in step S3, the adjacent pattern distance q of the n ⁺ -type polycrystalline Si gate layer is calculated include p ⁺ -type polycrystalline Si gate layer represented by the measurement pattern GCP. The reason is as described above.

In step S4, the correction table of the adjacent pattern of the n ⁺ type polycrystalline Si gate layer is referred to. An appropriate correction amount is selected according to the data of the correction table as shown in FIG. 6, and the pattern of the n ⁺ -type polycrystalline Si gate layer is corrected in the subsequent step S5.

Next, in step S6, the p ⁺ type polycrystalline Si gate layer indicated by the measurement pattern GCP in FIG. 5 is extracted. In step S7, the adjacent pattern distance of the p ⁺ -type polycrystalline Si gate layer is calculated contains n ⁺ -type polycrystalline Si gate layer represented by the measurement pattern GCN.

In step S8, the correction table of the adjacent pattern of the p ⁺ type polycrystalline Si gate layer is referred to. According to the data of the correction table as shown in FIG. 6, an appropriate correction amount is selected, and the pattern of the p ⁺ type polycrystalline Si gate layer is corrected in step S9.

  Thereafter, pattern synthesis of the corrected pattern is performed for each gate material. This pattern synthesis is performed by acquiring all the corrected gate patterns.

Thus, used correction table shown in FIG. 6, p ⁺ -type polycrystalline Si gate electrode and the n ⁺ -type polycrystalline Si correction of the design data at each gate electrode (the correction amount to the edge of the pattern Addition) is performed, and high-precision correction can be realized.

In the embodiment described above, a buried channel type CMOS transistor using a p ⁺ type polycrystalline Si gate electrode for an n channel element and an n ⁺ type polycrystalline Si gate electrode for a p channel element is assumed as a transistor. It can also be applied to other gate materials such as refractory silicide materials (WSi, TiSi, MoSi) and polymetals, or laminated structures of insulating films (cap materials using silicon nitride, silicon oxide, etc.) / Gate conductive materials. Needless to say.

  In the present embodiment, the gate layer has been described as an example, but it goes without saying that the present technique can be applied to any layer (such as a wiring layer) using a plurality of materials in the same layer.

  Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the present invention.

  Furthermore, the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. In addition, various inventions can be formed by appropriately combining a plurality of constituent elements disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, constituent elements over different embodiments may be appropriately combined.

It is a flowchart explaining operation | movement of a mask pattern correction | amendment system. 1 is a block diagram schematically illustrating a mask pattern correction system for performing a mask pattern correction method according to an embodiment of the present invention. It is the figure which showed the pattern dimension measurement TEG which quantifies the proximity effect resulting from a process. It is the characteristic view which showed the relationship between the distance with an adjacent pattern, and the difference of a desired pattern dimension. It is the figure which showed the example of the correction | amendment area | region. It is a figure showing the example of the correction table. It is a structural diagram of a buried channel type MOS transistor. It is an energy band figure of a buried channel type transistor. It is the figure which showed the gate processing process in the semiconductor device in which multiple gate materials exist. It is the figure which showed the gate processing process in the semiconductor device in which multiple gate materials exist. It is the characteristic view which showed the relationship between the distance to the adjacent pattern by the conventional correction system, and the amount of dimension movement. It is the figure which showed the example of the correction | amendment area | region. It is the figure which showed the example of the correction table of the conventional correction system.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 20 ... Control part, 21 ... Pattern data storage part, 22a, 22b, 22c, ... Area extraction part, 23a, 23b, 23c, ... Correction table reference part, 24 ... Correction table, 25a, 25b, 25c, ... Correction pattern acquisition , 26... Correction pattern merging unit, 27... Display unit, 28.

Claims (2)

Pattern data storage means for storing mask pattern data given in advance;
A plurality of region extraction means for extracting each region for each material or processing process from the mask pattern data output from the pattern data storage means;
In the extracted plurality of regions, a calculation means for calculating an adjacent pattern distance including other materials of the mask pattern;
Corresponding to the mask pattern data given in advance to the pattern data storage means, correction value storage means for storing a plurality of mask pattern correction values for each material,
With reference to the region extracted by the plurality of region extracting means, the adjacent pattern distance calculated by the calculating means, and the correction value of the mask pattern for each material stored in the correction value storing means, A plurality of correction value reference means for selecting a correction value of the area;
A correction pattern synthesis unit that corrects the mask pattern data stored in the pattern data storage unit for each material or processing process based on the correction values selected by the plurality of correction value reference units;
A mask pattern correction system for a semiconductor device, comprising:   2. The mask pattern correction system for a semiconductor device according to claim 1, wherein the regions extracted by the plurality of region extracting means are regions for each gate electrode material.

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