JP2006339670A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

A semiconductor device capable of sufficiently suppressing off-leakage current even when the gate length is 100 nm or less and a method for manufacturing the same are provided.
An N-type pocket layer is formed on the surface of a semiconductor substrate by ion-implanting phosphorus into the semiconductor substrate on which an N-type well, a gate insulating film, and a gate electrode are formed. The length of the gate electrode 33 (gate length) is 100 nm or less. Ion implantation is performed by oblique ion implantation from four directions. Further, for example, the implantation energy is 15 to 30 keV, and the dose amount is 3 × 10 ^{12 to} 1.5 × 10 ¹³ cm ⁻² per direction. According to this method, since the phosphorus ions are implanted in forming the N-type pocket layer 34, it is possible to suppress the generation of a strong electric field in the vicinity of the channel even if the gate length is reduced to 100 nm or less. it can. For this reason, it is possible to suppress the leakage current between BDs and reduce the off-leakage current.
[Selection] Figure 23

Description

  The present invention relates to a semiconductor device suitable for reducing off-leakage current and a manufacturing method thereof.

  Recently, the gate length of MOS transistors has been shortened due to a demand for reduction in chip size. In addition, in a battery-driven electronic device such as a cellular phone, that is, an electronic device that particularly requires a low off-leakage current, in a MOS transistor having a short gate length, in forming the extension layer and the pocket layer, N As the type impurity, As having a low diffusion coefficient is used. Specifically, As is used as an N-type impurity in a pocket layer of a P-channel MOS (PMOS) transistor and an extension layer of an N-channel MOS (NMOS) transistor. In order to suppress the short channel effect accompanying the shortening of the gate length, particularly the occurrence of off-leakage current and the decrease in threshold voltage, a method of increasing the channel impurity concentration has been conventionally employed.

When manufacturing an NMOS transistor, first, as shown in FIG. 26A, a gate insulating film 102 and a gate electrode 103 are formed on a semiconductor substrate 101 on which a P-type well is formed. Next, as shown in FIG. 26B, boron (B) ions are implanted to form a P-type pocket layer 104 on the surface of the semiconductor substrate 101. This ion implantation is performed by oblique ion implantation from four directions orthogonal to each other in plan view. The implantation energy is 5 to 10 keV, and the dose is 3 × 10 ^{12 to} 1.8 × 10 ¹³ cm ⁻² per direction. Next, as shown in FIG. 26C, arsenic (As) is ion-implanted to form an N-type extension layer 106 on the surface of the pocket layer 104. This ion implantation is performed from a direction perpendicular to the surface of the semiconductor substrate 101. The implantation energy is 2 to 5 keV, and the dose is 5 × 10 ^{14 to} 3 × 10 ¹⁵ cm ⁻² . Thereafter, deep N-type source / drain diffusion layers are formed to complete the NMOS transistor.

On the other hand, when manufacturing a PMOS transistor, first, as shown in FIG. 27A, a gate insulating film 132 and a gate electrode 133 are formed on a semiconductor substrate 131 on which an N-type well is formed. Next, as shown in FIG. 27B, an N-type pocket layer 134 is formed on the surface of the semiconductor substrate 131 by implanting As. This ion implantation is performed by oblique ion implantation from four directions orthogonal to each other in plan view. The implantation energy is 40 to 80 keV, and the dose is 3 × 10 ^{12 to} 1.5 × 10 ¹³ cm ⁻² per direction. Next, as shown in FIG. 27C, B-type ion implantation is performed to form a P-type extension layer 136 on the surface of the pocket layer 134. This ion implantation is performed from a direction perpendicular to the surface of the semiconductor substrate 131. The implantation energy is 0.2 to 0.5 keV, and the dose is 5 × 10 ^{14 to} 2 × 10 ¹⁵ cm ⁻² . Thereafter, deep P-type source / drain diffusion layers and the like are formed to complete the PMOS transistor.

JP-A-11-163157 JP-A-5-267331 Japanese Patent Laid-Open No. 6-224281 JP-A-6-338591 JP 2000-196077 A

  However, recently, when the gate length is 100 nm or less and the pocket layer is formed to increase the impurity concentration of the channel, the electric field at the PN junction near the extension becomes stronger, and the band-to-band tunnel leakage between the drain and the body is caused. growing. There is a problem that off-leakage current increases due to the tunnel leakage.

  The present invention has been made in view of such problems, and an object of the present invention is to provide a semiconductor device capable of sufficiently suppressing off-leakage current even when the gate length is 100 nm or less, and a method for manufacturing the same. .

  As a result of intensive studies to solve the above-mentioned problems, the present inventor has come up with the following aspects of the invention.

  A semiconductor device according to the present invention includes a semiconductor substrate, a gate insulating film and a gate electrode formed on the semiconductor substrate, and a pair of sidewall insulating films formed on the sides of the gate electrode. It has been. A pair of first P-type impurity diffusion layers formed in a self-aligned manner with respect to the gate electrode is formed on the surface of the semiconductor substrate at a first depth. Further, a pair of second P-type formed on the surface of the semiconductor substrate in a self-aligned manner with respect to the gate electrode and the sidewall insulating film at a second depth deeper than the first depth. An impurity diffusion layer is formed. A pair of N-type impurities formed between the pair of second P-type impurity diffusion layers, each adjacent to the pair of first P-type impurity diffusion layers and containing phosphorus; A diffusion layer is formed. In addition, the length of the gate electrode is 100 nm or less, and the proportion of phosphorus in the N-type impurity introduced into the N-type impurity diffusion layer is 30 atomic% or more.

  In the method for manufacturing a semiconductor device according to the present invention, first, a gate insulating film and a gate electrode having a length of 100 nm or less are formed on a semiconductor substrate. Next, a pair of N-type impurity diffusion layers are formed by introducing at least phosphorus into the surface of the semiconductor substrate using the gate electrode as a mask. Next, a pair of first P-type impurity diffusion layers are formed with a first depth by introducing P-type impurities into the surface of the semiconductor substrate using the gate electrode as a mask. Thereafter, a pair of sidewall insulating films are formed on the sides of the gate electrode. Then, by introducing P-type impurities into the surface of the semiconductor substrate using the gate electrode and the sidewall insulating film as a mask, a pair of second P-type impurity diffusion layers are deeper than the first depth. It is formed at the second depth. Further, among the N-type impurities introduced into the N-type impurity diffusion layer, the proportion of phosphorus is set to 30 atomic% or more.

  According to the present invention, even when the gate length is 100 nm or less, a strong electric field in the vicinity of the channel can be relaxed and a leakage current generated between the semiconductor substrate and the drain can be suppressed. For this reason, off-leakage current can be reduced.

  Hereinafter, embodiments of the present invention will be specifically described with reference to the accompanying drawings.

(Basic principle of the present invention)
First, the basic principle of the present invention will be described.

  The off-leakage current of the MOS transistor varies with the impurity concentration (channel dose) of the channel. In the conventional MOS transistor, the off-leakage current is smaller as the channel dose is higher. For this reason, conventionally, in order to suppress the short channel effect, a method of increasing the channel dose is employed. However, as described above, when the gate length is shorter, particularly when the gate length is 100 nm or less, the off-leakage current cannot be lowered below a certain value even if the channel dose is increased.

  Therefore, as a result of intensive studies by the inventors of the present invention to find out the cause, the following matters have been clarified. FIG. 1 is a cross-sectional view showing types of off-leakage current in an NMOS transistor.

In the NMOS transistor, in the off state, for example, the potential of the gate electrode 5 formed on the semiconductor substrate 1 via the gate insulating film 4 is applied with 0 V, and the potential of the source region 2 formed on the surface of the semiconductor substrate 1 is applied. Also, the potential of the semiconductor substrate 1 is set to 0 V, and a voltage of 1.2 V is applied to the drain region 3 formed on the surface of the semiconductor substrate 1.

  At this time, a source-drain (SD) leakage current flows between the source region 2 and the drain region 3, and a gate-drain (GD) tunnel leakage current flows between the gate electrode 5 and the drain region 3, A body-drain (BD) leakage current flows between the semiconductor substrate 1 and the drain region 3. The sum of these becomes the off-leakage current.

  The relationship between the channel dose and the off-leakage current in the PMOS transistor is as shown in FIG. With the gate length of the conventional MOS transistor, an off-leakage current is allowed if the channel dose is a certain amount. In this range, as shown in FIG. 2, since the influence of the leakage current between SDs is extremely large and the influence of the leakage current between BDs is extremely small, the leakage current between SDs is reduced by increasing the channel dose. Off-leakage current is suppressed.

  Conventionally, however, it has been considered that a higher channel dose is necessary to shorten the gate length. However, as the channel dose is increased, the influence of the leakage current between BDs increases, In addition, the off-leakage current increases. That is, as shown in FIG. 2, there is a minimum value in the off-leakage current indicated by the solid line.

  For this reason, in a MOS transistor having a gate length of 100 nm or less, it is impossible to reduce the off-leakage current simply by increasing the channel dose as in the prior art.

  Therefore, the inventors of the present invention have made further studies to weaken the electric field in the vicinity of the channel. In the PMOS transistor, by using P having a large diffusion coefficient for forming the pocket layer, The inventors have conceived that the leakage current between BDs can be suppressed by using P for forming the extension layer.

  FIG. 3 is a graph showing the relationship between the channel dose and the off-leakage current while comparing the As pocket with the P pocket. As shown in FIG. 3, in the PMOS transistor, the leakage current between BDs is lower when the P pocket is used (two-dot chain line) than when the As pocket is used (solid line). The minimum value of off-leakage current is decreasing. This means that the off-leakage current can be further reduced by increasing the channel dose. In the NMOS transistor, the same effect can be expected by using the P extension layer instead of the conventional As extension layer.

(Effect in N-channel MOS transistor)
Next, the effect of the P extension layer in the NMOS transistor will be described. FIG. 4 is a graph showing the relationship between the gate length and the threshold voltage Vth in an NMOS transistor having an As extension layer. FIG. 4 shows the result of measurement performed on an NMOS transistor fabricated using B for forming the pocket layer, As for forming the extension layer, and P for forming the source / drain diffusion layer. . In FIG. 4, the dose amount of the pocket layer is different between ▲, ●, and ◆, and the dose amounts of ● and ♦ are 1.5 times and 2 times the dose amount of ▲, respectively.

  As shown in FIG. 4, when the gate length is longer than about 115 nm (0.115 μm), the variation in the threshold voltage Vth due to the difference in the gate length is relatively small regardless of the dose amount. However, when the gate length is smaller than 100 nm (0.1 μm), the threshold voltage Vth fluctuates (rolls off) due to the difference in gate length, and the short channel effect becomes remarkable.

Further, when the As extension layer is used, the drain current Id (off-leakage current) when the gate voltage Vg is 0 V with a gate length of 115 nm, even if the dose of the pocket layer is low, as shown in FIG. to 10 ^-11 to (a / μm) degree has been achieved, the gate length of 80 nm, as shown in FIG. 6, increasing the dose of the pocket layer in order to increase the threshold voltage as, The off-leakage current fluctuated greatly according to the dose of the pocket layer. Here, the solid line, the broken line, and the two-dot chain line in FIGS. 5 and 6 are obtained with the same dose as ▲, ●, and ◆ in FIG. 4, respectively. The same applies to FIGS. 7 and 8 below.

  That is, when the As extension layer is used, as shown in FIGS. 5 and 6, when the gate length is 115 nm, the gate length is sufficiently low even if the dose amount (solid line) sufficiently reduces the off-leakage current. Is 80 nm or more, the off-leakage current increases by one digit or more, and even if the dose is 1.5 times (dashed line) or 2 times (two-dot chain line), it cannot be sufficiently reduced. The reduction has reached its limit.

  FIG. 7 is a graph showing a leakage current between BDs in the drain current Id shown in FIG. The thick line in FIG. 7 indicates the leakage current between BDs. More specifically, the thick solid line, the thick broken line, and the thick two-dot chain line indicate the leakage current between the BDs in the graph indicated by the solid line, the broken line, and the two-dot chain line in FIG. Is shown. When the As extension layer was used, as shown in FIG. 7, the BD leakage current increased as the pocket layer dose increased.

  In this situation, in the NMOS transistor, when the P extension layer is used instead of the As extension layer, an increase in leakage current between BDs accompanying an increase in the dose amount of the pocket layer can be suppressed. FIG. 8 is a graph showing the relationship between the gate voltage Vg and the drain current Id in an NMOS transistor having a P extension layer. FIG. 8 is obtained when the gate length is set to 80 nm as in FIGS.

  As shown in FIG. 8, when the P extension layer was used, the leakage current between BDs did not increase and was stable at a low value. For this reason, by increasing the dose amount of the pocket layer, it was possible to reduce the leakage current between SD and the off-leakage current.

  FIG. 9 shows the relationship between the gate length and the threshold voltage Vth in an NMOS transistor having a P extension layer for reference. In FIG. 9, ▲, ●, and ♦ indicate the results obtained under the same conditions as the same symbols in FIG. 4. As shown in FIG. 9, even when a P extension layer is used, a roll-off can be seen with a gate length of about 80 nm. However, since the P extension layer is used even in such a range, the off-leakage current can be reduced by increasing the dose of the pocket layer, that is, the channel dose, as shown in FIG.

  In forming the P extension layer, instead of forming the extension layer on both sides of the gate electrode as a mask in a self-aligning manner, a thin sidewall insulating film is formed on the side of the gate electrode. It is necessary to perform ion implantation. This is because P has a larger diffusion coefficient than As. FIG. 10 is a graph showing the relationship between the gate length and the threshold voltage Vth in an NMOS transistor having a P extension layer while comparing the presence or absence of a thin sidewall insulating film. FIG. 11 shows the gate length and off-leakage current. It is a graph which shows the relationship with Ioff, comparing the presence or absence of a thin sidewall insulating film. In FIGS. 10 and 11, ▲ and ◆ indicate the results when there is no thin sidewall insulating film and when there is a thin sidewall insulating film, respectively. As shown in FIGS. 10 and 11, when there is no thin sidewall insulating film (▲), when the gate length is 100 nm or less, roll-off is more remarkable and off-leakage current is high. For example, when the gate length is about 90 nm, the off-leakage current is lower by one digit or more than when the thin sidewall insulating film is formed (◆) and when the thin sidewall insulating film is not (▲). became.

(Effect in P-channel MOS transistor)
Next, the effect of the P pocket layer in the PMOS transistor will be described. FIG. 12 is a graph showing the relationship between the gate length and the threshold voltage Vth in a PMOS transistor having an As pocket layer. FIG. 12 shows the result of measurement performed on a PMOS transistor fabricated using As for forming the pocket layer, using B for forming the extension layer, and using B for forming the source / drain diffusion layer. . In FIG. 12, the dose amount of the pocket layer is different between ▲, ●, and ◆, and the dose amounts of ● and ♦ are two times and three times the dose amount of ▲, respectively.

  As shown in FIG. 12, when the gate length is longer than about 115 nm (0.115 μm), the variation of the threshold voltage Vth due to the difference in the gate length is small regardless of the dose amount. However, when the gate length is smaller than 100 nm (0.1 μm), the threshold voltage Vth fluctuates (rolls off) due to the difference in gate length, and the short channel effect becomes remarkable. This is the same tendency as the above-described NMOS transistor.

When the As pocket layer is used, the off-leakage current is about 10 ⁻¹¹ (A / μm) even when the dose of the pocket layer is relatively low as shown in FIG. On the other hand, at a gate length of 80 nm, as shown in FIG. 14, the off-leakage current greatly fluctuated according to the dose of the pocket layer. Here, the solid line, the broken line, and the two-dot chain line in FIGS. 13 and 14 are obtained with the same dose amount as ▲, ●, and ◆ in FIG. 12, respectively. The same applies to FIG. 15, FIG. 16, and FIG.

  When the As pocket layer is used, as shown in FIG. 14, when the gate length is 80 nm, the off-leakage current can be lowered to some extent by increasing the dose of the pocket layer. Even if the dose was increased further, the off-leakage current did not decrease, and the reduction of the off-leakage current reached the limit.

  FIG. 15 is a graph showing a leakage current between BDs in the drain current Id shown in FIG. The thick line in FIG. 1515 indicates the BD leakage current. More specifically, the thick solid line, the thick broken line, and the thick two-dot chain line indicate the leakage current between the BDs in the graph indicated by the solid line, the broken line, and the two-dot chain line in FIG. Is shown. When the As pocket layer was used, as shown in FIG. 15, the leakage current between BDs increased as the dose of the pocket layer increased.

  In such a situation, if a P pocket layer is used instead of an As pocket layer in a PMOS transistor, an increase in leakage current between BDs accompanying an increase in the dose of the pocket layer can be suppressed. FIG. 16 is a graph showing the relationship between the gate voltage Vg and the drain current Id in a PMOS transistor having a P pocket layer. FIG. 16 is obtained when the gate length is 80 nm as in FIGS. 14 and 15.

  As shown in FIG. 16, when the P pocket layer was used, the leakage current between BDs did not increase and was stable at a low value. For this reason, by increasing the dose amount of the pocket layer, it was possible to reduce the leakage current between SD and the off-leakage current.

  For reference, FIG. 17 shows a graph showing the relationship between the gate voltage Vg and the drain current Id in a PMOS transistor having a P pocket layer when the gate length is 115 nm. As can be seen from a comparison between FIG. 17 and FIG. 13, even when the gate length was 115 nm, the effect of reducing the off-leakage current accompanying the reduction of the leakage current between BDs was obtained.

  For reference, FIG. 18 shows the relationship between the gate length and the threshold voltage Vth in a PMOS transistor having a P pocket layer. In FIG. 18, ▲, ●, and ♦ indicate the results obtained under the same conditions as the same symbols in FIG. As shown in FIG. 18, even when a P pocket layer is used, a roll-off can be seen at a gate length of about 80 nm. However, since the P pocket layer is used even in such a range, the off-leak current can be reduced by increasing the dose of the pocket layer, that is, the channel dose, as shown in FIG.

  In the PMOS transistor, all the N-type impurities in the pocket layer need not be P, and As may be contained. When the inventors of the present application examined the relationship between the As ratio and the off-leakage current, the results shown in FIG. 19 were obtained. That is, among the N-type impurities in the pocket layer, if the As ratio is less than 0.7 (70%), that is, if the P ratio is 0.3 (30%) or more, the P pocket layer Similarly, a sufficiently low off-leakage current was obtained. Such a result can also be obtained with an NMOS transistor. In the NMOS transistor, all the N-type impurities in the extension layer do not have to be P, and As may be included. In this case, when the P ratio was 0.5 (50%) or more, a sufficiently low off-leakage current was obtained as in the P extension layer.

(Reference example)
Next, reference examples of the present invention will be described. However, here, for convenience, the structure of the semiconductor device will be described together with its manufacturing method. In the reference example, a semiconductor device including an NMOS transistor is manufactured. 20 to 22 are cross-sectional views illustrating a method of manufacturing a semiconductor device according to a reference example in the order of steps.

  In the reference example, first, as shown in FIG. 20A, a gate insulating film 12 and a gate electrode 13 are formed on a semiconductor substrate 11 such as a silicon substrate on which a P-type well is formed. The length of the gate electrode 13 (gate length) is 100 nm or less.

Next, as shown in FIG. 20B, a P-type impurity layer, for example, boron (B) is ion-implanted to form a P-type pocket layer (P-type impurity diffusion layer) 14 on the surface of the semiconductor substrate 11. . This ion implantation is performed, for example, by oblique ion implantation from four directions orthogonal to each other in plan view. Further, for example, the implantation energy is 5 to 10 keV, and the dose is 3 × 10 ^{12 to} 1.8 × 10 ¹³ cm ⁻² per direction.

  Next, as shown in FIG. 20C, a thin sidewall insulating film (first sidewall insulating film) 15 is formed on the sides of the gate insulating film 12 and the gate electrode 13. The thickness of the thin sidewall insulating film 15 is, for example, about 10 nm. When the thickness of the thin sidewall insulating film 15 is less than 5 nm, roll-off becomes remarkable and the threshold voltage may be lowered. If the thickness of the thin sidewall insulating film 15 exceeds 15 nm, the parasitic resistance may increase and the on-resistance may increase. For this reason, the thickness of the thin sidewall insulating film 15 is preferably about 5 to 15 nm.

Thereafter, as shown in FIG. 21A, phosphorus (P) ions are implanted to form an N-type extension layer (first N-type impurity diffusion layer) 16 on the surface of the pocket layer 14. This ion implantation is performed, for example, from a direction perpendicular to the surface of the semiconductor substrate 11. Further, for example, the implantation energy is 1 to 2.5 keV, and the dose is 5 × 10 ^{14 to} 2 × 10 ¹⁵ cm ⁻² .

  Subsequently, after an insulating film, for example, a silicon oxide film is formed on the entire surface, anisotropic etching is performed so that the insulating film remains only on the side of the thin sidewall insulating film 15, whereby FIG. As shown in FIG. 2, a sidewall insulating film (second sidewall insulating film) 17 is formed. The width of the sidewall insulating film 17 is, for example, about 75 nm. Therefore, the side wall insulating film 17 is wider than the side wall insulating film 15.

Thereafter, as shown in FIG. 21C, an N-type impurity, for example, phosphorus is ion-implanted at a high concentration, whereby a deep N-type source / drain diffusion layer (second N-type impurity diffusion) is formed on the surface of the semiconductor substrate 11. Layer) 18 is formed. This ion implantation is performed, for example, from a direction perpendicular to the surface of the semiconductor substrate 11. Further, for example, the implantation energy is 4 to 10 keV, and the dose is 6 × 10 ^{15 to} 1.2 × 10 ¹⁶ cm ⁻² . The depth of the N-type source / drain diffusion layer 18 is deeper than the depth of the N-type extension layer 16. After the ion implantation, annealing is performed to activate the implanted impurities.

  Then, as shown in FIG. 22, the formation of the interlayer insulating film 19, the opening of the contact hole 20 reaching the N-type source / drain diffusion layer 18 with respect to the interlayer insulating film 19, and the conductive material 21 to the contact hole 20 The semiconductor device is completed by embedding and forming a wiring (not shown).

  The semiconductor device manufactured in this way has a structure shown in FIG.

  According to such a reference example, when forming the N-type extension layer 16, phosphorus ions having a diffusion coefficient larger than that of arsenic are implanted while using the thin sidewall insulating film 15 as an offset film. Even if it is shortened to 100 nm or less, generation of a strong electric field in the vicinity of the channel can be suppressed. For this reason, it is possible to suppress the leakage current between BDs and reduce the off-leakage current.

(Embodiment)
Next, an embodiment of the present invention will be described. However, also here, for convenience, the structure of the semiconductor device will be described together with its manufacturing method. In the present embodiment, a semiconductor device including a PMOS transistor is manufactured. 23 to 25 are cross-sectional views showing the method of manufacturing a semiconductor device according to the embodiment of the present invention in the order of steps.

  In the present embodiment, first, as shown in FIG. 23A, for example, a gate insulating film 32 and a gate electrode 33 are formed on a semiconductor substrate 31 such as a silicon substrate on which an N-type well is formed. The length of the gate electrode 33 (gate length) is, for example, 100 nm or less.

Next, as shown in FIG. 23B, an N-type pocket layer (N-type impurity diffusion layer) 34 is formed on the surface of the semiconductor substrate 31 by ion implantation of phosphorus. This ion implantation is performed, for example, by oblique ion implantation from four directions orthogonal to each other in plan view. Further, for example, the implantation energy is 15 to 30 keV, and the dose amount is 3 × 10 ^{12 to} 1.5 × 10 ¹³ cm ⁻² per direction.

Next, as shown in FIG. 23C, a P-type extension layer (first P-type impurity diffusion layer) 36 is formed on the surface of the pocket layer 34 by ion implantation of a P-type impurity, for example, boron. . This ion implantation is performed from a direction perpendicular to the surface of the semiconductor substrate 31, for example. Further, for example, the implantation energy is set to 0.2 to 0.5 keV, and the dose amount is set to 5 × 10 ^{14 to} 2 × 10 ¹⁵ cm ⁻² .

  Thereafter, after an insulating film, for example, a silicon oxide film is formed on the entire surface, anisotropic etching is performed so that this insulating film remains only on the sides of the gate insulating film 32 and the gate electrode 33. As shown in FIG. 2B, a sidewall insulating film 37 is formed. The width of the sidewall insulating film 37 is, for example, about 75 nm.

Subsequently, as shown in FIG. 24B, a deep P-type source / drain diffusion layer (second P-type impurity) is formed on the surface of the semiconductor substrate 31 by ion implantation of a P-type impurity such as boron at a high concentration. Diffusion layer) 38 is formed. This ion implantation is performed from a direction perpendicular to the surface of the semiconductor substrate 31, for example. Further, for example, the implantation energy is 3 to 6 keV, and the dose is 4 × 10 ^{15 to} 6 × 10 ¹⁵ cm ⁻² . The depth of the P-type source / drain diffusion layer 38 is deeper than the depth of the P-type extension layer 36. After the ion implantation, annealing is performed to activate the implanted impurities.

  Then, as shown in FIG. 25, the formation of the interlayer insulating film 39, the opening of the contact hole 40 reaching the P-type source / drain diffusion layer 38 to the interlayer insulating film 39, and the conductive material 41 to the contact hole 40 The semiconductor device is completed by embedding and forming a wiring (not shown).

  The semiconductor device manufactured in this way has a structure shown in FIG.

  According to such an embodiment of the present invention, phosphorus is ion-implanted in forming the N-type pocket layer 34, so that a strong electric field is generated in the vicinity of the channel even if the gate length is reduced to 100 nm or less. This can be suppressed. For this reason, similarly to the reference example, it is possible to suppress the leakage current between BDs and reduce the off-leakage current.

  Hereinafter, various aspects of the present invention will be collectively described as supplementary notes.

(Appendix 1) a semiconductor substrate;
A gate insulating film and a gate electrode formed on the semiconductor substrate;
A pair of first sidewall insulating films formed on the sides of the gate electrode;
A pair of second sidewall insulation films sandwiching the first sidewall insulation film between the gate electrodes and having a width wider than the width of the first sidewall insulation film;
A pair of first N-type impurity diffusion layers formed in a self-aligned manner with respect to the gate electrode and the first sidewall insulating film at a first depth on the surface of the semiconductor substrate and containing phosphorus When,
Formed on the surface of the semiconductor substrate in a self-aligned manner with respect to the gate electrode, the first sidewall insulating film, and the second sidewall insulating film at a second depth deeper than the first depth. A pair of second N-type impurity diffusion layers formed;
A pair of P-type impurity diffusion layers formed between the pair of second N-type impurity diffusion layers, each adjacent to the pair of first N-type impurity diffusion layers;
A semiconductor device comprising:

  (Supplementary note 2) The semiconductor device according to supplementary note 1, wherein a width of the first sidewall insulating film is 5 to 15 nm.

  (Supplementary note 3) The semiconductor device according to Supplementary note 1 or 2, wherein the first N-type impurity diffusion layer contains arsenic.

  (Additional remark 4) Any one of the additional remarks 1 thru | or 3 characterized by the ratio of phosphorus being 50 atomic% or more among the N-type impurities introduce | transduced in the said 1st N-type impurity diffusion layer. Semiconductor device.

(Appendix 5) a semiconductor substrate;
A gate insulating film and a gate electrode formed on the semiconductor substrate;
A pair of sidewall insulating films formed on the sides of the gate electrode;
A pair of first P-type impurity diffusion layers formed in a self-aligned manner with respect to the gate electrode at a first depth on the surface of the semiconductor substrate;
A pair of second P-type impurity diffusions formed in a self-aligned manner with respect to the gate electrode and the sidewall insulating film at a second depth deeper than the first depth on the surface of the semiconductor substrate. Layers,
A pair of N-type impurity diffusion layers formed between the pair of second P-type impurity diffusion layers, each adjacent to the pair of first P-type impurity diffusion layers and containing phosphorus. When,
A semiconductor device comprising:

  (Supplementary note 6) The semiconductor device according to supplementary note 5, wherein the N-type impurity diffusion layer contains arsenic.

  (Supplementary note 7) The semiconductor device according to supplementary note 5 or 6, wherein the N-type impurity introduced into the N-type impurity diffusion layer has a phosphorus ratio of 30 atomic% or more.

  (Supplementary note 8) The semiconductor device according to any one of supplementary notes 1 to 7, wherein a length of the gate electrode is 100 nm or less.

(Additional remark 9) The process of forming a gate insulating film and a gate electrode on a semiconductor substrate,
Forming a pair of P-type impurity diffusion layers by introducing P-type impurities into the surface of the semiconductor substrate using the gate electrode as a mask;
Forming a pair of first sidewall insulating films on the sides of the gate electrode;
A pair of first N-type impurity diffusion layers are formed with a first depth by introducing at least phosphorus into the surface of the semiconductor substrate using the gate electrode and the first sidewall insulating film as a mask. Process,
Forming a pair of second sidewall insulating films sandwiching the first sidewall between the gate electrode and having a width wider than that of the first sidewall insulating film;
Using the gate electrode, the first sidewall insulating film, and the second sidewall insulating film as a mask, an N-type impurity is introduced into the surface of the semiconductor substrate to form a pair of second N-type impurity diffusions. Forming a layer at a second depth deeper than the first depth;
A method for manufacturing a semiconductor device, comprising:

  (Additional remark 10) The manufacturing method of the semiconductor device of Additional remark 9 characterized by making the width | variety of said 1st sidewall insulating film into 5 thru | or 15 nm.

  (Additional remark 11) The manufacturing method of the semiconductor device of Additional remark 9 or 10 characterized by introduce | transducing arsenic with phosphorus in the surface of the said semiconductor substrate in the process of forming a said 1st N type impurity diffused layer.

  (Supplementary note 12) The N-type impurity introduced into the first N-type impurity diffusion layer has a phosphorus content of 50 atomic% or more, according to any one of supplementary notes 9 to 11 Semiconductor device manufacturing method.

  (Additional remark 13) The process of forming the said P-type impurity diffusion layer has the process of ion-implanting the said P-type impurity from the direction inclined with respect to the surface of the said semiconductor substrate, Additional remark 9 thru | or 12 characterized by the above-mentioned. A manufacturing method of a semiconductor device given in any 1 paragraph.

(Additional remark 14) The process of forming a gate insulating film and a gate electrode on a semiconductor substrate,
Forming a pair of N-type impurity diffusion layers by introducing at least phosphorus into the surface of the semiconductor substrate using the gate electrode as a mask;
Forming a pair of first P-type impurity diffusion layers at a first depth by introducing P-type impurities into the surface of the semiconductor substrate using the gate electrode as a mask;
Forming a pair of sidewall insulating films on the sides of the gate electrode;
By introducing P-type impurities into the surface of the semiconductor substrate using the gate electrode and the sidewall insulating film as a mask, a pair of second P-type impurity diffusion layers are formed in a second region deeper than the first depth. Forming at a depth of
A method for manufacturing a semiconductor device, comprising:

  (Supplementary note 15) The method for manufacturing a semiconductor device according to supplementary note 14, wherein in the step of forming the N-type impurity diffusion layer, arsenic is introduced into the surface of the semiconductor substrate together with phosphorus.

  (Supplementary note 16) The method for manufacturing a semiconductor device according to supplementary note 14 or 15, wherein the proportion of phosphorus in the N-type impurity introduced into the N-type impurity diffusion layer is 30 atomic% or more.

  (Supplementary Note 17) Any one of Supplementary Notes 14 to 16, wherein the step of forming the N-type impurity diffusion layer includes a step of implanting phosphorus ions from a direction inclined with respect to the surface of the semiconductor substrate. A method for manufacturing the semiconductor device according to the item.

  (Supplementary note 18) The method for manufacturing a semiconductor device according to any one of supplementary notes 9 to 17, wherein in the step of forming the gate electrode, a length of the gate electrode is set to 100 nm or less.

It is sectional drawing which shows the kind of off-leakage current in an NMOS transistor. It is a graph which shows the relationship between the channel dose amount and off-leakage current in a PMOS transistor. It is a graph which shows the relationship between a channel dose amount and an off-leakage current, comparing an As pocket and a P pocket. It is a graph which shows the relationship between the gate length and threshold voltage Vth in the NMOS transistor provided with the As extension layer. It is a graph which shows the relationship between the gate voltage and drain current which were obtained when the gate length was 115 nm using an As extension layer. It is a graph which shows the relationship between the gate voltage and drain current which were obtained when the gate length was 80 nm using an As extension layer. It is a graph which shows the leakage current between BD in the drain current Id shown in FIG. It is a graph which shows the relationship between the gate voltage Vg and the drain current Id in the NMOS transistor provided with the P extension layer. It is a graph which shows the relationship between the gate length and threshold voltage Vth in the NMOS transistor provided with the P extension layer. It is a graph which shows the relationship between the gate length and threshold voltage Vth in the NMOS transistor provided with P extension layer, comparing the presence or absence of a thin sidewall. It is a graph which shows the relationship between gate length and off-leakage current Ioff, comparing the presence or absence of a thin sidewall. It is a graph which shows the relationship between the gate length and threshold voltage Vth in a PMOS transistor provided with an As pocket layer. It is a graph which shows the relationship between the gate voltage and drain current which were obtained when the gate length was 115 nm using an As pocket layer. It is a graph which shows the relationship between the gate voltage and drain current which were obtained when the gate length was 80 nm using an As pocket layer. It is a graph which shows the leakage current between BD in the drain current Id shown in FIG. It is a graph which shows the relationship between the gate voltage Vg and the drain current Id in the PMOS transistor (gate length: 80 nm) provided with the P pocket layer. It is a graph which shows the relationship between the gate voltage Vg and the drain current Id in the PMOS transistor (gate length: 115 nm) provided with the P pocket layer. It is a graph which shows the relationship between the gate length and threshold voltage Vth in the PMOS transistor provided with the P pocket layer. It is a graph which shows the relationship between the ratio of As and off-leakage current. It is sectional drawing which shows the manufacturing method of the NMOS transistor which concerns on a reference example in order of a process. FIG. 21 is a cross-sectional view illustrating a method for manufacturing an NMOS transistor according to a reference example, in order of processes, following FIG. 20; FIG. 22 is a cross-sectional view illustrating a method of manufacturing the NMOS transistor according to the reference example in order of processes subsequent to FIG. 21; It is sectional drawing which shows the manufacturing method of the PMOS transistor which concerns on embodiment of this invention to process order. FIG. 24 is a cross-sectional view illustrating the method of manufacturing the PMOS transistor according to the embodiment of the present invention in the order of steps, following FIG. 23. FIG. 25 is a cross-sectional view illustrating the method of manufacturing the PMOS transistor according to the embodiment of the present invention in the order of steps, following FIG. 24. It is sectional drawing which shows the manufacturing method of the conventional NMOS transistor in order of a process. It is sectional drawing which shows the manufacturing method of the conventional PMOS transistor in order of a process.

Explanation of symbols

1: Semiconductor substrate 2: Source region 3: Drain region 4: Gate insulating film 5: Gate electrode 11, 31: Semiconductor substrate 12, 32: Gate insulating film 13:33: Gate electrode 14: P-type pocket layer 15: Thin side Wall insulating film 16: N-type extension layer 17, 37: Side wall insulating film 18: N-type source / drain diffusion layer 19, 39: Interlayer insulating film 20, 40: Contact hole 21, 41: Conductive material 34: N-type pocket Layer 36: P-type extension layer 38: P-type source / drain diffusion layer

Claims (2)

A semiconductor substrate;
A gate insulating film and a gate electrode formed on the semiconductor substrate;
A pair of sidewall insulating films formed on the sides of the gate electrode;
A pair of first P-type impurity diffusion layers formed in a self-aligned manner with respect to the gate electrode at a first depth on the surface of the semiconductor substrate;
A pair of second P-type impurity diffusions formed in a self-aligned manner with respect to the gate electrode and the sidewall insulating film at a second depth deeper than the first depth on the surface of the semiconductor substrate. Layers,
A pair of N-type impurity diffusion layers formed between the pair of second P-type impurity diffusion layers, each adjacent to the pair of first P-type impurity diffusion layers and containing phosphorus. When,
Have
The gate electrode has a length of 100 nm or less;
A semiconductor device characterized in that the proportion of phosphorus in the N-type impurity introduced into the N-type impurity diffusion layer is 30 atomic% or more. Forming a gate insulating film and a gate electrode having a length of 100 nm or less on a semiconductor substrate;
Forming a pair of N-type impurity diffusion layers by introducing at least phosphorus into the surface of the semiconductor substrate using the gate electrode as a mask;
Forming a pair of first P-type impurity diffusion layers at a first depth by introducing P-type impurities into the surface of the semiconductor substrate using the gate electrode as a mask;
Forming a pair of sidewall insulating films on the sides of the gate electrode;
By introducing P-type impurities into the surface of the semiconductor substrate using the gate electrode and the sidewall insulating film as a mask, a pair of second P-type impurity diffusion layers are formed in a second region deeper than the first depth. Forming at a depth of
Have
A method for manufacturing a semiconductor device, characterized in that the proportion of phosphorus in the N-type impurity introduced into the N-type impurity diffusion layer is 30 atomic% or more.

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