JP2006331564A - Nonvolatile semiconductor memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress decrease in a data output rate for binary read to multiple-valued read without requiring complicated control, without increasing chip area. <P>SOLUTION: A nonvolatile memory block (2) has a plurality of the nonvolatile memory cells capable of storing information with the binary and multiple values. A volatile memory block (11) is connected to the nonvolatile memory block and has a plurality of the volatile memory cells for storing the information to be rewritable by the binary. A data path selection circuit (19) switches a read path for the binary data and externally outputs it. A control circuit, when externally outputting the information read from the nonvolatile memory cell for storing the binary information, controls so that an output operation rate for the above volatile memory block is made quicker than externally outputting the information read from the nonvolatile memory cell for storing the multi-valued information, and performs the external output for the information stored by the binary and the external output for the information stored by a quadruple value at the same information output rate. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a nonvolatile semiconductor memory having nonvolatile memory cells capable of storing information in binary and multilevel values.

  There is a flash memory as a nonvolatile semiconductor memory capable of electrically writing information. The nonvolatile memory transistor of the flash memory has a charge storage region, and a relatively high threshold voltage is set by injecting charge into the charge storage region. The threshold voltage is lowered by releasing the charge from the charge storage region. Information is stored according to the difference in threshold voltage. A relatively high threshold voltage or a low threshold voltage is set for a nonvolatile memory transistor that stores information in binary. In order to increase the storage density of the flash memory, information should be stored in multiple values. For example, when information is stored in four values corresponding to 2-bit data, any one of four types of threshold voltage distributions corresponding to 2-bit data is set in the nonvolatile memory transistor. The threshold voltage of the nonvolatile memory transistor is determined according to the amount of charge stored in the charge storage region. For example, with respect to the “11” state in which electrons are emitted from the charge storage region, 2-bit data can be obtained by a total of four states of “10” state, “00” state, and “01” state in which the amount of accumulated electrons is sequentially increased Can be remembered. In the read operation, for example, the upper bit of the 2-bit storage information is determined by performing the read operation with the word line voltage between the threshold voltage distribution in the “10” state and the threshold voltage distribution in the “00” state. When the upper bit is a logical value “1”, the read operation is performed with the word line voltage between the threshold voltage distribution in the “11” state and the threshold voltage distribution in the “10” state, whereby the lower order of the stored information of 2 bits. Determine the bit. When the upper bit is a logical value “0”, the read operation is performed with the word line voltage between the threshold voltage distribution in the “00” state and the threshold voltage distribution in the “01” state, whereby the lower bit of the stored information of 2 bits. Determine the bit. Therefore, in reading of 4-level storage information, the word line selection and sensing operation for determining the upper bit and the word line selection and sensing operation for determining the lower bit must be performed separately. For this reason, the latency when reading four-level stored information is larger than when reading binary stored information. Therefore, binary information storage is advantageous in applications that require high-speed reading. For this reason, flash memories that can handle both 4-value information storage and 2-value information storage are provided.

  Patent Document 1 describes a flash memory having a nonvolatile memory cell capable of selecting binary information storage and multi-value information storage.

JP 2001-6374 A

  When the present inventor reads information stored in binary in a flash memory capable of storing information in both binary and quaternary, it corresponds to reading information stored in four values. We examined that half of the provided buffer memory and input / output terminals were not used and the data output rate was halved. For example, when selecting a word line of a nonvolatile memory cell in units of 8K per page, when reading information stored in four values, it is higher than each nonvolatile memory cell selected in the first word line selection operation. Bit storage information is detected and stored in the upper buffer memory. Next, lower bit storage information is detected for each nonvolatile memory cell selected by the second selection operation of the same word line and stored in the lower buffer memory. The storage information is output to the outside in units of bytes when the storage information of the upper 2 bits and the lower 2 bits for each nonvolatile memory cell has become 2K bytes in total. When reading out information stored in binary, the reading procedure is basically the same as that in quaternary reading, but the word line operation that is actually performed is only the first time, and the buffer used substantially is higher. There is only a side buffer. For this reason, in the output operation, only the data held in the upper buffer is output, and the data output rate is halved.

  The inventor has significantly changed the reading sequence of the binary reading in order to make the data output rates of the multi-level reading and the binary reading uniform, or has a bit correspondence between the sense latch of the flash memory and the buffer memory. However, if control is complicated by this, high-speed access by binary reading may be hindered. Further, if the physical circuit scale increases, the chip area increases, and the effect of improving the storage density by quaternary storage is reduced.

  An object of the present invention is to provide a nonvolatile semiconductor memory capable of suppressing a decrease in data output rate of binary reading with respect to multi-level reading.

  An object of the present invention is to provide a non-volatile semiconductor memory capable of suppressing a decrease in data output rate of binary reading with respect to multi-level reading without requiring complicated control and increasing a chip area. There is.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  [1] The nonvolatile semiconductor memory (1) includes a nonvolatile memory block (2), a volatile memory block (3), an input / output circuit (4), and a control circuit (5). The non-volatile memory block has a plurality of non-volatile memory cells (15) capable of storing information in binary and multilevel values. The volatile memory block is connected to the nonvolatile memory block and has a plurality of volatile memory cells that store information in a rewritable binary manner. The input / output circuit is connected to the volatile memory block and inputs / outputs information to / from the outside. The control circuit reads out the output operation speed of the volatile memory block from the nonvolatile memory cell storing multi-value information when outputting the information read from the nonvolatile memory cell storing binary information to the outside. Control to make information faster than when outputting information to the outside. Thereby, the external output of the information stored in binary and the external output of the information stored in 4-value are performed at the same output rate.

  According to the above means, even if the number of read information bits is reduced in the case of binary reading compared to multi-level reading, the same output rate as in the case of quaternary reading is obtained by increasing the output operation speed of the volatile memory block. The read data can be output to the outside. There is no need for complicated control, and it is not necessary to add a circuit such as a large-scale aligner along the memory array of the nonvolatile memory block.

  As one specific form of the present invention, the non-volatile memory block reads information in units of the prescribed number of bits by using a prescribed number of nonvolatile memory cells as an access unit. The volatile memory block has a buffer area (UBM, LBM) for storing information read from the non-volatile memory cells of the number of access units storing information in multiple values in units of the predetermined number of bits. . When the storage information in the nonvolatile memory cell is read as multi-value information storage, the control circuit takes out the outputs of the plurality of buffer areas in parallel and outputs them in parallel to the outside from the input / output circuit. When reading stored information as binary stored information, the output of one buffer area is taken out at a speed that is several times the parallel number of the parallel output, and the extracted information is taken at the same parallel bit number and speed as the parallel output. A parallel output is performed from the input / output circuit.

  As another specific form of the present invention, the nonvolatile memory cell stores four-value information as multiple values. The non-volatile memory block reads information in units of the specified number of bits using a specified number of non-volatile memory cells as an access unit. The volatile memory block has a buffer area (UBM, LBM) for storing information read from the non-volatile memory cell of the number of access units storing information in four values in units of the specified number of bits. . The volatile memory block performs a single data rate (SDR) output operation in which an output operation is performed in synchronization with one of the rising and falling edges of the clock, and an output operation in synchronization with both the rising and falling edges of the clock. It is possible to select a double data rate (DDR) output operation. The input / output circuit outputs a first output path for outputting the outputs of the plurality of buffer areas in parallel, and a second output path for dropping the output of one buffer area to the transfer rate of the first output path. Output path (21 to 23). The control circuit instructs the volatile memory block to perform a double data rate output operation when reading information stored in binary in the nonvolatile memory cell, and selects a second output path for the input / output circuit. And reading out the information stored in the nonvolatile memory cell in four values, the volatile memory block is instructed to perform a single data rate output operation, and the input / output circuit is selected for the first output path. Instruct.

  [2] A nonvolatile semiconductor memory according to another aspect of the present invention includes an input / output circuit (30, 30A), a plurality of memory banks (BNK0 to BNK3) connected to the input / output circuit, and a control circuit (31, 31A). , 34). The input / output circuit inputs / outputs information to / from the outside. The memory bank includes a volatile memory block (33) and a nonvolatile memory block (32). The volatile memory block is connected to the input / output circuit and has a plurality of volatile memory cells that store information in a rewritable binary manner. The non-volatile memory block is connected to the volatile memory block of the corresponding memory bank, and has a plurality of non-volatile memory cells capable of storing information in binary and multilevel values. When the control circuit reads out the information stored in binary in the nonvolatile memory cell, the control circuit reads out the storage information of the nonvolatile memory cell storing the multi-value information from the nonvolatile memory block of one selected memory bank. A plurality of nonvolatile memory blocks are selected so as to be the same as the number of read information bits at the time, the stored information is read from the nonvolatile memory cells of each nonvolatile memory block, and the read information is paralleled from the input / output circuit. Output externally.

  According to the above means, in the case of binary reading as compared with multi-level reading, even if the number of read information bits is reduced in units of memory banks, the read data of a plurality of memory banks are collectively output in parallel, so that 4 Read data can be output to the outside at the same output rate as in the case of value reading. There is no need for complicated control, and it is not necessary to add a circuit such as a large-scale aligner along the memory array of the nonvolatile memory block.

  As one specific mode of the present invention, when the control circuit reads information stored in binary in a nonvolatile memory cell, the stored information read from each of the selected nonvolatile memory blocks. Are stored in the volatile memory blocks of the corresponding memory banks, and the information output from the respective volatile memory blocks is combined by the input / output circuit and output to the outside in parallel. For example, the input / output circuit includes selectors (42, 43) for combining information output from a plurality of volatile memory blocks. Since the input / output circuit combines the information stored in a plurality of volatile memory blocks, the necessary circuit modification can be performed within the range of the number of information bits that interface the volatile memory block and the input / output circuit. The scale is small.

  As another specific mode of the present invention, when the control circuit reads information stored in binary in the nonvolatile memory cell, the control circuit reads from each of the selected nonvolatile memory blocks. The stored information is combined and stored together in a volatile memory block of a corresponding memory bank, and the stored information is output from the input / output circuit to the outside. For example, a selector (50, 51) for combining stored information read from a plurality of nonvolatile memory blocks is provided between the nonvolatile memory block and the volatile memory block. It is necessary to combine the information read from the nonvolatile memory block according to the signal interface scale with the volatile memory block in the memory bank.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, it is possible to suppress a decrease in the data output rate of binary reading with respect to multi-level reading without requiring complicated control and increasing the chip area.

<Flash memory>
FIG. 2 shows a block diagram of the flash memory. The flash memory 1 (LSI) is not particularly limited, but is formed on a single semiconductor substrate such as single crystal silicon by an integrated circuit manufacturing technique such as complementary MOS. The flash memory 1 includes a flash memory block (FLASH) 2 as a nonvolatile memory block, a buffer RAM (BMRY) 3 as a volatile memory block, an input / output circuit (I / O) 4, and a control circuit (CONT) 5. Have

  The flash memory block 2 includes a memory array (MARY) 10, a sense latch (SL) 11, a main amplifier (MA) 12, a power supply circuit (VPGEN) 13, and a high voltage driver (VPDRV) 14.

  The memory array 10 has a plurality of non-volatile memory cells 15 in which information can be written by initialization of a threshold voltage and a program. Although not particularly limited, the nonvolatile memory cell 15 is configured by a memory transistor having a stacked gate structure in which a memory gate is superimposed on a charge storage region via an insulating film. For example, the drain of the memory cell 15 is connected to the bit line BL, the source is connected to the source line SL, and the memory gate is connected to the word line WL. A large number of bit lines BL, word lines WL, and source lines SL are actually arranged, and selection thereof is performed by an output of a decoder (not shown) that decodes an address signal.

  The threshold voltage can be lowered by applying a circuit ground potential to the source, drain, and well of the memory cell 15 and applying a negative high voltage to the memory gate to move electrons in the charge storage region. it can. Here, lowering the threshold voltage of the memory cell 7 is referred to as initialization (erase). Further, a current is passed from the drain of the memory cell 15 to the source, hot electrons are generated on the substrate surface at the source end, and this is injected into the charge storage region by an electric field due to the high voltage of the memory gate, thereby increasing the threshold voltage. Can do. Increasing the threshold voltage of the memory cell 15 is referred to as a program. Information can be written by a program in two or four values. A high voltage necessary for erasing and programming is generated by the power supply circuit 13, and a high voltage necessary for the operation is selected and supplied to the high voltage driver 14. The output of the high voltage driver is supplied to the word line selected by the address decoder. To read the stored information, the bit line is precharged in advance, the memory transistor is selected with the predetermined read determination level as the word line selection level, and the stored information is changed by changing the current flowing in the bit line or changing the voltage level appearing on the bit line. Determine. A sense latch 11 is connected to the bit line, and the sense latch 11 latches the data read to the bit line. The sense latch 11 latches write data. The main amplifier 12 amplifies the data latched by the sense latch 11 and selected for output and outputs the amplified data to the buffer RAM 3.

  The buffer RAM 3 is composed of, for example, a static RAM (SRAM). The SRAM has, for example, a CMOS static latch as a memory cell, and stores information in binary in its storage node. The buffer RAM 3 operates in synchronization with the clock CLK, and its output operation is a single data rate (SDR) operation in which data output operation is performed in synchronization with either rising or falling of the clock CLK, or rising and rising of the clock CLK. A double data rate (DDR) operation in which a data output operation is performed in synchronization with both falling edges can be selectively performed. In the DDR operation, data can be input / output at a speed twice that of the SDR operation.

  The input / output circuit 4 includes a data input / output buffer (DATB) 17, a command input / output buffer (CMDB) 18, and a data path selection circuit (DPS) 19. The data input / output buffer 17 and the command input / output buffer 18 are interfaced with the outside. The data path selection circuit 19 makes it possible to select the connection form between the data input / output buffer 17 and the buffer RAM 3. The command input / output buffer 18 is connected to the control circuit 5. The command input / output buffer 18 supplies commands and address signals supplied from the outside via the data input / output buffer 17 and the command input / output buffer 18 to the control circuit 5.

  The control circuit 5 generally controls the operation of the flash memory 1 according to a command supplied from the outside. In response to the input / output command, the control circuit 5 controls reading / writing of the buffer RAM 3. In response to the access command, the control circuit 5 controls program, erase, and read operation procedures for the memory cell 15 of the flash memory block 2 in accordance with the command. The access command is accompanied by an input / output command. For example, in writing data to the flash memory block 2, an input / output command for storing the write data in the buffer RAM 3 is preceded, and thereafter, an access command for erasing and programming the flash memory block 2 using the write data in the buffer RAM 3 is provided. Accompanying. Access commands are broadly divided into commands for performing information storage and reading with two values, and commands for performing information storage and reading with four values. Even if an access command and an input / output command for reading information stored in binary are designated, or an access command and an input / output command for reading information stored in 4-value are designated, the control circuit 5 The buffer RAM 3 is controlled to perform DDR operation so that data is output from the data input / output buffer 17 at the same output rate, and the data path selection circuit 19 is controlled to perform speed conversion operation. Details of this control content will be described later.

  FIG. 3 exemplifies stored information by four values and its threshold voltage distribution. The storage information in four values is “11” data, “01” data, “00” data, and “10” data. “11” data is obtained by erasing. “01” data, “00” data, and “10” data are obtained by a program. The threshold voltage of the memory cell differs depending on the stored information “10”, “00”, “01”. The difference is controlled by changing the application time or application level of the high voltage pulse in the program for each data value. In the read operation, the word line selection levels as read word line voltages for identifying “11” data, “01” data, “00” data, and “10” data are made different between VRW1, VRW2, and VRW3. In binary information storage, “1” data is stored by erasing, and “0” data is stored by a program of “01” data. Since the threshold voltage distribution of the “11” data and the threshold voltage distribution of the “01” data are separated from each other, the reliability of information storage is higher in binary storage than in 4-level storage.

  FIG. 4 illustrates a data path when data is written with four values. Although not particularly limited, write data to the memory array 10 is in units of 2K bytes. In terms of the configuration for performing quaternary storage, the number of writing units of the nonvolatile memory cell is 8K. 8K sense latches 11 are arranged. The buffer RAM 3 has an upper buffer area (UBM) 3U for storing 2K bytes of data divided into upper 4 bits and lower 4 bits and storing 1K bytes each, and a lower buffer area (LBM) 3L. Write data supplied from the outside is supplied in units of 8 bits, the upper 4 bits are stored in the upper buffer area 3U, and the lower 4 bits are stored in the lower buffer area 3L. The write data is stored in the buffer memory according to the write address. First, “00” or “01” data is programmed to 8K nonvolatile memory cells to be programmed in accordance with the write data in the upper buffer area (UBM) 3U. Next, according to the write data in the lower buffer area (LBM) 3L, the 8K nonvolatile memory cells to be programmed are selectively programmed with “10” data.

  FIG. 5 shows a read operation flow of data (four-value data) stored in the nonvolatile memory in four values. This read flow corresponds to the program method of FIG. 4 divided into upper bits and lower bits. First, a read operation is performed with the word line selection level set to VRW2 (S1). If the selected memory cell is on, the upper bit of the quaternary data is “0”, and if it is off, the upper bit of the quaternary data is “1”. As a result, the upper bit can be determined. The upper bit data latched in the sense latch 11 is stored in the upper bit storage area of the buffer RAM 3 (S2). Next, a read / write operation is performed with the word line selection level set to VRW1 (S3), and read data is latched in the sense latch 11 (S4). Further, the read / write operation is performed with the word line selection level set to VRW3 (S5), and the low-order bit is determined by calculating the read data read this time and the read data previously latched in the latch 11 in the sense latch (S6). . The determined lower bit data is stored in the lower bit storage area of the buffer RAM 3 from the sense latch 11 (S7). The read data stored in the buffer RAM 11 is output to the outside in units of 8 bits.

  FIG. 6 shows a read operation flow of data (binary data) stored in binary in the nonvolatile memory. A read operation is performed with the word line selection level set to VRW2 (S11). If the selected memory cell is on, the upper bit of the quaternary data is “0”, and if it is off, the upper bit of the quaternary data is “1”. As a result, binary data can be determined. The data latched in the sense latch 11 is stored in the upper bit storage area (UBM) 3U of the buffer RAM 3 (S12). The read data stored in the buffer RAM 11 is output to the outside (S13). In reading binary data, the read data is stored only in the upper area 3U of the buffer RAM. When reading binary data in the same way as reading quaternary data, the output of the lower 4 bits of the 8-bit parallel output (× 8) of the data input / output buffer 17 becomes invalid. For example, as shown in the timing chart of FIG. 7, in the output operation of quaternary data, the upper and lower portions of the data input / output buffer 17 are both valid, but in FIG. 8, the output of the lower 4 bits is invalid. In this state, the binary data read operation halves the data output rate compared to the quaternary data read operation.

<< Improvement of binary data read by speed conversion control >>
A configuration for equalizing the data output rates of the binary data read operation and the quaternary data read operation will be described below.

  FIG. 1 illustrates a binary data read path. In the binary data read operation, the control circuit 5 causes the buffer RAM 3 to perform a DDR operation to double the output operation. The data path selection circuit (DPS) 19 performs conversion for doubling the parallel number by halving the speed of the output data from the upper bit storage area (UBM) 3U of the buffer RAM 3 in the binary data read operation. Provide a circuit. The conversion circuit includes latch circuits (LT1 to LT3) 21 to 23 and a selector (SEL) 24. Data is output from the upper storage area (UBM) 3U in parallel with 4 bits in synchronization with both rising and falling edges of the clock CLK. The latch circuit 21 latches the output data by a pulse change of the control signal φ1 synchronized with the rising edge of the clock CLK. The latch circuit 22 latches the output data by a pulse change of the control signal φ2 synchronized with the falling edge of the clock CLK. The latch circuit 23 latches the latch data of both the latch circuits 21 and 22 by the pulse change of the control signal φ3 synchronized with the rising edge of the clock CLK. The selector 24 selects the output of the latch circuit 23 by the control signal φ4 in the binary data read operation. As a result, the x8 parallel output of the data input / output buffer 17 is all valid in the binary data read operation as shown in FIG. 10, and the same data output rate as that of the quaternary data read operation in FIG. 9 is obtained. Can do. In the four-value data read operation, the selector 24 selects the input to be connected to the data output terminal of the buffer memory 3. The control signals φ1 to φ4 are output from the control circuit 5.

  Although not shown in particular, a conversion circuit having a data transfer direction opposite to that of the read path of FIG. 1 is provided as a binary data write path. That is, in the binary data write operation, the write data is supplied in × 8 bits, and this is guided to the binary data write path by a selector (not shown). In the binary data write path, x8-bit write data is latched in the first latch circuit in synchronization with the cycle of the clock CLK, and the upper 4 bits of the latch data by the first latch circuit are used at the rising edge of the clock CLK. The latches are latched in the second latch circuit in synchronism, and the lower 4 bits of the latch data of the first latch circuit are latched in the third latch circuit in synchronism with the rising edge of the clock CLK. The x4 output of the second latch circuit, the x4 output of the third latch circuit, and the upper 4 bits of the data input / output terminal of the buffer memory 11 are connected via the transfer gate. In writing binary data, the input operation of the buffer memory 11 is performed as a DDR operation. As a result, even when binary data is written, the write data can be supplied to the flash memory 1 in × 8 bits as in the case of writing quaternary data.

  FIG. 11 shows a layout configuration of a flash memory including four memory banks (BNK) that can operate independently from each other. The outputs of the four selectors 24 are connected to the data input / output buffer 4 via the common IO bus 30. In the input / output operation, one of the four selectors 24 is selected and operated, and the output of the other selectors is set to a high impedance state. Each memory bank (BNK) 31 to 34 includes a flash memory block (FLASH) 2, a buffer RAM (BMRY) 3 as a volatile memory block, an input / output circuit (I / O) 4, and a bank control circuit (CONTS) 34. It is comprised so that it can operate | move independently. As is clear from FIG. 11, in order to output read data to the outside at the same output rate as that in the case of reading quaternary data in the read operation of binary data, a large scale is required along the large scale flash memory array 10. There is no need to add a circuit like an aligner. It is only necessary to provide some latch circuits 21 to 24 and their control lines. With respect to the control, the buffer memory 3 may be DDR-operated in synchronization with the binary data reading to control several latch circuits 21 to 24 and the selector 24. No complicated control is required.

<Improvement of binary data read by multi-bank operation>
FIG. 12 shows a configuration for equalizing the data output rates of the binary data read operation and the quaternary data read operation by multi-bank control.

  In FIG. 12, the flash memory 1A has four memory banks BNK0 to BNK3. Each of the memory banks BNK0 to BNK3 has the same basic configuration as that of FIG. 1, but an input / output circuit (I / O) 30 is provided to represent each of the memory banks BNK0 to BNK3. In addition, a main control circuit (CONTM) 31 for controlling the memory banks BNK0 to BNK3 as a whole is provided. Each of the memory banks BNK0 to BNK3 includes a flash memory block (FLASH) 32 as a nonvolatile memory block, a buffer RAM (BMRY) 33 as a volatile memory block, and a bank control circuit (CONTS) 34. The flash memory block 32 has basically the same configuration as that described in FIG. In the figure, a memory array (MARY) 35 and a sense latch (SL) 36 are representatively shown. In particular, here, the memory array is divided into four pages PG0 to PG3, and any one page is selected at the time of access to be erased, programmed or read. In each page of PG0 to PG3, the selection unit of the nonvolatile memory cell by the word line is 8K as in the case of FIG. As in the above, 8K sense latches 36 are arranged. Similarly, the buffer RAM 33 has an upper buffer area (UBM) 33U and a lower buffer area (UBM) 33L for storing 2K bytes of data divided into upper 4 bits and lower 4 bits and storing 1K bytes each.

  The main control circuit 31 inputs a command supplied from the input / output circuit 30. The main control circuit 31 outputs bank control signals BACK0 to BACK3 to the bank control circuits 34 of the corresponding memory banks BNK0 to BNK3 according to the designation by the command. The bank control circuit 34 controls input / output of the buffer RAM 33 of the corresponding memory bank in accordance with a bank control signal corresponding to the input command. The bank control circuit 34 controls the erase, program or read operation for the flash memory block 32 of the corresponding memory bank in accordance with a bank control signal corresponding to the access command. Here, the buffer RAM 33 does not need to have a function of DDR operation.

  The input / output circuit 30 includes a data input / output buffer (DATB) 40, a command input / output buffer (CMDB) 41, and selectors (SEL) 42 and 43. The data input / output buffer (DATB) 40 performs input / output in 8-bit parallel (× 8). HBUS is an upper 4-bit bus, and LBUS is a lower 4-bit bus. The selector 42 selectively connects the upper buffer area UBM or the lower buffer area LBM of the memory bank BNK1 to the lower 4-bit bus LBUS according to the control signal φ5. The selector 43 selectively connects the upper buffer area UBM or the lower buffer area LBM of the memory bank BNK3 to the lower 4-bit bus LBUS according to the control signal φ5.

  As described with reference to FIG. 5, 4-bit data is read out from the data input / output buffer 40 in parallel by 8 bits. When the main control circuit 31 receives the access command TVCOM instructing to read binary data, when the bank address designated by the access command designates the bank BNK0, the operation of the memory bank BNK0 and the memory bank BNK1 is controlled by the control signals BACK0, By instructing with BACK1, the memory banks BNK0 and BNK1 are operated in parallel. As a result, 1 Kbyte of data is stored from the flash memory block 32 into the upper buffer area UBM of the buffer RAM 33. This operation is the same as that of the flash memory described in FIG. The difference is that 1 Kbytes of data is stored in the upper buffer area UBM of each of the two memory banks BNK0 and BNK1. At this time, the main control circuit 31 causes the selector 42 to select an input from the upper buffer area UBM in a process in response to an input / output command accompanying the binary data read access command. As a result, binary data is output in parallel from the data input / output buffer 40 in response to the input / output command. When the bank address designated by the access command designates the bank BNK1, the operation of the memory bank BNK2 and the memory bank BNK3 is instructed by the control signals BACK2 and BACK3, so that the memory banks BNK2 and BNK3 are operated in parallel. Thereby, 1 Kbyte of data is stored in the upper buffer area UBM of each of the two memory banks BNK2 and BNK3. At this time, the main control circuit 31 causes the selector 43 to select the input from the upper buffer area UBM in the process of responding to the input / output command accompanying the binary data read access command. As a result, binary data is output in parallel from the data input / output buffer 40 in response to the input / output command. Therefore, the output rate of binary data can be made the same as the output rate of quaternary data. The binary data read access command specifying the bank addresses of the memory banks BNK2 and BNK3 is invalidated.

  The binary data may be written in the same manner using the binary data read path.

  FIG. 13 shows a flowchart of the read operation. In the read operation, in the binary data read mode, only the selection operation based on the word line selection level VRW2 is performed. Since binary data reading is actually performed in parallel in two memory banks, finally, up to 2 Kbytes of data can be output at the same transfer rate as in the case of reading quaternary data.

  FIG. 14 shows a flowchart of the write operation. In the program mode of binary data in the write operation, only the “01” data of the first distribution is selected. Since the binary data program operation is actually performed in parallel in two memory banks, the binary data can be finally written in the two memory banks.

  FIG. 15 shows the layout configuration of the flash memory. As can be seen from FIG. 15, in order to output read data to the outside at the same output rate as in the case of reading quaternary data in the read operation of binary data, a large scale is required along the large scale flash memory array 10. There is no need to add a circuit like an aligner. It is only necessary to add a little control logic for reading and writing binary data to the selectors 42 and 43 and the control circuit 31 from the buffer RAM 33 to the lower-side common bus LBUS. As for the control contents, only selector selection control and memory bank operation designation are added, and no complicated control is required.

  FIG. 16 illustrates a flash memory 1B in which the arrangement of the selector is changed with respect to the configuration of FIG. The selectors 50 and 51 are arranged between the sense latch 36 and the buffer RAM 33. The selector 50 selectively connects the sense latch 36 of the memory bank BNK0 or the sense latch 36 of the memory bank BNK1 to the buffer RAM 33 of the memory bank BNK0. The selector 51 selectively connects the sense latch 36 of the memory bank BNK2 or the sense latch 36 of the memory bank BNK3 to the buffer RAM 33 of the memory bank BNK2. Connection control is performed by a control signal φ6.

  When the main control circuit 31A receives the access command TVCOM instructing reading of binary data, the operation of the memory bank BNK0 and the memory bank BNK1 is controlled by the control signal BACK0, when the bank address designated by the access command designates the bank BNK0. By instructing with BACK1, the memory banks BNK0 and BNK1 are operated in parallel. As a result, read data is stored in the sense latches of both memory banks BNK0 and BNK1. At this time, in the process of responding to the input / output command accompanying the binary data read access command, first, the main control circuit 31A causes the selector 50 to select the output of the sense latch of the memory bank BNK0 and the memory bank BNK0. Connected to the input of the buffer RAM 33. Then, the data of the sense latch 36 of the memory bank BNK0 is stored in the upper buffer area UBM of the memory bank BNK0. Next, the main control circuit 31A causes the selector 50 to select the output of the sense latch 36 of the memory bank BNK1, and connects it to the input of the buffer RAM 33 of the memory bank BNK0. Then, the data of the sense latch 36 of the memory bank BNK1 is stored in the lower buffer area LBM of the memory bank BNK0. As a result, binary data is output in parallel from the data input / output buffer 40 in response to the input / output command. On the other hand, when the bank address designated by the access command designates the bank BNK1, the main control circuit 31A instructs the operation of the memory bank BNK2 and the memory bank BNK3 with the control signals BACK2 and BACK3, whereby the memory banks BNK2 and BNK3 are designated. Operate in parallel. As a result, 1 Kbyte of data is stored in the sense latch 36 of each of the two memory banks BNK2 and BNK3. In the process of responding to the input / output command associated with this binary data read access command, the main control circuit 31A causes the selector 51 to select the output of the sense latch 36 of the memory bank BNK3 and input it to the buffer RAM 33 of the memory bank BNK2. Connecting. Then, the data of the sense latch 36 of the memory bank BNK3 is stored in the lower buffer area LBM of the memory bank BNK2. As a result, binary data is output in parallel from the data input / output buffer 40 in response to the input / output command. Therefore, the output rate of binary data can be made the same as the output rate of quaternary data. The binary data read access command specifying the bank addresses of the memory banks BNK2 and BNK3 is invalidated.

  FIG. 17 shows a flowchart of the read operation in the configuration of FIG. In the read operation, in the binary data read mode, only the selection operation based on the word line selection level VRW2 is performed. Since binary data reading is actually performed in parallel in two memory banks, finally, up to 2 Kbytes of data can be output at the same transfer rate as in the case of reading quaternary data. However, in order to transfer the latch data latched in parallel in the sense latches 36 of the two memory banks to the buffer RAM 33 of one memory bank, the transfer operation must be performed in series. In this respect, the latency for reading binary data is larger than in the case of FIG.

  FIG. 18 shows a flowchart of the write operation in the configuration of FIG. In the program mode of binary data in the write operation, only the “01” data of the first distribution is selected. However, in order to supply write data from one buffer RAM 33 to the sense latch 36 of a different memory bank, the transfer operation must be performed in series. After the write data is transferred to both memory banks, the program operation is performed in parallel in the two memory banks, and finally binary data can be written to the two memory banks.

  FIG. 19 shows a layout configuration of the flash memory 1B. As is clear from FIG. 15, the logical scale of the selectors 50 and 51 is determined by the interface scale between the sense latch 36 and the buffer RAM 33. If the scale of the interface is 1 Kbyte, the scales of the selectors 50 and 51 are larger than in the case of FIG. Also, in the control logic by the control circuit 31A, the states of the selectors 50 and 51 must be switched during the process of responding to the input / output command. In the case of FIG. 15, it is not necessary to switch during the operation. Accordingly, the configuration of FIG. 19 has a larger logical scale and more complicated control content than the configuration of FIG.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

  For example, the nonvolatile memory cell is not limited to a stack gate structure, and a split gate structure memory transistor in which a selection transistor portion and a memory transistor portion are separated can be employed. The program of the memory cell is not limited to electron injection by hot electrons, but may be a form in which electrons are injected from the substrate side through a tunnel oxide film. The initialization for the memory cell is not limited to the FN tunnel, and may be performed by hot hole injection from the substrate side. Further, the nonvolatile memory block is not limited to the flash memory, and may be another nonvolatile memory such as an EEPROM. Multi-value storage is not limited to four values, and may be eight-value storage. The nonvolatile semiconductor memory can be widely applied to semiconductor integrated circuits in which other logic functions are on-chip together.

It is a block diagram which illustrates the read-out route of binary data by speed conversion control. 1 is a block diagram generally illustrating a flash memory. It is explanatory drawing which illustrates the memory | storage information by 4 values, and its threshold voltage distribution. It is a block diagram which illustrates a data path when writing quaternary data. It is a flowchart which illustrates the read-out operation flow of quaternary data. It is a flowchart which illustrates the read-out operation | movement flow of binary data. 4 is a timing chart showing a state in which both upper and lower data input / output buffers are valid in the output operation of quaternary data. 6 is a timing chart showing how the output of lower 4 bits is invalidated in a binary data read operation. It is a timing chart showing a control form of the data path selection circuit in the read operation of quaternary data. It is a timing chart which shows the control form of the data path selection circuit in the read-out operation | movement of binary data. It is explanatory drawing which shows the outline of the layout structure of the flash memory provided with four memory banks which can mutually operate | move independently. FIG. 3 is a block diagram of a flash memory adopting a configuration for equalizing data output rates of binary data read operation and quaternary data read operation by multi-bank control. 13 is a flowchart of a read operation in the flash memory of FIG. 13 is a flowchart of a write operation in the flash memory of FIG. FIG. 13 is an explanatory diagram schematically showing a layout configuration of the flash memory of FIG. 12. FIG. 13 is a block diagram of another flash memory in which the arrangement of selectors is changed with respect to the configuration of FIG. FIG. 16 is a flowchart of a read operation in the flash memory of FIG. 15. FIG. 16 is a flowchart of a write operation in the flash memory of FIG. FIG. 16 is an explanatory diagram schematically showing a layout configuration of the flash memory of FIG. 15.

Explanation of symbols

1, 1A, 1B Flash memory 2 Flash memory block 3 Buffer RAM
UBM Upper buffer area LBM Lower buffer area 4 Input / output circuit 5 Control circuit 10 Memory array 11 Sense latch 15 Non-volatile memory cell 17 Data output buffer 18 Command input / output buffer 19 Data path selection circuit 21-23 Latch circuit 24 Selector 31-34 Memory bank BNK0 to BNK3 Memory bank 30 Input / output circuit 31, 31A Main control circuit 32 Flash memory block 33 Buffer RAM
34 Bank control circuit 35 Memory array 36 Sense latch 40 Data input / output buffer 41 Command input / output buffer 42, 43 Selector φ5 control signal 50, 51 Selector φ6 control signal

Claims (8)

A non-volatile memory block, a volatile memory block, an input / output circuit, and a control circuit;
The nonvolatile memory block includes a plurality of nonvolatile memory cells capable of storing information in binary and multi-values,
The volatile memory block is connected to the non-volatile memory block, and has a plurality of volatile memory cells for storing information in a binary manner so as to be rewritable.
The input / output circuit is connected to the volatile memory block and inputs / outputs information to / from the outside.
The control circuit reads out the output operation speed of the volatile memory block from the nonvolatile memory cell storing multi-value information when outputting the information read from the nonvolatile memory cell storing binary information to the outside. A nonvolatile semiconductor memory that performs control so that information is output faster than when information is output to the outside, and performs external output of information stored in binary and external output of information stored in four values at the same output rate. The non-volatile memory block reads information in units of the prescribed number of bits using an access unit of a prescribed number of nonvolatile memory cells,
The volatile memory block has a plurality of buffer areas for storing information read from the nonvolatile memory cells of the number of access units storing information in multiple values in units of the prescribed number of bits,
When the storage information in the nonvolatile memory cell is read as multi-value information storage, the control circuit takes out the outputs of the plurality of buffer areas in parallel and outputs them in parallel to the outside from the input / output circuit. When reading stored information as binary stored information, the output of one buffer area is taken out at a speed that is several times the parallel number of the parallel output, and the extracted information is taken at the same parallel bit number and speed as the parallel output. 2. The non-volatile semiconductor memory according to claim 1, wherein the non-volatile semiconductor memory outputs externally in parallel from the input / output circuit. The nonvolatile memory cell performs quaternary information storage as multiple values,
The non-volatile memory block reads information in units of the prescribed number of bits using an access unit of a prescribed number of nonvolatile memory cells,
The volatile memory block has a buffer area for storing information read from the nonvolatile memory cells of the number of access units storing information in four values in units of the prescribed number of bits,
The volatile memory block has a single data rate output operation in which the output operation is performed in synchronization with one of the rising and falling edges of the clock, and a double operation in which the output operation is performed in synchronization with both the rising and falling edges of the clock. The data rate output operation can be selected,
The input / output circuit outputs a first output path for outputting the outputs of the plurality of buffer areas in parallel, and a second output path for dropping the output of one buffer area to the transfer rate of the first output path. An output path,
The control circuit instructs the volatile memory block to perform a double data rate output operation when reading information stored in binary in the nonvolatile memory cell, and selects a second output path for the input / output circuit. And reading out the information stored in the nonvolatile memory cell in four values, the volatile memory block is instructed to perform a single data rate output operation, and the input / output circuit is selected for the first output path. 2. The nonvolatile semiconductor memory according to claim 1, wherein the nonvolatile semiconductor memory is designated. An input / output circuit, a plurality of memory banks connected to the input / output circuit, and a control circuit;
The input / output circuit inputs / outputs information to / from the outside,
The memory bank has a volatile memory block and a nonvolatile memory block;
The volatile memory block is connected to the input / output circuit, and has a plurality of volatile memory cells for storing information in a rewritable binary manner,
The non-volatile memory block is connected to the volatile memory block of a corresponding memory bank, and has a plurality of non-volatile memory cells capable of storing information in binary and multi-values,
When the control circuit reads out the information stored in binary in the nonvolatile memory cell, the control circuit stores the storage information of the nonvolatile memory cell storing the multi-value information from the nonvolatile memory block of one selected memory bank. A plurality of nonvolatile memory blocks are selected so as to have the same number of read information bits as when reading, and the stored information is read from the nonvolatile memory cells of each nonvolatile memory block, and the read information is input / output circuit Non-volatile semiconductor memory that outputs data externally in parallel.   When the control circuit reads information stored in binary in the nonvolatile memory cell, the control circuit reads the stored information read from each of the selected nonvolatile memory blocks into the volatile memory block of the corresponding memory bank. 5. The nonvolatile semiconductor memory according to claim 4, wherein the non-volatile semiconductor memory is stored and output from each volatile memory block is combined by the input / output circuit and output to the outside in parallel.   6. The nonvolatile semiconductor memory according to claim 5, wherein the input / output circuit includes a selector for combining information output from a plurality of volatile memory blocks.   When the control circuit reads the information stored in binary in the nonvolatile memory cell, the control circuit combines the stored information read from each of the selected nonvolatile memory blocks to correspond to one memory. 5. The nonvolatile semiconductor memory according to claim 4, wherein the volatile memory blocks of the bank are collectively stored and the stored information is output from the input / output circuit to the outside.   The nonvolatile semiconductor memory according to claim 7, further comprising a selector for coupling storage information read from a plurality of nonvolatile memory blocks between the nonvolatile memory block and the volatile memory block.

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