JP2006329778A - Capacitance detection circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a capacitance detection circuit capable of preventing a decrease in reliability due to fluctuations in electrostatic force applied to a capacitive element.
A capacitance detection circuit is a capacitance detection circuit for detecting a capacitance difference between capacitive elements, and switches between one end connected to Vdd, Vdd / 2, or a floating state. A switch S1, a switch S2 that switches between one end connected to the Vdd / 2, a ground voltage, or a floating state, and a capacitive element that has one end connected to the other end of the switch S1 Ca, one end connected to the other end of the switch S2, the other end connected to the other end of the capacitive element Ca, one end connected to the Vdd / 2, and the other end connected to the capacitive element Ca and a switch S3 connected to the connection point of the capacitive element Cb.
[Selection] Figure 1

Description

  The present invention relates to a capacitance detection circuit, and more particularly to a capacitance detection circuit used for measuring pressure, acceleration, angular velocity, and the like.

  In the field of inertial force sensors that detect accelerations on moving objects and angular velocities of moving objects, in recent years, especially by applying semiconductor micromachining technology, acceleration can be detected by detecting changes in the capacitance of capacitive elements. Capacitive sensors such as an acceleration sensor for detecting and an angular velocity sensor for detecting an angular velocity have attracted attention.

  For example, Patent Document 1 discloses the following capacitance detection circuit. That is, the silicon mass body is supported by the anchor portion via the beam. In addition, two fixed electrodes are formed on glass or silicon above and below the silicon mass body, and the two capacitive elements C1 and C2 are formed by the silicon mass body and the two fixed electrodes. These two capacitive elements C1 and C2 constitute a sensor element.

  And in the capacity | capacitance detection circuit of patent document 1, if the inertial force by acceleration acts on a certain direction of a silicon mass body, a silicon mass body will be displaced in that direction. Due to this displacement, the capacitance value between the silicon mass and the two fixed electrodes increases on the one hand and decreases on the other hand. This change in capacitance value is converted into a voltage.

  More specifically, the capacitance detection circuit described in Patent Document 1 is a switched capacitor type, and is used for feedback between two capacitance elements C1 and C2 whose values vary at least, and between the output terminal and the inverting input terminal. An operational amplifier to which the sampling capacitive element C3 is connected, and a hold capacitive element C4 connected between the non-inverting input terminal of the operational amplifier and the reference voltage source are provided. One end of each of the capacitive elements C1, C2, and C3 is connected to the inverting input terminal of the operational amplifier. At the timing φ1 of the switching cycle, the other ends of the capacitive elements C1 and C2 are connected to the power supply and the ground, or two positive and negative power supplies, respectively, and the capacitive element C3 is short-circuited. At timing φ2, the other ends of the capacitive elements C1 and C2 and the output terminal of the operational amplifier are respectively connected to the non-inverting input terminal of the operational amplifier. With such a configuration, an analog voltage representing the capacitance difference between the two capacitive elements C1 and C2 can be obtained.

  In recent years, there has been an increasing demand for digital output of sensors. As a configuration for obtaining the output of the sensor with a digital value instead of an analog voltage, a configuration in which an analog / digital conversion circuit (AD conversion circuit) is arranged after the capacitance detection circuit described in Patent Document 1, that is, after the operational amplifier, is common. is there. However, the capacitance detection circuit described in Patent Document 1 has a problem in that power consumption increases because an operational amplifier, which is an analog circuit that consumes a large amount of power, is generally used.

In order to solve such a problem, for example, Non-Patent Document 1 discloses the following capacitance detection circuit. That is, the non-inverting input terminal of the comparator is connected to the ground voltage, the analog output of the capacitance detection circuit is connected to the inverting input terminal of the comparator, and the output of the comparator is connected to a SAR (Successive Approximation Register). The digital output of the SAR is converted into an analog voltage by a digital / analog conversion circuit (DA conversion circuit), and the analog voltage is output to the inverting input terminal of the comparator via a capacitive element. The control circuit changes the digital output of the SAR and sets the voltage at the inverting input terminal of the comparator as the ground voltage. The digital output of the SAR at this time is a digital value representing the capacitance difference between the two capacitance elements in the capacitance detection circuit. With such a configuration, the output of the sensor can be obtained as a digital value, and an increase in power consumption due to the use of an operational amplifier can be prevented.
JP 2003-67270 A JTKUNG et al., `` A Digital Readout Technique for Capacitive Sensor Applications '', IEEE Journal of Solid-State Circuits, VOL.23, NO.4, AUGUST 1988

  Incidentally, the direction of the electrostatic force is determined by the direction of the electric field generated by the applied voltage, and the magnitude of the electrostatic force is proportional to the square of the applied voltage. Therefore, when the magnitude and direction of the electrostatic force applied to the two capacitance elements in the capacitance detection circuit vary greatly, the movable electrode varies greatly and the reliability of the capacitive sensor decreases. For example, the movable electrode is attracted to the fixed electrode and the capacitive sensor becomes inoperable, which is a serious problem in terms of reliability of the capacitive sensor. In the capacitance detection circuit of a capacitive sensor that applies semiconductor micromachining technology, the fluctuation of the electrostatic force between the two capacitive elements is a major problem, especially because the movable electrodes are arranged at a minute interval with respect to the fixed electrode. Become.

  Here, in the capacitance detection circuit described in Non-Patent Document 1, the output of the DA converter circuit, that is, the voltage at the connection point of the capacitive elements C1 and C2, varies between the ground voltage and the power supply voltage. The voltages at the other ends of the capacitive elements C1 and C2 are switched between the power supply voltage and the ground voltage at a predetermined timing. Therefore, the capacitance detection circuit described in Non-Patent Document 1 has a problem that the magnitude and direction of the electrostatic force applied to the capacitive elements C1 and C2 vary greatly, and the reliability of the capacitive sensor decreases.

  Therefore, an object of the present invention is to provide a capacitance detection circuit capable of preventing a decrease in reliability due to a variation in electrostatic force applied to a capacitive element.

  In order to solve the above problem, a capacitance detection circuit according to an aspect of the present invention is a capacitance detection circuit that detects a capacitance difference between capacitance elements, and one end of the capacitance detection circuit is connected to a first voltage, A first switch for switching between being connected to a second voltage lower than the voltage or being in a floating state; and one end connected to the second voltage or a third voltage lower than the second voltage A second switch for switching between connection and floating, a first capacitor element having one end connected to the other end of the first switch, and one end connected to the other end of the second switch A second capacitive element having the other end connected to the other end of the first capacitive element, a first end connected to the second voltage, and a second end connected to the first capacitive element and the second capacitive element. And a third switch connected to the point.

  Preferably, the capacitance detection circuit further includes a first input terminal and a second input terminal, wherein the first input terminal is connected to a connection point of the first capacitance element and the second capacitance element, A comparator that compares the voltage at the input terminal and the voltage at the second input terminal and outputs a voltage representing the comparison result.

  More preferably, the capacitance detection circuit further outputs to the second input terminal of the comparator a register circuit that outputs a plurality of bits of data and a voltage corresponding to the logic level of each bit of the data received from the register circuit And a DA converter circuit, and the register circuit determines a logic level of each bit of data based on the output voltage of the comparator.

  More preferably, the comparator has a predetermined voltage connected to the second input terminal, and the capacitance detection circuit further includes a third capacitor element having one end connected to the first input terminal of the comparator, and a plurality of capacitors. A register circuit that outputs bit data, and a DA converter circuit that outputs a voltage corresponding to the logic level of each bit of data received from the register circuit to the other end of the third capacitor element. The logic level of each bit of data is determined based on the output voltage of the device.

  According to the present invention, it is possible to prevent a decrease in reliability due to a variation in electrostatic force applied to the capacitive element.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

<First Embodiment>
[Configuration and basic operation]
FIG. 1 is a functional block diagram showing the configuration of the capacitance detection circuit according to the first embodiment of the present invention. Referring to the figure, the capacitance detection circuit includes switches S1 to S3 (first to third switches), differential capacitance sensor unit 1, comparator 2, successive approximation register circuit 3, and DA. A conversion circuit 4 and a control circuit 10 are provided.

  The differential capacitive sensor unit 1 includes, for example, a capacitive element Ca (first capacitive element) and a capacitive element Cb (formed by a silicon mass body and two fixed electrodes, similarly to the capacitive detection circuit described in Patent Document 1. Second capacitor element).

  The switch S1 switches whether one end is connected to the first voltage Vdd, the second voltage Vdd / 2, or a floating state.

  The switch S2 switches whether one end is connected to the second voltage Vdd / 2, the third voltage (ground voltage), or the floating state.

  One end of the capacitive element Ca is connected to the other end of the switch S1. One end of the capacitive element Cb is connected to the other end of the switch S2, and the other end is connected to the other end of the capacitive element Ca.

  The switch S3 has one end connected to the second voltage Vdd / 2 and the other end connected to a connection point between the capacitive element Ca and the capacitive element Cb.

  Hereinafter, the connection point of the switch S3, the capacitive element Ca, and the capacitive element Cb is the node A2, the other end of the switch S1 and the capacitive element Ca is the node B2, and the other end of the switch S2 and the capacitive element Cb is the node C2. Called. The capacitance value of the capacitive element Ca is Ca, and the capacitance value of the capacitive element Cb is Cb.

  The comparator 2 has an inverting input terminal connected to the connection point between the capacitive element Ca and the capacitive element Cb, and a non-inverting input terminal connected to the output of the DA conversion circuit 4. The comparator 2 compares the voltage at the inverting input terminal and the voltage at the non-inverting input terminal, and outputs a voltage representing the comparison result.

  The successive approximation register circuit 3 includes a register that outputs a plurality of bits of data. Here, the successive approximation register circuit 3 determines the logical level of each bit of the register based on the output of the comparator 2 and outputs each bit of the register to the DA conversion circuit 4 as comparison result data.

  The DA conversion circuit 4 outputs a voltage corresponding to the logic level of each bit of the comparison result data received from the successive approximation register circuit 3 to the non-inverting input terminal of the comparator 2. Here, the resolution of the DA conversion circuit 4, that is, the number of input bits, is the same as the number of bits of comparison result data output from the successive approximation register circuit 3. Further, the bits from the MSB (Most Significant Bit) to LSB (Least Significant Bit) of the output of the successive approximation register circuit 14 are connected in correspondence with the bits from the MSB to LSB of the input of the DA conversion circuit 15, respectively. Yes.

  Here, the switches S1 to S3 are, for example, switches configured by N-type MOS transistors or P-type MOS transistors using CMOS (Complementary Metal Oxide Semiconductor) processes in an integrated circuit, or N-type transistors and P-type transistors. It is a complementary switch composed of both transistors. The capacitance detection circuit shown in FIG. 1 can be manufactured as an integrated circuit except for the differential capacitance sensor unit 1. Regarding the connection between the differential capacitance sensor unit 1 and each switch, the following three cases are conceivable.

  The first case is a one package type. That is, a differential capacitance type sensor is fabricated on a silicon substrate using semiconductor micromachining technology. The one obtained by cutting out the chip of the differential capacitance type sensor produced on this silicon substrate and the one obtained by cutting out the integrated circuit chip produced by integrating the interface circuit on the silicon substrate are sealed in one package. The differential capacitance type sensor chip and the interface integrated circuit chip are connected by wire bonding.

  The second case is a module type. That is, a differential capacitance type sensor fabricated on a silicon substrate using semiconductor micromachining technology is sealed in a package, and the interface integrated circuit chip is sealed in another package. These two packages are connected as a module on a printed circuit board or the like.

  The third case is a one-chip type. That is, a semiconductor chip manufactured as a single chip is sealed in a package by the same integration process in which a differential capacitance sensor and an interface integrated circuit are formed on the same chip on a silicon substrate using a semiconductor micromachining technique. Any of the above cases may be used.

  Also, a sampling operation for holding the output voltage of the differential capacitive sensor unit 1 for a certain period is performed between the node A2 which is a connection point of the capacitive element Ca and the capacitive element Cb, and the comparator 2 to obtain a differential capacitive type. A sample-and-hold circuit for preventing malfunction due to fluctuations in the output voltage of the sensor unit 1 can be provided. Further, an operational amplifier circuit for amplifying the sensor output can be arranged.

[Operation]
Next, an operation when the capacitance detection circuit according to the present embodiment detects a capacitance difference between two capacitance elements will be described.

  FIG. 2 is a time chart showing the state of each node in the capacitance detection circuit according to the present embodiment. FIG. 3 is a time chart showing the state of each switch in the capacitance detection circuit according to the present embodiment.

  First, as an initial state, the control circuit 10 turns off the switches S1 to S3, that is, puts the node A2, the node B2, and the node C2 into a floating state (FIG. 2 and FIG. 3A).

  Next, the control circuit 10 turns on the switch S3 to set the voltage at the node A2 to the second voltage Vdd / 2 (FIG. 2 and FIG. 3B).

  Next, the control circuit 10 connects one end of the switch S1 to the first voltage Vdd to set the voltage at the node B2 to the first voltage Vdd. Further, the control circuit 10 connects one end of the switch S2 to the third voltage (ground voltage), and sets the voltage at the node C2 to the third voltage (ground voltage) ((c) in FIGS. 2 and 3). ).

  Next, the control circuit 10 turns off the switch S3 to place the node A2 in a floating state ((d) in FIGS. 2 and 3).

  Here, assuming that the charge accumulated in the node A2, that is, the charge accumulated in the capacitive element Ca and the capacitive element Cb is QA2, QA2 is expressed by the following equation.

QA2 = Ca × (Vdd / 2−Vdd) + Cb × (Vdd / 2−0)
= (Cb-Ca) x Vdd / 2 (A1)
Next, the control circuit 10 turns off the switch S1 and the switch S2, and sets the node B2 and the node C2 in a floating state ((e) in FIGS. 2 and 3). This is because, for example, the switching of the switch S1 prevents the first voltage Vdd and the second voltage Vdd / 2 from being conducted to destroy the circuit. Therefore, when each switch has an ideal configuration that does not cause such a problem, the state shown in FIG. 2 and FIG. 3E becomes unnecessary.

  Then, the electric charge accumulated at node A2 is redistributed to capacitive element Ca and capacitive element Cb. Here, the voltage of the node A2 is VA2, and the charge stored in the node A2 in the states of FIG. 2 and FIG. 3D and the states of FIG. 2 and FIG. Since they are equal, the following equation holds.

(Cb−Ca) × Vdd / 2 =
Ca × (VA2−Vdd / 2) + Cb × (VA2−Vdd / 2) (A2)
From the formula (A2), VA2 is expressed by the following formula.

VA2 = 2 × Cb / (Ca + Cb) × Vdd / 2
= Vdd / 2 + (Vdd / 2) × (Cb−Ca) / (Ca + Cb) (A3)
From the equation (A3), the voltage VA2 at the node A2 after the state shown in FIG. 2 and FIG. 3F, that is, after the charge accumulated at the node A2 is redistributed to the capacitive element Ca and the capacitive element Cb, is obtained. It can be seen that the second voltage Vdd / 2 is added to the voltage proportional to the capacitance difference of the capacitor Cb. Therefore, the capacitance detection circuit according to the present embodiment can detect the capacitance difference between the two capacitance elements Ca and Cb and output a voltage representing the capacitance difference.

  Next, the electrostatic force applied to the capacitive element Ca and the capacitive element Cb constituting the differential capacitive sensor unit 1 of the capacitive detection circuit according to the present embodiment will be described.

  First, in the state of FIG. 2 and FIG. 3C, the voltage VA2 of the node A2 is Vdd / 2, and the voltage of the node B2 is Vdd, so that the node A2 applied to the capacitive element Ca is Assuming that the reference voltage, that is, the voltage based on the node A2 applied to the node B2, is VCa, VCa is expressed by the following equation.

VCa = −Vdd / 2 (A4)
Next, in the state of FIG. 2 and FIG. 3F, the voltage VA2 at the node A2 is expressed by the equation (A3), and the voltage at the node B2 is Vdd / 2. The voltage VCa based on the applied node A2 is expressed by the following equation.

VCa = Vdd / 2 + (Vdd / 2) × (Cb−Ca) / (Ca + Cb) −Vdd / 2 = (Vdd / 2) × (Cb−Ca) / (Ca + Cb) (A5)
Here, initial values of the capacitive element Ca and the capacitive element Cb before the silicon mass body is displaced by the inertial force are Ca0 and Cb0, respectively. Further, it is assumed that the capacitance values of the capacitive element Ca and the capacitive element Cb are equal, that is, Ca0 = Cb0.

  When the silicon mass body is displaced, the capacitance values of the capacitive element Ca and the capacitive element Cb change to Ca0 + ΔC and Cb0−ΔC, respectively. From Ca0 = Cb0, the variation value ΔC of the capacitive element is expressed by the following equation.

ΔC = | (Cb0−ΔC) − (Ca0 + ΔC) | / 2
= | Cb-Ca | / 2 (A6)
The initial value Ca0 of the capacitive element Ca is expressed by the following equation.

Ca0 = (Cb0 + Ca0) / 2 = | (Cb0−ΔC) + (Ca0 + ΔC) | / 2
= (Cb + Ca) / 2 (A7)
From formula (A6) and formula (A7),
| Cb-Ca | / (Ca + Cb) = (| Cb-Ca | / 2) / (Ca + Cb) / 2
= ΔC / Ca0 (A8)
It becomes.

Here, in the general differential capacitance type sensor, the maximum value of the variation value ΔC of the capacitive element is about 10% of the initial value Ca0 of the capacitive element. Is the maximum,
| Cb−Ca | / (Ca + Cb) = ΔC / Ca0≈0.1 (A9)
It becomes.

  Therefore, the voltage VCa with reference to the node A2 applied to the capacitive element Ca is expressed by the following expression when the variation value of the capacitive element is maximized.

VCa≈ ± 0.1 × (Vdd / 2) (A10)
From equation (A10), the voltage that determines the electrostatic force applied to the capacitive element Ca, that is, the voltage VCa based on the node A2 applied to the capacitive element Ca is in the state of FIG. 2 and FIG. −Vdd / 2, and in the state of FIG. 2 and FIG. 3F, even when the variation value of the capacitive element is maximum, it is very small ± 0.1 × compared to Vdd / 2. (Vdd / 2).

  Similarly, for capacitor Cb, in the state of FIG. 2 and FIG. 3C, voltage VA2 at node A2 is Vdd / 2, and voltage at node C2 is 0 V (ground voltage). Therefore, when a voltage based on the node A2 applied to the capacitor Cb, that is, a voltage based on the node A2 applied to the node C2, is VCb, VCb is expressed by the following expression.

VCb = Vdd / 2 (A11)
Next, in the state of FIG. 2 and FIG. 3F, the voltage VA2 at the node A2 is expressed by the equation (A3), and the voltage at the node C2 is Vdd / 2. The voltage VCb based on the applied node A2 is expressed by the following equation.

VCb = Vdd / 2 + (Vdd / 2) × (Cb−Ca) / (Ca + Cb) −Vdd / 2 = (Vdd / 2) × (Cb−Ca) / (Ca + Cb) (A12)
Therefore, similarly to the capacitive element Ca, the voltage VCb based on the node A2 applied to the capacitive element Cb is expressed by the following expression when the variation value of the capacitive element is maximized.

VCb≈ ± 0.1 × (Vdd / 2) (A13)
From the equation (A8), the voltage that determines the electrostatic force applied to the capacitive element Cb, that is, the voltage VCb based on the node A2 applied to the capacitive element Cb is as shown in FIG. 2 and FIG. Vdd / 2, and in the state of FIG. 2 and FIG. 3 (f), even when the variation value of the capacitive element is maximum, it is very small ± 0.1 × ( Vdd / 2).

  Next, an operation when the capacitance detection circuit according to the present embodiment outputs an analog voltage representing a capacitance difference between two capacitance elements as a digital value will be described. Hereinafter, the connection point between the output of the DA conversion circuit 4 and the non-inverting input terminal of the comparator 2 is referred to as a node AA2.

  FIG. 4 is a flowchart showing the successive approximation operation performed by the capacitance detection circuit according to the present embodiment.

  The successive approximation register circuit 3 is a voltage indicating a capacitance difference between the two capacitive elements Ca and Cb after each switch is controlled by the control circuit 10 to be in the state of FIG. 2 and FIG. Is obtained, the successive approximation operation is started (S1).

  First, the successive approximation register circuit 3 substitutes the input bit number n (n is a natural number of 2 or more), which is the resolution of the DA conversion circuit 4, for a variable k (S2).

  Next, the successive approximation register circuit 3 sets the k-th bit of the register included in the successive approximation register circuit 3 to 1 and outputs each bit of the register as comparison result data (S3). The successive approximation register circuit 3 clears each bit of the register included in the successive approximation register circuit 3 to 0 at the start of the successive approximation operation. Therefore, the comparison result data output from the successive approximation register circuit 3 at the start of the successive approximation operation is “100,000” in binary when k = 6, for example.

  The DA conversion circuit 4 outputs a voltage corresponding to the logic level of each bit of the comparison result data received from the successive approximation register circuit 3 to the non-inverting input terminal of the comparator 2.

  Comparator 2 compares voltage VA2 at node A2 representing the capacitance difference between capacitive element Ca and capacitive element Cb with the voltage at node AA2, that is, the voltage received from DA converter circuit 4, and compares the voltage VA2 at node A2. Is larger or the voltage at node AA2 is equal to voltage VA2 at node A2, the output voltage is the third voltage (ground voltage), and when the voltage at node AA2 is greater, the output voltage is the first voltage The voltage is Vdd.

  The successive approximation register circuit 3 receives the voltage representing the comparison result from the comparator 2 and determines that the k-th bit of the register is set to 1 when the voltage VA2 of the node A2 is larger (YES in S4). (S5).

  On the other hand, the successive approximation register circuit 3 receives the voltage representing the comparison result from the comparator 2, and if the voltage at the node AA2 is greater or the voltage at the node AA2 is equal to the voltage VA2 at the node A2 (S4). NO), it is determined to set the k-th bit of the register to 0 (S6).

  Next, the successive approximation register circuit 3 sets a value obtained by subtracting 1 from the variable k as a new k (S7). The successive approximation register circuit 3 ends the successive approximation operation when k is 0 (YES in S8). The comparison result data output from the successive approximation register circuit 3 to the digital output terminal t1 at the end of the successive approximation operation becomes a digital value representing the capacitance difference between the two capacitive elements Ca and Cb (S9).

  On the other hand, when k is larger than 0 (NO in S8), the successive approximation register circuit 3 sets the k-th bit of the register as 1, outputs each bit of the register as comparison result data, and sets the new k value. A successive approximation operation is performed (S3).

  By the way, in the capacitance detection circuit described in Non-Patent Document 1 and the capacitance detection circuit described in Patent Document 1, the magnitude and direction of the electrostatic force applied to the capacitive elements C1 and C2 greatly fluctuate, and the reliability of the sensor decreases. There was a problem.

  However, in the capacitance detection circuit according to the present embodiment, the control circuit 10 controls the switches S1 to S3, so that the voltage VCa that determines the electrostatic force applied to the capacitive element Ca and the capacitive element Cb are applied. The voltage VCb that determines the electrostatic force is −Vdd / 2 and Vdd / 2 in the state of FIG. 2 and FIG. 3C, and compared with Vdd / 2 in the state of FIG. 2 and FIG. And very small ± 0.1 × (Vdd / 2). That is, fluctuations in the voltage VCa that determines the electrostatic force applied to the capacitive element Ca and the voltage VCb that determines the electrostatic force applied to the capacitive element Cb are expressed by −Vdd / 2 to ± 0.1 × (Vdd / 2). And Vdd / 2 to ± 0.1 × (Vdd / 2). Therefore, in the capacitance detection circuit according to the present embodiment, fluctuations in the electrostatic force applied to the capacitive element Ca and the capacitive element Cb can be significantly suppressed, resulting from fluctuations in the electrostatic force applied to the capacitive element. Reliability degradation can be prevented.

  Furthermore, the capacitance detection circuit according to the present embodiment performs the successive approximation operation as described above using the comparator 2, the successive approximation register circuit 3, and the DA conversion circuit 4. Then, the comparison result data output from the successive approximation register circuit 3 to the digital output terminal t1 at the end of the successive approximation operation becomes a digital value representing the capacitance difference between the two capacitive elements Ca and Cb. Therefore, in the capacitance detection circuit according to the present embodiment, in order to compare the voltage representing the capacitance difference between the two capacitance elements Ca and Cb with a predetermined voltage, the capacitance detection circuit described in Patent Document 1 is added to the AD conversion circuit. Unlike the case of adding, an analog circuit that increases power consumption does not need to use an operational amplifier, and is realized by using only a comparator included in the AD conversion circuit, thereby preventing an increase in power consumption. In the capacitance detection circuit according to the present embodiment, the sensor output, that is, the capacitance difference between the two capacitance elements Ca and Cb can be obtained as a digital value.

  Next, another embodiment of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

<Second Embodiment>
First, for comparison, an example of a capacitance detection circuit in which the capacitance detection circuit described in Patent Document 1 and the capacitance detection circuit described in Non-Patent Document 1 are combined will be described.

  FIG. 5 is a functional block diagram showing a configuration of a capacitance detection circuit in which the capacitance detection circuit described in Patent Document 1 and the capacitance detection circuit described in Non-Patent Document 1 are combined. With reference to the figure, the capacitance detection circuit further includes a switch S3 and a capacitance element Cc with respect to the capacitance detection circuit according to the first embodiment. In addition, the capacitance detection circuit is configured not to include the switch S3 with respect to the capacitance detection circuit according to the first embodiment.

  The switch S1 switches whether one end is connected to the first voltage Vdd, the third voltage (ground voltage), or a floating state.

  The switch S2 switches whether one end is connected to the first voltage Vdd, the third voltage (ground voltage), or the floating state.

  One end of the capacitive element Ca is connected to the other end of the switch S1. One end of the capacitive element Cb is connected to the other end of the switch S2, and the other end is connected to the other end of the capacitive element Ca.

  Comparator 2 has an inverting input terminal connected to the connection point of capacitive element Ca and capacitive element Cb, and a non-inverting input terminal connected to a third voltage (ground voltage).

  One end of the capacitive element Cc is connected to the connection point between the capacitive element Ca and the capacitive element Cb, and the other end is connected to the output of the DA converter circuit 4.

  The DA conversion circuit 4 outputs a voltage corresponding to the logic level of each bit of the comparison result data received from the successive approximation register circuit 3 to the other end of the capacitive element Cc. The output voltage of the DA conversion circuit 4 is output to the inverting input terminal of the comparator 2 through the capacitive element Cc.

  Hereinafter, a connection point between the capacitive element Ca and the capacitive element Cb is referred to as a node A1, a connection point between the other end of the switch S1 and the capacitive element Ca is referred to as a node B1, and a connection point between the other end of the switch S2 and the capacitive element Cb is referred to as a node C1. The capacitance value of the capacitive element Cc is Cc. The output voltage of the DA converter circuit 4 is VDAC.

  Next, an operation when the capacitance detection circuit according to the present embodiment detects a capacitance difference between two capacitance elements will be described.

  First, the control circuit 10 turns on the switch S4 in order to set the initial voltage of the node A1 to the ground voltage. Then, the control circuit 10 connects one end of the switch S1 to the first voltage Vdd and sets the voltage at the node B1 to the first voltage Vdd. In addition, the control circuit 10 connects one end of the switch S2 to the third voltage (ground voltage) and sets the voltage at the node C1 to the third voltage (ground voltage). Then, the control circuit 10 turns off the switch S4 (hereinafter, this state is referred to as state 1). In state 1, assuming that the charge accumulated in the node A1, that is, the charge accumulated in the capacitive element Ca and the capacitive element Cb is QA1, QA1 is expressed by the following equation.

QA1 = Ca × (0−Vdd) + Cb × 0 = −Ca × Vdd (B1)
Next, the control circuit 10 connects one end of the switch S1 to the third voltage (ground voltage) and sets the voltage at the node B1 to the third voltage (ground voltage). Further, the control circuit 10 connects one end of the switch S2 to the first voltage Vdd, and sets the voltage at the node C1 to the first voltage Vdd (hereinafter, this state is referred to as state 2). When the state transitions to state 2, the successive approximation register circuit 3 starts the successive approximation operation described above. When the voltage at the node A1 is VA1, in the state 2, QA1 is expressed by the following equation.

QA1
= Ca * (VA1-0) + Cb * (VA1-Vdd) + Cc * (VA1-VDAC)
= (Ca + Cb + Cc) * VA1-Cb * Vdd-Cc * VDAC (B2)
According to the law of conservation of charge, since the charges accumulated in the node A1 in the state 1 and the state 2 are equal, the following expression is established.

-Ca x Vdd
= (Ca + Cb + Cc) * VA1-Cb * Vdd-Cc * VDAC (B3)
Therefore, VA1 is expressed by the following equation.

VA1
= ((Cb−Ca) × Vdd + Cc × VDAC) / (Ca + Cb + Cc) (B4)
Therefore, if a voltage based on the node A1 applied to the capacitive element Ca, that is, a voltage based on the node A1 applied to the node B1, is VCa, the VCa in the state 1 is expressed by the following expression.

VCa = −Vdd (B5)
Further, VCa in state 2 is expressed by the following equation.

VCa = VA1-0
= ((Cb−Ca) × Vdd + Cc × VDAC) / (Ca + Cb + Cc) (B6)
From the equation (B6), it can be seen that VCa changes according to the output voltage VDAC of the DA converter circuit 4. When the successive approximation operation ends, the inverting input terminal of the comparator 2, that is, the voltage VA1 of the node A1 becomes the ground voltage. Therefore, VCa at the end of the successive approximation operation is expressed by the following equation.

VCa = 0-0 = 0 (B7)
Therefore, it can be seen that the voltage VCa varies from −Vdd to a voltage value greater than 0V.

  When a voltage based on the node A1 applied to the capacitive element Cb, that is, a voltage based on the node A1 applied to the node C1, is VCb, VCb in the state 1 is expressed by the following expression.

VCb = 0 (B8)
Further, VCb in the state 2 is expressed by the following equation.

VCb = VA1-Vdd
= ((Cb-Ca) * Vdd + Cc * VDAC) / (Ca + Cb + Cc) -Vdd (B9)
Also, VCb at the end of the successive approximation operation is expressed by the following equation.

VCb = −Vdd (B10)
Therefore, it can be seen that voltage VCb varies from −Vdd to 0V.

[Configuration and basic operation]
Next, a capacitance detection circuit according to a second embodiment of the present invention will be described. FIG. 6 is a functional block diagram showing the configuration of the capacitance detection circuit according to the second embodiment of the present invention. With reference to the figure, the capacitance detection circuit further includes a capacitance element Cc with respect to the capacitance detection circuit according to the first embodiment.

  Comparator 2 has an inverting input terminal connected to a connection point between capacitive element Ca and capacitive element Cb, and a non-inverting input terminal connected to second voltage Vdd / 2.

  One end of the capacitive element Cc is connected to the connection point between the capacitive element Ca and the capacitive element Cb, and the other end is connected to the output of the DA converter circuit 4.

  The DA conversion circuit 4 outputs a voltage corresponding to the logic level of each bit of the comparison result data received from the successive approximation register circuit 3 to the other end of the capacitive element Cc. The output voltage of the DA conversion circuit 4 is output to the inverting input terminal of the comparator 2 through the capacitive element Cc.

  Next, an operation when the capacitance detection circuit according to the present embodiment detects a capacitance difference between two capacitance elements will be described.

  First, the state of each node and each switch in the capacitance detection circuit according to the present embodiment is shown in FIG. 2 and FIG. 3 as in the capacitance detection circuit according to the first embodiment. That is, the control of the switches S1 to S3 performed by the control circuit 10 in the capacitance detection circuit according to the present embodiment is the same as that of the capacitance detection circuit according to the first embodiment.

  Next, the electrostatic force applied to the capacitive element Ca and the capacitive element Cb constituting the differential capacitive sensor unit 1 of the capacitive detection circuit according to the present embodiment will be described. Hereinafter, the connection point of the switch S3, the capacitive element Ca, and the capacitive element Cb is the node A3, the other end of the switch S1 and the capacitive element Ca is the node B3, and the other end of the switch S2 and the connection point of the capacitive element Cb is the node C3. Called. The capacitance value of the capacitive element Ca is Ca, the capacitance value of the capacitive element Cb is Cb, and the capacitance value of the capacitive element Cc is Cc. The output voltage of the DA converter circuit 4 is VDAC.

  First, in the state of FIG. 2 and FIG. 3C, the voltage VA2 of the node A3 is Vdd / 2, and the voltage of the node B3 is Vdd, so that the node A3 applied to the capacitive element Ca is Assuming that the reference voltage, that is, the voltage based on the node A3 applied to the node B3, is VCa, VCa is expressed by the following equation.

VCa = −Vdd / 2 (C1)
From the equations (B5) and (C1), the VCa in the capacitance detection circuit according to the present embodiment is smaller than the VCa of the capacitance detection circuit shown in FIG.

  Here, assuming that the charge accumulated in the node A3, that is, the charge accumulated in the capacitive element Ca and the capacitive element Cb is QA3, QA3 is expressed by the following equation.

QA3 = Ca × (Vdd / 2−Vdd) + Cb × (Vdd / 2−0) = (Cb−Ca) × Vdd / 2 (C2)
Next, in the state of FIG. 2 and FIG. 3F, QA3 is expressed by the following equation.

QA3 = Ca * (VA3-Vdd / 2) + Cb * (VA3-Vdd / 2) + Cc * (VA3-VDAC)
= (Ca + Cb + Cc) * VA3- (Ca + Cb) * Vdd / 2-Cc * VDAC (C3)
According to the law of conservation of charge, since the charges accumulated in the node A3 in the state of FIGS. 2 and 3D and the state of FIG. 2 and FIG. 3F are equal, the following equation is established.
(Cb−Ca) × Vdd / 2 = (Ca + Cb + Cc) × VA3− (Ca + Cb) × Vdd / 2−Cc × VDAC (C4)
From the formula (C4), VA3 is represented by the following formula.

VA3 = (Cb × Vdd + Cc × VDAC) / (Ca + Cb + Cc) (C5)
Since the voltage at the other end node B3 of the capacitive element Ca is Vdd / 2, the voltage VCa based on the node A2 applied to the capacitive element Ca is expressed by the following equation.

VCa = ((Cb × Vdd + Cc × VDAC) / (Ca + Cb + Cc) −Vdd / 2 (C6)
Considering the case of Cc << Ca + Cb for simplification, the equation (C6) can be expressed as follows.

VCa = ((Cb × Vdd + Cc × VDAC) / (Ca + Cb) −Vdd / 2
= (Vdd / 2) × (Cb−Ca) / (Ca + Cb) + Cc × VDAC / (Ca + Cb) (C7)
Here, considering the expression (B6) representing VCa in the state 2 of the capacitance detection circuit shown in FIG. 5 in the case of Cc << Ca + Cb, the expression (B6) can be expressed as follows.

((Cb−Ca) × Vdd + Cc × VDAC) / (Ca + Cb + Cc)
= Vdd × (Cb−Ca) / (Ca + Cb) + Cc × VDAC / (Ca + Cb) (C8)
From the formula (C7) and the formula (C8), the Vdd of the first term of the formula (C8) is as small as Vdd / 2 in the formula (C7).

  Next, when the successive approximation operation ends, the inverting input terminal of the comparator 2, that is, the voltage VA3 of the node A3 becomes the second voltage Vdd / 2. Therefore, VCa at the end of the successive approximation operation is expressed by the following equation.

VCa = Vdd / 2−Vdd / 2 = 0 (C9)
This is the same as the capacitance detection circuit shown in FIG. Also, the voltage with reference to the node A3 applied to the capacitive element Cb, that is, the voltage with reference to the node A3 applied to the node C3 has the same maximum value and fluctuation range as the VCa.

  Therefore, in the capacitance detection circuit according to the present embodiment, the maximum value of VCa and the capacitance detection circuit shown in FIG. 5 in which the capacitance detection circuit described in Patent Literature 1 and the capacitance detection circuit described in Non-Patent Literature 1 are combined are compared. The fluctuation range, that is, the fluctuation of the electrostatic force applied to the capacitive element Ca and the capacitive element Cb can be significantly suppressed, and the reliability reduction due to the fluctuation of the electrostatic force applied to the capacitive element can be prevented. .

  In addition, the capacitance detection circuit according to the present embodiment uses the comparator 2, the successive approximation register circuit 3, and the DA conversion circuit 4 as described above, similarly to the capacitance detection circuit according to the first embodiment. A comparison operation is performed. Then, the comparison result data output from the successive approximation register circuit 3 to the digital output terminal t1 at the end of the successive approximation operation becomes a digital value representing the capacitance difference between the two capacitive elements Ca and Cb. Therefore, in the capacitance detection circuit according to the present embodiment, the voltage representing the capacitance difference between the two capacitance elements Ca and Cb is compared with a predetermined voltage, as in the capacitance detection circuit according to the first embodiment. Therefore, it is not necessary to use an operational amplifier as an analog circuit for increasing power consumption, and it is realized by using only a comparator included in the AD conversion circuit, and an increase in power consumption can be prevented. In the capacitance detection circuit according to the present embodiment, the sensor output, that is, the capacitance difference between the two capacitance elements Ca and Cb can be obtained as a digital value.

[Modification]
The present invention is not limited to the above embodiment, and includes, for example, the following modifications.

(1) Second voltage and third voltage In the capacitance detection circuit according to the embodiment of the present invention, the second voltage is ½ of the first voltage Vdd, and the third voltage However, the present invention is not limited to this.

  The configuration in which the first voltage Vdd is the power supply voltage, the third voltage is the ground voltage, and the second voltage is half the power supply voltage can be realized with a simple circuit, and the capacitance difference of the capacitance detection circuit can be detected. Although it is preferable because the range can be increased, if the second voltage is smaller than the first voltage and the third voltage is smaller than the second voltage, the electrostatic force applied to the capacitor element It is possible to achieve the object of the present invention to prevent a decrease in reliability due to fluctuations.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

1 is a functional block diagram showing a configuration of a capacitance detection circuit according to a first embodiment of the present invention. It is a time chart which shows the state of each node in the capacity | capacitance detection circuit based on the 1st Embodiment of this invention. It is a time chart which shows the state of each switch in the capacity | capacitance detection circuit based on the 1st Embodiment of this invention. 3 is a flowchart showing a successive approximation operation performed by the capacitance detection circuit according to the first embodiment of the present invention. 3 is a functional block diagram illustrating a configuration of a capacitance detection circuit in which a capacitance detection circuit described in Patent Literature 1 and a capacitance detection circuit described in Non-Patent Literature 1 are combined. FIG. It is a functional block diagram which shows the structure of the capacity | capacitance detection circuit based on the 2nd Embodiment of this invention.

Explanation of symbols

  S1 to S4 switch, 1 differential capacitance type sensor unit, 2 comparator, 3 successive approximation register circuit, 4 DA conversion circuit, 10 control circuit, C1, C2, Ca, Cb, Cc capacitive element.

Claims (4)

A capacitance detection circuit that detects a capacitance difference between capacitive elements,
A first switch that switches between one end connected to a first voltage, a second voltage lower than the first voltage, or a floating state;
A second switch that switches between one end connected to the second voltage, a third voltage lower than the second voltage, or a floating state;
A first capacitive element having one end connected to the other end of the first switch;
A second capacitive element having one end connected to the other end of the second switch and the other end connected to the other end of the first capacitive element;
A capacitance detection circuit comprising: a third switch having one end connected to the second voltage and the other end connected to a connection point of the first capacitor and the second capacitor. The capacitance detection circuit further includes:
A first input terminal and a second input terminal, wherein the first input terminal is connected to a connection point of the first capacitive element and the second capacitive element, and the voltage of the first input terminal and The capacitance detection circuit according to claim 1, further comprising a comparator that compares the voltage of the second input terminal and outputs a voltage representing a comparison result. The capacitance detection circuit further includes:
A register circuit for outputting multi-bit data;
A DA conversion circuit that outputs a voltage corresponding to the logic level of each bit of the data received from the register circuit to the second input terminal of the comparator;
The capacitance detection circuit according to claim 2, wherein the register circuit determines a logic level of each bit of the data based on an output voltage of the comparator. The comparator has a predetermined voltage connected to the second input terminal,
The capacitance detection circuit further includes:
A third capacitive element having one end connected to the first input terminal of the comparator;
A register circuit for outputting multi-bit data;
A DA conversion circuit that outputs a voltage according to a logic level of each bit of the data received from the register circuit to the other end of the third capacitive element;
The capacitance detection circuit according to claim 2, wherein the register circuit determines a logic level of each bit of the data based on an output voltage of the comparator.

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