JP2006324541A - Wiring substrate manufacturing method and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technique for securing planarity of terminals formed to a wiring board even if warpage occurs in the wiring board. <P>SOLUTION: The warpage 23 is formed to the rear face region facing a cavity 13 in the wiring board 12. The height of a terminal 19a in the rear face region where the warpage 23 is formed, and that of the surface of each terminal 19b formed to the other parts in the rear face region, are aligned. Concretely, the surface of the terminal 19a and that of each terminal 19b are aligned by respectively adjusting an amount of a conductive material constituting the terminal 19a and the terminals 19b. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a wiring board manufacturing technique and a semiconductor device, and more particularly to a wiring board manufacturing technique that requires flatness of terminals and a technique that is effective when applied to a semiconductor device using the wiring board.

For example, Japanese Unexamined Patent Application Publication No. 2004-072035 (Patent Document 1) discloses a method for manufacturing a ceramic laminated substrate. Specifically, as shown in FIG. 5A of Japanese Patent Application Laid-Open No. 2004-072035, an inorganic composition powder 12 (lower layer) that does not sinter at a firing temperature is placed in a mold 11, and a desired shape is placed thereon. Stack the number of green sheets 10 into the stack. Further, there is disclosed a method for producing a ceramic laminated substrate in which a powder 12 (upper layer) of an inorganic composition is further put thereon and then press-molded. This method is characterized in that the ceramic laminated substrate shrinks only in the thickness direction during firing and does not shrink in the plane direction.
JP 2004-072035 A (2nd page, FIG. 5 (a))

  However, as described in Patent Document 1 described above, when the powder layer of the inorganic composition is pressurized, there is a problem that the propagation of pressure in the powder is not transmitted uniformly unlike the liquid. For this reason, the pressure balance of the pressurized inorganic composition powder is lost, and pressure is not uniformly applied to the green sheet. Therefore, the flatness and thickness uniformity of the ceramic laminated substrate are impaired. That is, warpage occurs in the ceramic laminated substrate.

  For example, when an RF (Radio Frequency) power module is mounted on a mounting board (PCB board; printed circuit board) using solder, there has been a problem that solder wettability of terminals of the RF power module is poor. It has been found that this is because the flatness of the terminals is deteriorated due to the warp of the wiring board (ceramic multilayer substrate) constituting the RF power module.

  Here, attempts have been made to reduce the amount of warpage of the ceramic laminated substrate as much as possible by changing the firing conditions, pressure forming conditions, material additive distribution, and the like. However, there is a limit to this, and the amount of warpage varies depending on the presence or absence of a cavity and the size of the substrate, so it is very difficult to individually control the amount of warpage.

  An object of the present invention is to provide a technique capable of ensuring the flatness of terminals formed on a wiring board even when the wiring board is warped.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  A semiconductor device according to the present invention is mounted on (a) a wiring board, (b) a plurality of terminals formed on a surface opposite to the main surface of the wiring board, and (c) a main surface of the wiring board. A semiconductor chip. Then, even if the wiring substrate is warped, the surfaces of the plurality of terminals are made uniform by adjusting the amounts of the conductive materials constituting the plurality of terminals, respectively.

  The method for manufacturing a wiring board according to the present invention includes (a) a step of firing a wiring board having a cavity on the main surface, and (b) after the step (a), on the side opposite to the main surface of the wiring substrate. A step of arranging a print mask on the surface; and (c) a step of forming a plurality of terminals by printing a conductive material using the print mask as a mask after the step (b).

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  Even when the wiring board is warped, the amounts of the conductive materials constituting the plurality of terminals are adjusted, so that the surfaces of the plurality of terminals can be made uniform. Therefore, since the flatness of the plurality of terminals is ensured, the solder wettability at the plurality of terminals can be improved.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

  Before describing embodiments of the present invention in detail, the meaning of terms in the embodiments will be described as follows.

  GSM (Global System for Mobile Communication) is one of radio communication systems or standards used for digital mobile phones. GSM has three frequency bands of radio waves to be used. The 900 MHz band is called GSM900 or simply GSM, and the 1800 MHz band is called GSM1800, DCS (Digital Cellular System) 1800 or PCN. The 1900 MHz band is called GSM1900, DCS1900, or PCS (Personal Communication Services). GSM1900 is mainly used in North America. In North America, GSM850 in the 850 MHz band may also be used.

  The GMSK modulation method is a method used for audio signal communication, and is a method of shifting the phase of a carrier wave in accordance with transmission data. The EDGE modulation method is a method used for data communication and is a method in which amplitude modulation is added in addition to phase shift.

(Embodiment 1)
In the first embodiment, a case where the semiconductor device of the first embodiment is applied to an RF power module used in a mobile phone will be described.

  FIG. 1 is a circuit block diagram showing an amplifier circuit 1 constituting the RF power module of the first embodiment. FIG. 1 illustrates a dual-band circuit block diagram in which two frequency bands, for example, GSM900 and DCS1800, can be used. In each frequency band, a GMSK (Gaussian filtered Minimum Shift Keying) modulation method and an EDGE (Enhanced) are illustrated. (Data GSM Environment) Two communication methods of modulation method can be used.

  As shown in FIG. 1, the amplifier circuit 1 includes a power amplifier circuit 2 for GSM 900, a power amplifier circuit 3 for DCS 1800, and a peripheral circuit 4 that controls and corrects the amplification operation of these power amplifier circuits 2 and 3. And have. Each of the power amplifier circuits 2 and 3 includes three amplification stages 2a to 2c and 3a to 3c, and three matching circuits 2d to 2f and 3d to 3f, respectively. That is, the input terminals 5a and 5b are electrically connected to the inputs of the first amplification stages 2a and 3a via the input matching circuits 2d and 3d, and the first amplification stages 2a and 3a are connected. The output is electrically connected to the inputs of the second amplification stages 2b and 3b via interstage matching circuits 2e and 3e. The outputs of the second amplification stages 2b and 3b are electrically connected to the inputs of the last amplification stages 2c and 3c via interstage matching circuits 2f and 3f, and the last amplification stages 2c and 3c. Are electrically connected to the output terminals 6a and 6b.

  The peripheral circuit 4 includes a control circuit 4a and a bias circuit 4b for applying a bias voltage to the amplification stages 2a to 2c and 3a to 3c. The control circuit 4a is a circuit that generates a predetermined voltage to be applied to the power amplifier circuits 2 and 3, and includes a power supply control circuit 4c and a bias voltage generation circuit 4d. The power supply control circuit 4c is a circuit that generates a first power supply voltage applied to the drain electrode of each output power MISFET (Metal Insulator Semiconductor Field Effect Transistor) in the amplification stages 2a to 2c and 3a to 3c. The bias voltage generation circuit 4d is a circuit that generates a first control voltage for controlling the bias circuit 4b.

  In the first embodiment, when the power supply control circuit 4c generates the first power supply voltage based on the output level designation signal supplied from the baseband circuit outside the amplifier circuit 1, the bias voltage generation circuit 4d controls the power supply. A first control voltage is generated based on the first power supply voltage generated by the circuit 4c. The baseband circuit is a circuit that generates an output level designation signal. The output level designation signal generated by the baseband circuit is a signal that designates the output level of the power amplifier circuits 2 and 3 and has an output level corresponding to the distance between the mobile phone and the base station, that is, the strength of the radio wave. It is generated based on.

  Next, FIG. 2 is a diagram showing an example of the circuit configuration of the power amplifier circuit 2 and the bias circuit 4b. In FIG. 2, the power amplifying circuit 2 in the present embodiment has a circuit configuration in which three MISFETs Q1 to Q3 are sequentially connected as three amplifying stages 2a to 2c. The output level of the power amplifier circuit 2 is controlled by the first power supply voltage Vdd1 supplied from the power supply control circuit 4c and the gate bias voltage supplied from the bias circuit 4b. The first power supply voltage Vdd1 is supplied to the drain electrodes of the three MISFETs Q1 to Q3.

  The matching circuits 2d to 2f include an inductor (passive component) and a capacitor (passive component), and have a function of matching the input of the amplification stage 2a and impedance between the stages. The capacitor is connected between the inductor and the inputs of the MISFETs Q1 to Q3 of each stage, and has a function of impedance matching and a function of cutting off the DC voltage between the first power supply voltage Vdd1 and the gate bias voltage. Have.

  The bias circuit 4b has a plurality of voltage dividing circuits. Each voltage dividing circuit includes a pair of resistors R1 and R2. Each pair of resistors R1 and R2 is connected in series between the input terminal 5c of the bias circuit 4b and a reference potential (for example, 0 V at the ground potential). And the wiring part which connects between a pair of resistance R1, R2 and the gate electrode of MISFETQ1-Q3 of each stage are electrically connected. Therefore, when the first control voltage is input to the input terminal 5c of the bias circuit 4b, the voltage is divided by the pair of resistors R1 and R2 to generate a predetermined gate bias voltage, and the generated gate bias voltage is The signals are input to the gate electrodes of the MISFETs Q1 to Q3.

  Next, the mounting configuration of the RF power module according to the first embodiment will be described. FIG. 3 is a cross-sectional view showing a state where the RF power module 10 according to the first embodiment is mounted on the mounting substrate 11. In FIG. 3, a concave cavity 13 is formed on the main surface of a wiring substrate 12 made of, for example, a ceramic multilayer substrate. Solder 14 is formed at the bottom of the cavity 13, and a semiconductor chip 15 is mounted in the cavity 13 via the solder 14. For example, a MISFET (Metal Insulator Semiconductor Field Effect Transistor) is formed on the semiconductor chip 15. The semiconductor chip 15 is electrically connected to bonding pads on the wiring substrate 12 by bonding wires 16. The bonding wire 16 is made of, for example, a gold wire.

The wiring board 12 has a multilayer wiring structure in which a plurality of insulating plates on which wiring is formed are laminated and integrated. The insulating plate constituting the wiring board 12 is made of a ceramic such as alumina (aluminum oxide, Al ₂ O ₃ , relative dielectric constant 9 to 9.7) having a low dielectric loss up to the millimeter wave region, for example. For example, a glass epoxy resin or the like may be used.

  A passive component 17 is also mounted on the main surface of the wiring board 12. Examples of the passive component 17 include a resistor, a capacitor, and an inductor that constitute the above-described circuit.

  A via 18 is formed at the bottom of the cavity 13 so as to reach the back surface (the surface opposite to the main surface) of the wiring substrate 12. The via 18 is filled with a conductive material such as copper, and is connected to a terminal 19 a formed on the back surface of the wiring board 12. That is, the solder 14 formed at the bottom of the cavity 13 is electrically and thermally bonded to the terminal 19 a on the back surface of the wiring board 12 through the conductor in the via 18. A reference potential (for example, about 0 V at the ground potential) is supplied to the terminal 19a. That is, the reference potential supplied to the terminal 19 a on the back surface of the wiring board 12 is supplied to the semiconductor chip 15 through the via 18. Conversely, heat generated during the operation of the semiconductor chip 15 is transmitted from the back surface of the semiconductor chip 15 to the terminals 19a on the back surface of the wiring substrate 12 through the solder 14 and the vias 18 and is dissipated. The main surface of the wiring board 12 is covered with a resin (resin) 22 in order to protect the semiconductor chip 15 and the passive component 17 formed on the main surface.

  The RF power module 10 configured as described above is mounted on the mounting substrate 11 using the terminals 19a and 19b. For example, the terminal 19 a is connected to the terminal 21 of the mounting substrate 11 by the solder 20.

  FIG. 4 is an enlarged view of a part of FIG. As shown in FIG. 4, the back surface area of the wiring substrate 12 facing the cavity 13 is recessed as compared with other back surface areas not facing the cavity 13, and a warp 23 is generated in the wiring substrate 12. This occurs in a firing process performed when the wiring board 12 is formed. Therefore, the warp 23 generated in the wiring board 12 is inevitably generated in the process of forming the wiring board 12.

  Here, a plurality of terminals are formed on the back surface of the wiring board 12, but when a warp 23 occurs in the wiring board 12, the terminals formed in the back surface area facing the cavity 13 and the cavity 13 face each other. Inconsistencies in height occur at terminals formed in other non-back areas. That is, the plurality of terminals are usually formed in the same shape and the same height, but at this time, since the warp 23 is generated in the back surface region facing the cavity 13, the back surface region facing the cavity 13 is It is recessed from the other back area. For this reason, the height of the surface of the terminal formed in the back surface region facing the cavity 13 is shifted by the amount of the warp 23 from the height of the surface of the terminal formed in the other back surface region. Then, when the wiring board 12 is mounted on the mounting board, the distance to the solder used for mounting is a terminal formed in the back surface area facing the cavity 13 and wider than the terminals formed in the other back surface areas. End up. Therefore, there is a problem that a contact failure between the terminal formed in the back surface region facing the cavity 13 and the solder is likely to occur. That is, the solder wettability of the terminals formed in the back surface region facing the cavity 13 is deteriorated, and mounting defects are likely to occur.

  Therefore, in the first embodiment, as shown in FIG. 4, the height of the terminal 19a formed in the back surface region facing the cavity 13 is compared with the height of the terminal 19b formed in the other back surface region. It is high. Thereby, even if the back surface area facing the cavity 13 is recessed and the warp 23 is generated, the surface of the terminal 19a and the surface of the terminal 19b can be aligned. That is, in the first embodiment, the height of the terminal 19a is increased by intentionally increasing the amount of the conductive material constituting the terminal 19a than the amount of the conductive material constituting the terminal 19b. Thereby, the amount of warpage of the wiring board 12 is compensated so that the height of the surface of the terminal 19a and the height of the surface of the terminal 19b are made uniform. Thus, the surface of the terminal 19a and the surface of the terminal 19b can be made uniform by adjusting the amount of the conductive material constituting the terminal 19a and the terminal 19b according to the back surface state of the wiring board 12. Therefore, it is possible to prevent poor contact between the terminals 19a formed in the back surface region facing the cavity 13 and the solder, and to ensure solder wettability of the terminals 19a.

  In the first embodiment, in order to improve the contact failure between the terminal 19a and the solder, that is, the solder wettability, the warping of the wiring board 12 itself is not prevented, but the warping of the wiring board 12 is presupposed. One feature is that the heights of the terminals 19b are matched. In other words, even if the warpage of the wiring board 12 is not prevented, if the warp amount is compensated and the heights of the terminals 19a and 19b are made to coincide with each other, even if the warpage occurs, the terminal 19a and the solder are prevented from being warped. Contact failure can be prevented. Thereby, there is no problem even if the wiring board 12 is warped.

  FIG. 5 is a diagram illustrating a state in which the RF power module 10 according to the first embodiment is mounted on the mounting substrate 11. As shown in FIG. 5, although a recess is formed in the back surface region facing the cavity 13 and the warp 23 is generated, the surface of the terminal 19a and the surface of the terminal 19b are configured to be aligned. For this reason, even if the warp 23 is generated, the terminals 19a and the solder 20 can be satisfactorily brought into contact with each other, so that the RF power module 10 can be reliably mounted on the mounting substrate 11.

  The RF power module according to the first embodiment is configured as described above, and a method for manufacturing a wiring board constituting the RF power module will be described below with reference to the drawings.

  First, as shown in FIG. 6, for example, a wiring board 30 having a multilayer ceramic structure is prepared. A cavity 31 is formed on the main surface (the lower surface in FIG. 6) of the wiring substrate 30, and vias 32 are formed from the cavity 31 to the back surface (the upper surface in FIG. 6) of the wiring substrate 30. The via 32 is filled with a conductive material. The wiring board 30 thus configured is fired. The wiring substrate 30 is fired by introducing hot air with a firing temperature of 900 ° C. and a firing time of 12 hours, for example. By this firing step, a recess is formed in the back surface region facing the cavity 31, and a warp 33 is generated in the wiring substrate 30.

  Next, as shown in FIG. 7, a print mask 34 for forming terminals is disposed on the back surface of the wiring board 30 where the warp 33 has occurred. The print mask 34 is patterned so that an opening is formed in a region where a terminal is formed. The printing mask 34 is flat, and even if it is disposed on the back surface of the wiring board 30 where the warp 33 is generated, the flatness is not impaired. That is, it is in close contact with the back surface region of the wiring board 30 where the warp 33 is not generated, and is not in close contact with the back surface region of the wiring substrate 30 where the warp 33 is generated, and there is a gap.

  Subsequently, as shown in FIG. 8, the conductive material 36 is printed on the print mask 34 using the squeegee 35. In this step, the opening formed in the printing mask 34 is filled with the conductive material 36. At this time, a larger amount of conductive material is embedded in the opening in the back surface region where the warp 33 is generated than in the opening in the back surface region where the warp 33 is not generated. That is, adjustment is automatically made so that the conductive material is embedded in each opening up to the height of the printing mask 34.

  And after removing the printing mask 34, the wiring board 30 is dried. This drying step is performed, for example, at a drying temperature of 50 to 80 ° C. and a drying time of about 60 minutes. The wiring substrate 30 is dried to vaporize the binder in the conductive material. By passing through a drying process, the terminal 37a and the terminal 37b as shown in FIG. 9 can be formed. Here, since the conductive material constituting the terminal 37a and the terminal 37b is filled to the same height by the printing mask 34, the surface of the terminal 37a and the surface of the terminal 37b are aligned.

  In this way, the wiring board 30 in which the surface of the terminal 37a and the surface of the terminal 37b are aligned can be manufactured. One feature of the first embodiment is that the terminal 37a and the terminal 37b are formed by using the printing mask 34 after the firing process of the wiring board 30 is performed first. In other words, as in the conventional case, when the terminals are formed using the printing mask and then fired, the surfaces of the plurality of terminals are aligned at the time of forming the terminals, but the wiring board warps by firing. The surface height varies between the terminals. However, in the first embodiment, the wiring substrate 30 is first fired to generate the warp 33. Thereafter, the terminal 37a and the terminal 37b are formed on the wiring board 30 where the warp 33 has occurred using the printing mask 34. At this time, even if the warp 33 is generated in the wiring board 30, the printing mask 34 is flat and is adjusted so that the conductive material is embedded up to the height of the printing mask 34. Therefore, the surface of the terminal 37a to be formed And the surface of the terminal 37b can be aligned.

  Thereafter, solder is formed in the cavity 31 of the wiring board 30 manufactured as described above, and a semiconductor chip is mounted via the solder. A passive component is also mounted on the main surface of the wiring board 30. Then, after the semiconductor chip and the wiring board 30 are connected by a bonding wire such as a gold wire, for example, the main surface of the wiring board 30 is resin-sealed. Subsequently, the RF power module can be manufactured by separating the wiring board 30 into individual pieces. The manufactured RF power module is mounted on the mounting board by the terminals 37 a and 37 b formed on the wiring board 30. At this time, according to the first embodiment, since the surface of the terminal 37a and the surface of the terminal 37b are aligned, the RF power module can be reliably mounted on the mounting substrate.

  According to the first embodiment, since the manufacturing process is simply replaced without adding the manufacturing process, the surface of the terminal 37a and the surface of the terminal 37b can be aligned without causing the process to be complicated.

(Embodiment 2)
In the first embodiment, the example of manufacturing the wiring board by replacing the manufacturing process of the wiring board has been described. In the second embodiment, an example of adding the manufacturing process of the wiring board will be described with reference to the drawings. To do.

  First, for example, a wiring board 40 having a multilayer ceramic structure is prepared. A cavity 41 is formed on the main surface (lower surface in FIG. 10) of the wiring substrate 40, and vias 42 are formed from the cavity 41 to the back surface (upper surface in FIG. 10) of the wiring substrate 40. The via 42 is filled with a conductive material. Next, as shown in FIG. 10, a print mask 43 is disposed on the back surface of the wiring board 40. The printing mask 43 is patterned so that an opening is formed in a region where a terminal is to be formed.

  Subsequently, as shown in FIG. 11, the conductive material 45 is printed using the squeegee 44. At this time, the wiring board 40 is not warped. Then, as shown in FIG. 12, after the drying process is performed to form the terminals 46a and 46b, the wiring board 40 is fired. In this firing step, a warp 47 is generated in the wiring board 40, and the surface of the terminal 46a and the surface of the terminal 46b are shifted.

  Next, as shown in FIG. 13, the above-described print mask 43 is again arranged on the back surface of the wiring board 40. That is, the print mask 43 is rearranged so that the opening of the print mask 43 is on the terminals 46a and 46b. At this time, the opening of the printing mask 43 and the terminal 46b are in close contact. On the other hand, since the warp 47 is formed in the back surface area facing the cavity 41 of the wiring board 40, there is a gap between the opening of the print mask 43 and the terminal 46a.

  Subsequently, as shown in FIG. 14, a conductive material 49 is printed using a squeegee 48. At this time, a larger amount of conductive material is embedded in the opening in the back region where the warp 47 is generated than in the opening in the back region where the warp 47 is not generated. That is, adjustment is automatically made so that the conductive material is embedded in each opening up to the height of the print mask 43.

  Then, after removing the printing mask 43, the wiring board 40 is dried. Through this drying step, the terminals 50a and 50b as shown in FIG. 15 can be formed. Here, since the conductive material constituting the terminal 50a and the terminal 50b is filled to the same height by the rearranged print mask 43, the surface of the terminal 50a and the surface of the terminal 50b are aligned.

  In this way, the wiring board 40 in which the surface of the terminal 50a and the surface of the terminal 50b are aligned can be manufactured. One feature of the second embodiment is that the conductive material is printed by rearranging the print mask 43 after the firing step. That is, one of the features of the second embodiment is that a conductive material printing process using the printing mask 43 is added after the baking process. Thereby, even if the curvature 47 generate | occur | produces in a baking process, the surface of the terminal 50a and the surface of the terminal 50b can be arrange | equalized.

  According to the second embodiment, in addition to the conventional manufacturing process, a conductive material printing process using the same printing mask 43 can be realized after the baking process, so that it is separate from the conventional manufacturing process. This is easier than adding a new process.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  In the above-described embodiment, the example applied to the wiring board having a multilayer structure has been described. Further, in the above-described embodiment, the case where the warp is mainly formed in the back surface region facing the cavity has been described as an example. However, the position of the warp is not limited to the above, and there is a warp in a predetermined region of the wiring board. Can be widely applied to the case.

  The present invention can be widely used in the manufacturing industry for manufacturing semiconductor devices or wiring boards.

It is a circuit block diagram which shows the amplifier circuit which comprises the RF power module in Embodiment 1 of this invention. It is a figure which shows an example of the circuit structure of a power amplifier circuit and a bias circuit. It is sectional drawing which shows a mode that the RF power module in Embodiment 1 was mounted in the mounting board | substrate. It is sectional drawing to which a part of FIG. 3 was expanded. It is sectional drawing which shows a mode that the RF power module in Embodiment 1 was mounted in the mounting board | substrate. 5 is a cross-sectional view showing a manufacturing step of the wiring board in the first embodiment. FIG. FIG. 7 is a cross-sectional view showing a manufacturing step of the wiring board that follows FIG. 6. FIG. 8 is a cross-sectional view showing a manufacturing step of the wiring board that follows FIG. 7. FIG. 9 is a cross-sectional view showing a manufacturing step of the wiring board following that of FIG. 8; FIG. 10 is a cross-sectional view showing a manufacturing process of a wiring board in a second embodiment. FIG. 11 is a cross-sectional view showing a manufacturing step of the wiring board following that of FIG. 10; FIG. 12 is a cross-sectional view showing a manufacturing step of the wiring board following that of FIG. 11; FIG. 13 is a cross-sectional view showing a manufacturing step of the wiring board following that of FIG. 12; FIG. 14 is a cross-sectional view showing a manufacturing step of the wiring board following that of FIG. 13; FIG. 15 is a cross-sectional view showing a manufacturing step of the wiring board following that of FIG. 14;

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Amplifier circuit 2 Power amplifier circuit 2a-2c Amplification stage 2d-2f Matching circuit 3 Power amplifier circuit 3a-3c Amplification stage 3d-3f Matching circuit 4 Peripheral circuit 4a Control circuit 4b Bias circuit 4c Power supply control circuit 4d Bias voltage generation circuit 5a Input terminal 5b Input terminal 5c Input terminal 6a Output terminal 6b Output terminal 10 RF power module 11 Mounting board 12 Wiring board 13 Cavity 14 Solder 15 Semiconductor chip 16 Bonding wire 17 Passive component 18 Via 19a terminal 19b terminal 20 Solder 21 terminal 22 Resin 23 Warpage 30 Wiring board 31 Cavity 32 Via 33 Warpage 34 Print mask 35 Squeegee 36 Conductive material 37a Terminal 37b Terminal 40 Wiring board 41 Cavity 42 Via 43 Print mask 44 Squeegee 45 Conductive material 46a Terminal 46b Terminal 47 Warpage 48 Squeegee 49 Conductive material 50a Terminal 50b Terminal Q1-Q3 MISFET
Vdd1 First power supply voltage R1 resistance R2 resistance

Claims (5)

(A) a wiring board;
(B) a plurality of terminals formed on a surface opposite to the main surface of the wiring board;
(C) a semiconductor chip mounted on the main surface of the wiring board;
Even if the wiring substrate is warped, the surfaces of the plurality of terminals are made uniform by adjusting the amounts of the conductive materials constituting the plurality of terminals. (A) a wiring board having a cavity on the main surface;
(B) a plurality of terminals formed on a surface opposite to the main surface of the wiring board;
(C) a semiconductor chip mounted in the cavity,
Even if warpage occurs in a region facing the cavity of the wiring board, the surface of the plurality of terminals is made uniform by adjusting the amount of the conductive material constituting the plurality of terminals, respectively. apparatus. (A) a multilayer wiring board having a cavity on the main surface;
(B) a plurality of terminals formed on a surface opposite to the main surface of the multilayer wiring board;
(C) a semiconductor chip mounted in the cavity,
A semiconductor device characterized in that even if warpage occurs in the multilayer wiring board, the surfaces of the plurality of terminals are made uniform by adjusting the amounts of the conductive materials constituting the plurality of terminals, respectively. (A) a step of firing a wiring substrate having a cavity on the main surface;
(B) After the step (a), a step of disposing a print mask on a surface opposite to the main surface of the wiring board;
(C) After the step (b), the method includes a step of forming a plurality of terminals by printing a conductive material using the printing mask as a mask. (A) a step of disposing a print mask on a surface opposite to the main surface of the wiring board having a cavity on the main surface;
(B) After the step (a), a step of printing a conductive material using the printing mask as a mask;
(C) after the step (b), firing the wiring board;
(D) After the step (c), the step of arranging the print mask again on the wiring board;
(E) After the step (d), the method includes: forming a plurality of terminals by printing a conductive material using the printing mask as a mask.

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