JP2006311030A - Transimpedance amplifier - Google Patents

Abstract

A high sensitivity and a wide input dynamic range are realized, an instantaneous response corresponding to burst data is realized, and operation stability against noise is realized.
A gain switching determination circuit 250 outputs a gain switching signal SEL based on a result of comparison determination of a comparison input voltage Vc, which is a differential output signal from an intermediate buffer circuit 230, with a first hysteresis characteristic. A gain switching operation for switching the gains of the first and second transimpedance amplifier core circuits 210 and 220 is performed, and the filter circuit 223 reduces the high frequency band of the frequency characteristics of the second transimpedance amplifier core circuit 220.
[Selection] Figure 1

Description

  The present invention relates to a transimpedance amplifier that receives a current signal photoelectrically converted by a light receiving element and converts and amplifies it into a voltage signal in an optical receiving circuit, and more particularly to a transimpedance amplifier that can handle an input current having a large dynamic range.

In an optical transmission circuit such as an optical transmission system capable of high-speed data transmission, an optical interconnection, or a passive optical network (hereinafter referred to as PON) system, an optical receiving circuit that converts an optical signal into an electric signal includes a transformer. Use an impedance amplifier.
The transimpedance amplifier receives the input current Iin obtained by photoelectrically converting the received optical signal by the light receiving element, converts it into an output voltage Vout by a transimpedance gain proportional to the value of the feedback resistor, and outputs it. It is.

In this type of transimpedance amplifier, when the input current Iin increases, the amplitude of the output voltage Vout is saturated and waveform distortion occurs.
Therefore, in order to achieve both high sensitivity and wide dynamic range characteristics, the conventional transimpedance amplifier reduces the value of the feedback resistor and lowers the transimpedance gain when the input current Iin increases, thereby increasing the large current input. The output voltage Vout with little distortion is also obtained.

  FIG. 15 shows a basic configuration of a conventional transimpedance amplifier 300 (see, for example, Non-Patent Document 1). The transimpedance amplifier 300 includes an amplifier circuit 311 and a gain switching circuit 312, and is a circuit that obtains an output voltage Vout by performing voltage amplification on the input current Iin output from the light receiving element 100 to perform signal amplification. The gain switching circuit 312 has a configuration in which a feedback resistor RF and a diode D1 are connected in parallel.

  In the transimpedance amplifier 300, when the input current Iin increases, the voltage difference between the input terminal and the output terminal of the amplifier circuit 311 increases, and the diode D1 inserted in parallel with the feedback resistor RF is turned on. As a result, the value of the feedback resistor is equivalently lowered, so that the transimpedance gain is lowered and saturation of the output voltage Vout can be avoided even when a large current is input.

  FIG. 16 shows a basic configuration of another conventional transimpedance amplifier 400 configured not only to switch the value of one feedback resistor RF by turning on / off a diode but also to switch and connect a plurality of feedback resistors as a gain switching circuit. (For example, see Patent Document 1). The transimpedance amplifier 400 includes a transimpedance amplifier core circuit 410 and a gain switching determination circuit 420. The transimpedance amplifier core circuit 410 includes an amplifier circuit 411 and a gain switching circuit 412, and performs signal amplification by converting the input current Iin output from the light receiving element 100 into a voltage. The gain switching determination circuit 420 controls the gain switching in the gain switching circuit 412 according to the output voltage Vout from the transimpedance amplifier core circuit 410.

  In this transimpedance amplifier 400, a gain switching circuit 412 is constituted by a plurality of feedback resistors in which switches are connected in series, and the gain obtained by monitoring the DC level of the output voltage Vout from the amplification circuit 411 by the gain switching determination circuit 420. The value of the feedback resistor is switched by turning on / off the switch of the gain switching circuit 412 by the switching signal SEL.

The applicant has not yet found prior art documents related to the present invention by the time of filing other than the prior art documents specified by the prior art document information described in this specification.
Japanese Patent No. 3259707 (Japanese Patent Laid-Open No. 2000-252774) Saruwatari, Sugawara, Ibe, “156-Mbps optical receiver for burst signals”, IEICE General Conference, Proceedings, 1997, B-10-128

  Usually, an optical transmission system that enables high-speed data transmission, particularly a PON system, requires high sensitivity, a wide input dynamic range, and burst response. FIG. 17 shows the configuration of the PON system. This PON system is composed of one station side device (OLT: Optical Line Terminal) 501 and a plurality of home side devices (ONU: Optical Network Units) 511 to 51n, and a passive device such as an optical coupler 502 and an optical fiber. 503 is connected.

  At this time, the upstream (from ONU to OLT) data from each of the home-side devices 511 to 51n, that is, the packets 521 to 52n, have different optical powers when reaching the station-side device 501 due to the difference in the respective paths. . For this reason, a wide dynamic range is required for a transimpedance amplifier (TIA: TransImpedance Amp) used in the optical receiving circuit of the station side device 501.

  In the PON system of FIG. 17, while a certain home-side device is sending packets (packet period), other home-side devices cannot send packets, so to increase transmission efficiency, shorten the time between packets. There is a need to. As shown in FIG. 18, a specific bit called a preamble 531 is prepared at the head of the packet 520 and is used for packet synchronization in the station side device 501.

  As described above, the signal amplitude of each packet 520 varies from packet to packet due to the optical power difference Pd when reaching the station-side device 501. Further, in order to increase the transmission efficiency, it is necessary to synchronize the packet with the short preamble 531 and receive the subsequent payload 532, and an optical receiving circuit capable of instantaneously switching the gain with the short preamble 531 is required. Become. For this reason, the optical receiving circuit is required to have a transimpedance amplifier capable of instantaneous response and having a wide dynamic range.

  However, in the conventional technique described above, for example, according to the conventional transimpedance amplifier 300 described with reference to FIG. 15, the diode D1 is inserted in parallel with the feedback resistor RF. Therefore, when the input current Iin increases, A large distortion occurs in the DC transfer characteristic of the output voltage Vout, and the duty of the waveform of the output voltage Vout is deteriorated. When the duty characteristic is deteriorated, there is a problem that a code error occurs and the transmission characteristic is deteriorated.

  Further, according to the conventional transimpedance amplifier 400 described with reference to FIG. 16, the problem of distortion of the DC transfer characteristic can be solved, but the determination of gain switching by the gain switching determination circuit 420 is usually performed by the output of the transimpedance amplifier 400. Since the high level and low level of the voltage Vout are held by the high level hold circuit and the low level hold circuit, respectively, and the switching determination is performed by identifying that the potential difference has become a certain level or more by the comparator 423 or the like. There was a problem that it took time and was inferior in instantaneous response.

  That is, the high level hold circuit is composed of an operational amplifier 421, a capacitor C1, and a diode D2, and the low level hold circuit is composed of an operational amplifier 422, a capacitor C2, and a diode D3. Although it is necessary to give C2 a large capacity, in this case, since it takes time until the capacitors C1 and C2 are charged, an instantaneous response becomes difficult. Further, when the capacitors C1 and C2 are configured in the LSI, the layout area becomes large.

  Further, in order to realize a high sensitivity and a wide dynamic range, when the number of feedback resistors of the gain switching circuit 412 is increased to two or more, it is necessary to grasp a gain state by a gain switching determination algorithm. It becomes a factor which lowers instantaneous responsiveness with complication of composition. As a circuit example for grasping the gain state, for example, a holding circuit 430 that holds a state by a logic circuit using SR latch circuits 431 and 432 and an AND circuit 43 as shown in FIG. 19 is known.

As described above, the conventional transimpedance amplifier that achieves a wide input dynamic range with high sensitivity has a problem that it cannot realize an instantaneous response corresponding to burst data. In addition, when emphasis is placed on instantaneous response, malfunctions due to noise tend to increase, so a configuration for suppressing noise and obtaining operational stability is also necessary. There has been a problem that the operational stability with respect to is not considered much.
The present invention is intended to solve such a problem. A transimpedance amplifier capable of realizing high sensitivity and a wide input dynamic range, realizing an instantaneous response corresponding to burst data, and realizing operation stability against noise. The purpose is to provide.

  In order to achieve such an object, a transimpedance amplifier according to the present invention includes a first transimpedance amplifier core circuit that amplifies a current input to an input terminal with a desired gain and outputs the amplified signal as a voltage signal. A second transimpedance amplifier core circuit having the same configuration as that of the first transimpedance amplifier core circuit and having an input terminal opened, and output signals from the first and second transimpedance amplifier core circuits are differentially amplified and output. An intermediate stage buffer circuit and a differential output signal output from the intermediate stage buffer circuit is used as a comparison input voltage, and the first and second transimpedances are based on a result of comparison and determination of the comparison input voltage using the first hysteresis characteristic. Gain switching judgment circuit for outputting a gain switching signal for switching the gain of the amplifier core circuit The first transimpedance amplifier core circuit includes a gain switching circuit that switches the gain based on the gain switching signal, and the second transimpedance amplifier core circuit includes a gain switching circuit that switches the gain based on the gain switching signal; And a filter circuit for attenuating the high frequency component of the voltage signal output from the second transimpedance amplifier core circuit.

  At this time, a capacitive element may be used as the filter circuit.

  In addition, the first transimpedance amplifier core circuit is provided with an amplifier circuit that amplifies the current input to the signal input terminal connected to the input terminal with a gain determined by the feedback resistance value and outputs it as a voltage signal from the signal output terminal, The gain switching circuit is connected between the signal input terminal and the signal output terminal of the amplifier circuit, and the feedback resistance value is switched based on the gain switching signal, and the filter circuit is connected between the signal input terminal and the signal output terminal of the amplifier circuit. You may implement | achieve with the capacitive element connected between.

  Alternatively, the first transimpedance amplifier core circuit is provided with an amplifier circuit that amplifies the current input to the signal input terminal connected to the input terminal with a gain determined by the feedback resistance value and outputs the amplified signal as a voltage signal from the signal output terminal. The gain switching circuit is connected between the signal input terminal and the signal output terminal of the amplifier circuit, and the feedback resistance value is switched based on the gain switching signal. The filter circuit is connected to the signal input terminal of the amplifier circuit and the predetermined power supply potential. It may be realized by a capacitive element connected between the two.

  Alternatively, the first transimpedance amplifier core circuit is provided with an amplifier circuit that amplifies the current input to the signal input terminal connected to the input terminal with a gain determined by the feedback resistance value and outputs the amplified signal as a voltage signal from the signal output terminal. The gain switching circuit is connected between the signal input terminal and the signal output terminal of the amplifier circuit, and the feedback resistance value is switched based on the gain switching signal. The filter circuit is connected to the signal output terminal of the amplifier circuit and the predetermined power supply potential. It may be realized by a capacitive element connected between the two.

At this time, the filter circuit may be provided with a switch that disconnects at least one of the connection terminals of the capacitive element based on the gain switching signal.
Further, the switch may be turned on in a state where the gain switching circuit selects the highest gain.
Further, a MOS transistor may be used as the switch.

  According to the present invention, the gain switching determination circuit outputs the gain switching signal based on the result of the comparison determination of the comparison input voltage, which is the differential output signal from the intermediate buffer circuit, using the first hysteresis characteristic. A gain switching operation for switching the gains of the first and second transimpedance amplifier core circuits is performed, and a high frequency component is attenuated from the second transimpedance amplifier core circuit by the filter circuit of the second transimpedance amplifier core circuit. An output signal is output.

  As a result, hysteresis characteristics are used to determine whether or not gain switching is necessary based on the comparison input voltage, so there is no need to hold the comparison input voltage for gain switching determination with a level hold circuit with a slow response time. Gain switching can be determined instantaneously based on a comparison input voltage that changes in accordance with the current, and an instantaneous response corresponding to burst data can be realized. Further, the noise band of the output signal from the second transimpedance amplifier core circuit can be reduced by the filter circuit, and a sufficiently low noise characteristic can be obtained.

In addition, when performing gain switching, the second transimpedance core circuit that outputs a reference potential to generate a differential signal with less distortion needs to generate the same output potential as the output potential of the first transimpedance circuit. However, by performing switching control of the filter circuit that reduces the noise band of the second transimpedance core circuit with a switch, noise characteristics can be improved and instantaneous response and operation stability can be obtained.
Therefore, even when importance is placed on low noise, it is possible to obtain stable operation by suppressing noise, and it is possible to realize a transimpedance amplifier having both instantaneous response and operational stability.

Next, embodiments of the present invention will be described with reference to the drawings.
[First Embodiment]
First, a transimpedance amplifier according to a first embodiment of the present invention will be described with reference to FIG. FIG. 1 is a block diagram showing the configuration of the transimpedance amplifier according to the first embodiment of the present invention.

  The transimpedance amplifier 200 electrically converts an optical signal received from the optical fiber received by the light receiving element 100 in an optical transmission circuit such as an optical transmission system, an optical interconnection, or a passive optical network (PON) system that enables high-speed data transmission. Used in an optical receiving circuit that converts signals.

  As shown in FIG. 1, the transimpedance amplifier 200 includes a first transimpedance amplifier core circuit 210, a second transimpedance amplifier core circuit 220, an intermediate stage buffer circuit 230, an output buffer circuit 240, as main circuit configurations. And a gain switching determination circuit 250.

  The first transimpedance amplifier core circuit 210 has an input terminal connected to the output terminal of the light receiving element 100, converts the input current Iin output from the light receiving element 100 to voltage amplification, and performs signal amplification according to the input current Iin. Is connected between the input terminal and the output terminal of the amplifier circuit 211, and is amplified according to the gain switching signal SEL from the gain switching determination circuit 250. And a gain switching circuit 212 for switching the transimpedance gain of the circuit 211.

  The second transimpedance amplifier core circuit 220 is similar to the amplifier circuit 211 of the first transimpedance amplifier core circuit 210, but has an input terminal open, and according to the input current Iin as a reference voltage of the output voltage V1. An amplification circuit 221 that outputs a constant output voltage V2 that does not change from the output terminal, a gain switching circuit 222 similar to the gain switching circuit 212 of the first transimpedance amplifier core circuit 210, and an output voltage that is output from the amplification circuit 221 And a filter circuit 223 that attenuates the high-frequency component of V2.

In the intermediate stage buffer circuit 230, the output terminals of the first and second transimpedance amplifier core circuits 210 and 220 are connected to the differential input terminal, and the output voltages V1 and V2 input to the differential input terminal are differentiated. This is a buffer circuit that dynamically amplifies (for example, gain = 1) and outputs from a differential output terminal as a differential output signal composed of an output voltage V3 (non-inverted output) and an output voltage V4 (inverted output).
In the output buffer circuit 240, the differential output terminal of the intermediate buffer circuit 230 is connected to the differential input terminal, and the output voltages V3 and V4 input to the differential input terminal are differentially amplified (for example, gain = 1) A buffer circuit that outputs the output voltages Voutp (non-inverted output) and Voutn (inverted output) as the output voltage Vout of the transimpedance amplifier 200.

  The gain switching determination circuit 250 receives the comparison input voltage Vc (= V4−V3) composed of the output voltages V3 and V4 of the intermediate buffer circuit 230 as an input, and compares the comparison input voltage with the first hysteresis characteristic. And a gain switching comparator 251 that outputs a gain switching signal SEL to the gain switching circuits 212 and 222 of the first and second transimpedance amplifier core circuits 210 and 220. This is a determination circuit that switches the gains of the first and second transimpedance amplifier core circuits 210 and 220 in accordance with the input current Iin.

  In the present embodiment, the gain switching determination circuit 250 outputs a gain switching signal based on the result of comparing and determining the comparison input voltage Vc, which is the differential output signal from the intermediate stage buffer circuit 230, with the first hysteresis characteristic. Thus, the gain switching operation for switching the gains of the first and second transimpedance amplifier core circuits 210 and 220 is performed, and the output voltage V2 in which the high frequency component is attenuated is output from the second transimpedance amplifier core circuit 220. It is a thing.

[Transimpedance amplifier core circuit]
Next, the first transimpedance amplifier core circuit used in the transimpedance amplifier according to the first embodiment of the present invention will be described in detail with reference to FIG. 2 and FIG. FIG. 2 is a circuit diagram showing a configuration of a first transimpedance amplifier core circuit used in the transimpedance amplifier according to the first embodiment of the present invention. FIG. 3 is a circuit diagram showing a configuration of a second transimpedance amplifier core circuit used in the transimpedance amplifier according to the first embodiment of the present invention.

As shown in FIG. 2, the first transimpedance amplifier core circuit 210 includes an amplifier circuit 211 and a gain switching circuit 212.
The amplifier circuit 211 is an amplifier circuit that amplifies an input current Iin input to a signal input terminal connected to the input terminal with a gain determined by a feedback resistance value, and outputs the amplified signal as a voltage signal from the signal output terminal.
The gain switching circuit 212 is a circuit that is connected between the signal input terminal and the signal output terminal of the amplification circuit 211 and switches the feedback resistance value of the amplification circuit 211 based on the gain switching signal SEL from the gain switching determination circuit 250. In FIG. 2, the gain switching circuit 212 is composed of a parallel circuit of a resistance element RFa and a resistance element RFb (resistance value: RFa> RFb), and the resistance element RFb is turned on / off according to the gain switching signal SEL. A switch SW1 is connected in series.

The switch SW1 is composed of, for example, an NMOS transistor. When the gain switching signal SEL input to the gate terminal thereof is at a low level, the switch SW1 is turned off (off), and the feedback resistance value of the entire gain switching circuit 212 is a resistance element. The resistance value is RFa. On the other hand, when the gain switching signal SEL input to the gate terminal is at a high level, the conductive element is turned on, the resistance element RFa and the resistance element FRb are connected in parallel, and the feedback resistance value of the entire gain switching circuit 212 is a resistance value. This is the parallel connection resistance value of the element RFa and the resistance element FRb.
Therefore, since the feedback resistance value is large when the gain switching signal SEL is LOW level, the gain of the first transimpedance amplifier core circuit 210 is large, and when the gain switching signal SEL is HIGH level, the feedback resistance value is small. The gain of the first transimpedance amplifier core circuit 210 is reduced.

As shown in FIG. 3, the second transimpedance amplifier core circuit 220 includes an amplifier circuit 221, a gain switching circuit 222, and a filter circuit 223.
The amplifier circuit 221 is an amplifier circuit that amplifies the input current Iin input to the signal input terminal with a gain determined by the feedback resistance value, and outputs the amplified signal as a voltage signal from the signal output terminal. In the case of the second transimpedance amplifier core circuit 220, since the signal input terminal is open, the output voltage V2 (DC voltage) when the input current Iin is zero (no input) is output from the signal output terminal.

  The gain switching circuit 222 is a circuit that is connected between the signal input terminal and the signal output terminal of the amplification circuit 221 and switches the feedback resistance value of the amplification circuit 221 based on the gain switching signal SEL from the gain switching determination circuit 250. In FIG. 3, the gain switching circuit 222 is composed of a parallel circuit of a resistance element RFa and a resistance element RFb, and a switch SW1 that is turned on / off in response to a gain switching signal SEL is connected in series to the resistance element RFb. . The operation of the gain switching circuit 222 is the same as that of the gain switching circuit 212 described above, and a description thereof is omitted here.

The filter circuit 223 is a circuit that attenuates the high-frequency component of the output voltage V <b> 2 output from the amplifier circuit 221. FIG. 3 shows a filter circuit 223 including a capacitive element C connected between a signal input terminal and a signal output terminal of the amplifier circuit 221, and in cooperation with the amplifier circuit 221 and the gain switching circuit 222, An amplifier circuit with a low-pass filter function is configured.
The arrangement position of the filter circuit 223 is not limited between the signal input terminal and the signal output terminal of the amplifier circuit 221, and may be arranged at other positions such as the filter circuit 223X and the filter circuit 223Y.

For example, the filter circuit 223X shows an example connected between the signal input terminal of the amplifier circuit 221 and the ground potential, and the high frequency component of the input signal input to the amplifier circuit 221 is caused by the capacitive element C of the filter circuit 223X. As a result, the low-noise output voltage V2 is output from the second transimpedance amplifier core circuit 220.
Further, the filter circuit 223Y is shown as being connected between the signal output terminal of the amplifier circuit 221 and the ground potential, and the high-frequency component of the output voltage V2 output from the amplifier circuit 221 is the capacitive element C of the filter circuit 223Y. As a result, the low-noise output voltage V2 is output from the second transimpedance amplifier core circuit 220.
In the filter circuits 223X and 223Y, the ground potential to which one end of the capacitor is connected may be any power supply potential as long as it has a low impedance.

[Operation of First Embodiment]
Next, the operation of the transimpedance amplifier according to the first exemplary embodiment of the present invention will be described with reference to FIGS. FIG. 4 is a signal waveform example in each part of the transimpedance amplifier according to the first exemplary embodiment of the present invention. FIG. 5 is an example of hysteresis characteristics of the gain switching comparator. FIG. 6 is an example of operating characteristics of the gain switching comparator. FIG. 7 is a timing chart showing an operation example of the transimpedance amplifier according to the first exemplary embodiment of the present invention.

First, operations of the first transimpedance amplifier core circuit 210, the second transimpedance amplifier core circuit 220, the intermediate stage buffer circuit 230, and the output buffer circuit 240 will be described with reference to FIG.
An optical signal that arrives at the station side device (OLT) from the home side device (ONU) via the optical fiber is separated by an optical wavelength division multiplex circuit (WDM) of the station side device, and then an optical reception circuit. The light receiving element 100 performs photoelectric conversion and is input to the transimpedance amplifier 200 as an input current Iin.

The first transimpedance amplifier core circuit 210 of the transimpedance amplifier 200 converts the input input current Iin into a voltage by the amplifier circuit 211 to perform signal amplification, and outputs an output voltage V1 that changes in accordance with the input current Iin. To do.
On the other hand, the second transimpedance amplifier core circuit 220 always outputs a constant output voltage V2 that does not change according to the input current Iin as a reference voltage of the output voltage V1.

The intermediate stage buffer circuit 230 receives the output voltage V1 of the first transimpedance amplifier core circuit 210 and the output voltage V2 of the second transimpedance amplifier core circuit 220. When the input current Iin increases, the output voltage V3 is increased. , V4, a differential output signal is obtained such that the potential difference (V4−V3) becomes large. These output voltages V3 and V4 have signal waveforms having amplitudes that are symmetrical up and down around a predetermined center potential V0.
The differential output signal of the intermediate stage buffer circuit 230 is input to the output buffer circuit 240 and output as the output voltage Vout of the transimpedance amplifier 200 composed of the output voltages Voutp (non-inverted output) and Voutn (inverted output).

Next, the operation of the gain switching determination circuit 250 will be described with reference to FIGS.
The differential output signal of the intermediate stage buffer circuit 230 is supplied as a comparison input voltage Vc to the gain switching determination circuit 250 and input to the gain switching comparator 251 of the gain switching determination circuit 250.
As shown in FIG. 5, the gain switching comparator 251 has a hysteresis characteristic (first hysteresis characteristic) composed of a predetermined voltage detection level Vh. Here, the input voltage at the differential input terminal where the rising operation of the hysteresis comparator is performed, that is, the comparison input voltage is referred to as a voltage detection level.

In the configuration of the transimpedance amplifier 200 according to the present embodiment, since the input current Iin is always input from the light receiving element 100, the output voltage V2> the output voltage V1, and the comparison input voltage Vc (= V4-V3)> 0. It is.
In the gain switching comparator 251 that uses the comparison input voltage Vc as a differential input, the comparison input voltage Vc is compared with the voltage detection level Vh. Therefore, when the comparison input voltage Vc exceeds the voltage detection level Vh, the output from the gain switching comparator 251, that is, the logic of the gain switching signal SEL is inverted.

At this time, once inverted, the output logic is not reset unless the comparison input voltage Vc is changed until the falling operation of the hysteresis characteristic. In this embodiment, since the comparison input voltage Vc> 0, the comparison input voltage Vc does not change until the falling operation of the hysteresis characteristic, and when it is inverted once as a result, the logic is retained. Therefore, when the comparison input voltage Vc when the input signal Iin is zero is set to the reference voltage Vn, the gain switching comparator 251 uses only the hysteresis characteristic (rise operation region) for the comparison input voltage Vc higher than the reference voltage Vn. .
In this embodiment, before receiving a packet, the logic of the gain switching signal SEL is initialized to “high gain”, and the logic of the gain switching signal SEL is changed according to the rising operation in the hysteresis characteristic of the gain switching comparator 251. Is switched from “high gain” to “low gain”.

  As for initialization of the gain switching signal SEL, a switch (MOS transistor) that forcibly returns the comparison potential of the hysteresis comparator in the gain switching comparator 251 to the initial value in response to an external reset signal is provided. 251 may be provided. The external reset signal can be obtained by detecting a reset signal sent for each packet from the network side using a known technique.

  Therefore, as shown in FIG. 6, when the input current Iin reaches the current value I1, the comparison input voltage Vc reaches the voltage detection level Vh, the gain switching comparator 251 rises, and the gain switching signal SEL The logic is switched from “high gain” to “low gain”. As a result, the gains of the first and second transimpedance amplifier core circuits 210 and 220 are reduced, and as a result, the output voltage Vout and the comparison input voltage Vc of the transimpedance amplifier are reduced.

  As a result, as shown in FIG. 7, when reception of a packet is started at time T1, the input current Iin increases, and when the comparison input voltage Vc reaches the voltage detection level Vh at time T2, the gain switching comparator 251 The gain switching signal SEL is inverted from “high gain” to “low gain”. Thereby, the gains of the first and second transimpedance amplifier core circuits 210 and 220 are reduced.

  Thereafter, even if the comparison input voltage Vc falls below the voltage detection level Vh due to the gain reduction, the gain switching comparator 251 does not perform the falling operation unless the Vc <−Vh is satisfied due to the hysteresis characteristic of the gain switching comparator 251, and the gain switching signal SEL does not reverse from “high gain” to “low gain”. As a result, the first and second transimpedance amplifier cores can be used even when the gain is reduced or the input current Iin is reduced after the logic of the gain switching signal SEL is switched from “high gain” to “low gain”. The gains of the circuits 210 and 220 are maintained, and a stable output voltage Vout is output.

  As described above, in the present embodiment, the gain switching determination circuit 250 performs the gain switching signal based on the result of comparing and determining the comparison input voltage Vc that is the differential output signal from the intermediate buffer circuit 230 with the first hysteresis characteristic. Since the gain switching operation for switching the gains of the first and second transimpedance amplifier core circuits 210 and 220 is performed by outputting SEL, in order to determine whether or not the gain switching is necessary based on the comparison input voltage Vc. Since the hysteresis characteristic is used, it is not necessary to hold the comparison input voltage Vc for determining the gain switching by the level hold circuit with a slow response time, and the gain is instantaneously based on the comparison input voltage Vc that changes according to the input current Iin. Switching judgment is possible, and an instantaneous response corresponding to burst data can be realized.

  Further, in the present embodiment, the filter circuit 223 is provided in the second transimpedance amplifier core circuit 220 so as to output the output voltage V2 in which the high frequency component is attenuated, so that the signal of the output voltage V2 serving as the reference voltage is output. Bandwidth can be reduced and sufficient low noise characteristics can be obtained.

As in this embodiment, two transimpedance amplifier core circuits are provided, and one of the first transimpedance amplifier core circuits 210 is used as a main core for amplifying the input current Iin from the light receiving element 100, and the other In the transimpedance amplifier configured to use the second transimpedance amplifier core circuit 220 as a dummy core for generating a reference potential, the same circuit configuration is used for the main core and the dummy core in order to reduce noise.
However, in such a configuration, although high instantaneous response can be obtained, since the dummy core has the same wide frequency characteristics as the main core, a high-frequency component due to noise tends to appear in the reference voltage that originally requires only a DC component, This will cause the noise characteristics to deteriorate.

In the present embodiment, a filter circuit 223 is provided in the second transimpedance amplifier core circuit 220 corresponding to this dummy core so as to reduce the high frequency band of the frequency characteristics of the second transimpedance amplifier core circuit 220. Therefore, the signal band of the reference voltage, that is, the output voltage V2 can be reduced, and a sufficiently low noise characteristic can be obtained.
Therefore, even when emphasis is placed on instantaneous response, noise can be suppressed and operation stability can be obtained, and a transimpedance amplifier having both instantaneous response and operation stability can be realized.

[Second Embodiment]
Next, a transimpedance amplifier according to a second embodiment of the present invention will be described with reference to FIG. FIG. 8 is a circuit diagram showing a configuration of a gain switching determination circuit used in the transimpedance amplifier according to the second embodiment of the present invention. FIG. 9 is a circuit diagram showing a configuration example of the first transimpedance amplifier core circuit used in the transimpedance amplifier according to the second embodiment of the present invention. The same reference numerals are given. FIG. 10 is a circuit diagram showing a configuration example of a second transimpedance amplifier core circuit used in the transimpedance amplifier according to the second embodiment of the present invention. The same reference numerals are given.

  In the first embodiment described above, the case where the gain switching in the transimpedance amplifier core circuits 210 and 220 is one-stage switching between “high gain” and “low gain” has been described as an example. In the present embodiment, when gain switching is performed in a plurality of stages, specifically, gain switching in transimpedance amplifier core circuits 210 and 220 is “high gain”, “medium gain”, and “low gain”. A case of stage switching will be described as an example. Of the transimpedance amplifier according to the present embodiment, configurations other than the gain switching determination circuit and the first and second transimpedance amplifier core circuits are the same as those of the first embodiment described above, and here The detailed description in is omitted.

  As shown in FIG. 8, compared to the gain switching determination circuit 250 described in the first embodiment, the gain switching determination circuit 250A used in the present embodiment includes the gain switching comparator 251 described above. Thus, a gain switching comparator 252 and a switch 253 are added. Among these, the gain switching comparator 252 is equivalent to the gain switching comparator 251 described above.

  The switch 253 is a switch circuit provided between the differential output terminal of the intermediate stage buffer circuit 230 and the differential input terminal of the gain switching comparator 252. The output terminal of the gain switching comparator 251 is connected to the switching control input terminal of the switch 253, and the logic of the first gain switching signal SEL1 output from the gain switching comparator 251 is changed from “high gain” to “medium gain”. When the signal is inverted, the operation is performed from “off” to “on”, and the comparison input voltage Vc is supplied to the gain switching comparator 252.

  The gain switching comparator 252 has a differential input terminal connected to the differential output terminal of the intermediate buffer circuit 230 via the switch 253, and compares and determines the comparison input voltage Vc input to the differential input terminal with hysteresis characteristics. A hysteresis comparator that performs a gain switching operation for switching the gain of the transimpedance amplifier core circuits 210 and 220 from “medium gain” to “low gain” by outputting a gain switching signal SEL2 corresponding to the result from the output terminal. is there.

  Further, as shown in FIG. 9, compared to the first transimpedance amplifier core circuit 210 described in the first embodiment, the first transimpedance amplifier core circuit 210A used in the present embodiment is Is provided with a gain switching circuit 212 </ b> A instead of the gain switching circuit 212.

  In the gain switching circuit 212A, a series connection circuit of a resistance element RFc (resistance value: RFa> RFb> RFc) and a switch SW2 is added in parallel to the resistance element RFa of the gain switching circuit 212. At this time, the switch SW1 operates according to the logic of the first gain switching signal SEL1, and the switch SW2 operates according to the logic of the second gain switching signal SEL2. With the switches SW1 and SW2 turned off, the feedback resistance value is the largest and “high gain”. Thereafter, by turning on the switches SW1 and SW2 in order, the feedback resistance value decreases stepwise, and the transition is made from “high gain” → “medium gain” → “low gain”.

  Further, as shown in FIG. 10, the second transimpedance amplifier core circuit 220A used in the present embodiment is compared with the second transimpedance amplifier core circuit 220 described in the first embodiment. A gain switching circuit 222A is provided instead of the gain switching circuit 222, and a filter circuit 223A is provided instead of the filter circuit 223.

The gain switching circuit 222A has the same configuration as that of the gain switching circuit 212A. By turning on the switches SW1 and SW2 in order, the feedback resistance value decreases stepwise, and “high gain” → “medium gain” → “low gain”. Transition.
The filter circuit 223A includes a series connection circuit of a capacitive element C and a switch SWc, and is switched according to the logic of the first gain switching signal SEL1 and the second gain switching signal SEL2. The connection / release of the capacitive element C is controlled in accordance with the gain of the circuit 220A.

[Operation of Second Embodiment]
Next, the operation of the transimpedance amplifier according to the second exemplary embodiment of the present invention will be described with reference to FIG. FIG. 11 is an example of operating characteristics of the gain switching comparator. FIG. 12 is a timing chart showing an operation example of the transimpedance amplifier according to the second exemplary embodiment of the present invention. Here, a case will be described in which filter circuit 223A is operated only when the gains of first and second transimpedance amplifier core circuits 210A and 220A are maximum, and filter circuit 223A is set in a non-operating state at other gains.

  As shown in FIG. 11, in the period until the input current Iin increases and reaches the current value I1, that is, in the initial state, the gain switching signal SEL1 is “high gain” because the comparison input voltage Vc is smaller than the voltage detection level Vh. The logic of Accordingly, the switch 253 is controlled to be in an OFF state, and the comparison input voltage Vc is not supplied to the gain switching comparator 252. Therefore, the gain switching signal SEL2 indicates a “medium gain” logic. Accordingly, the switches SW1 and SW2 of the gain switching circuits 212A and 212B are turned off and “high gain” is selected.

  Further, the switch SWc is turned on by the gain switching signal SEL1, and the capacitor C is connected between the signal input terminal and the signal output terminal of the amplifier circuit 221, and the filter circuit 223A operates. Thereby, when “high gain” is selected, the high frequency band of the frequency characteristics of the second transimpedance amplifier core circuit 220 is reduced, the signal band of the reference voltage, that is, the output voltage V2, is reduced, and the low noise characteristics. A transimpedance amplifier having is realized.

Thereafter, when the input current Iin increases and reaches the current value I1, the comparison input voltage Vc reaches the voltage detection level Vh, the gain switching comparator 251 starts up, and the logic of the gain switching signal SEL1 is “gain”. “Large” to “Medium”. As a result, the switch SW1 of the gain switching circuits 212A and 212B is controlled to be in the on state, the feedback resistance value is reduced, and “medium gain” is selected.
Further, the switch SWc is turned off by the gain switching signal SEL1, and the capacitive element C is disconnected from between the signal input terminal and the signal output terminal of the amplifier circuit 221, and the filter circuit 223A is deactivated. Thereby, when a value other than “high gain” is selected, the frequency characteristics of the second transimpedance amplifier core circuit 220 are not reduced.

  When the logic of the gain switching signal SEL 1 is switched from “high gain” to “medium gain”, the switch 253 is turned on and the comparison input voltage Vc is supplied to the gain switching comparator 252. At this time, as described above, the gains of the first and second transimpedance amplifier core circuits 210A and 220A are controlled to “medium gain”, and as a result, the output voltage Vout and the comparison input voltage Vc of the transimpedance amplifier are reduced. To do. For this reason, in the gain switching comparator 252, the comparison input voltage Vc does not reach the voltage detection level Vh, and the logic of the gain switching signal SEL2 remains “in gain”.

Thereafter, when the input current Iin further increases and reaches the current value I2, the comparison input voltage Vc reaches the voltage detection level Vh again, the gain switching comparator 252 rises, and the logic of the gain switching signal SEL2 becomes Switching from “medium gain” to “small gain”. As a result, the switch SW2 of the gain switching circuits 212A and 212B is controlled to be in the ON state, the feedback resistance value is further reduced, and “low gain” is selected.
Further, the switch SWc remains in the OFF state by the gain switching signal SEL1, and the capacitive element C is disconnected from between the signal input terminal and the signal output terminal of the amplifier circuit 221, and the filter circuit 223A remains inactive. Thereby, when a value other than “high gain” is selected, the frequency characteristics of the second transimpedance amplifier core circuit 220 are not reduced.

  As a result, as shown in FIG. 12, the gain switching signal SEL1 from the gain switching comparator 251 is “gain” during the period from the start of packet reception at time T11 until the comparison input voltage Vc reaches the voltage detection level Vh. “High” and the gain switching signal SEL2 indicates “medium gain”, so that the switches SW1 and SW2 are turned off, and the gains of the first and second transimpedance amplifier core circuits 210 and 220 are “high gain”. Become. Further, the switch SWc is turned on, the filter circuit 223A is connected, and the frequency characteristics of the second transimpedance amplifier core circuit 220 are reduced.

  Thereafter, when the input current Iin increases and the comparison input voltage Vc reaches the voltage detection level Vh at time T12, the gain switching signal SEL1 from the gain switching comparator 251 is inverted from “high gain” to “medium gain”. As a result, the switch SW1 is turned on, and the gains of the first and second transimpedance amplifier core circuits 210 and 220 become “medium gain”, and the comparison input voltage Vc decreases. Further, the switch SWc is turned off, the filter circuit 223A is disconnected, and the frequency characteristics of the second transimpedance amplifier core circuit 220 are not reduced.

  Thereafter, when the input current Iin increases and the comparison input voltage Vc reaches the voltage detection level Vh again at time T13, the gain switching signal SEL2 from the gain switching comparator 252 is inverted from “medium gain” to “low gain”. . Thereby, the switch SW2 is turned on, and the gains of the first and second transimpedance amplifier core circuits 210 and 220 become “low gain”. Further, since the switch SWc is off, the filter circuit 223A is disconnected, and the frequency characteristics of the second transimpedance amplifier core circuit 220 are not reduced.

  As described above, in this embodiment, in addition to the gain switching comparator 251 constituting the gain switching determination circuit 250 of the first embodiment described above, an equivalent gain switching comparator 252 is provided and output from the gain switching comparator 251. When the logic of the first gain switching signal SEL1 is inverted, the switch 253 is operated from “off” to “on” to supply the comparison input voltage Vc to the differential input terminal of the gain switching comparator 252. Therefore, the effects of the first embodiment described above can be obtained, and the gains of the first and second transimpedance amplifier core circuits 210 and 220 can be switched in a plurality of stages.

In the present embodiment, the case of performing two-stage switching of “high gain”, “medium gain”, and “low gain” has been described as an example, but the present invention is not limited to this and is not limited to this. In such a case, the necessary number of stages of gain switching comparators may be connected in series via a switch, and on / off of the switch may be controlled by a gain switching signal output from the previous stage gain switching comparator.
In the present embodiment, the case where the same hysteresis characteristic, that is, the voltage detection level is used in each gain switching comparator has been described as an example. However, the present invention is not limited to this, and each hysteresis characteristic, that is, the voltage detection level is used. May be used.

  Further, in the present embodiment, the filter circuit is controlled only when “high gain” is selected by the gain switching circuit 222A by controlling the switch SWc of the filter circuit 223A of the transimpedance amplifier core circuit 220A by the gain switching signal SEL1. Since 223A is operated, the high frequency band of the frequency characteristics of the second transimpedance amplifier core circuit 220A can be reduced only when the gain is maximum, and the followability of the reference voltage, that is, the output voltage V2, is improved. This maintains the instantaneous response of the transimpedance amplifier.

As described above, in the dummy core that generates the reference voltage, that is, the second transimpedance amplifier core circuit 220, by adding the filter circuit 223, the high frequency band of the frequency characteristics of the dummy core is reduced, and the reference voltage, that is, the output voltage. The signal band of V2 can be reduced, and a transimpedance amplifier having low noise characteristics can be realized.
On the other hand, in the configuration in which the gains of the first and second transimpedance amplifier core circuits 210 and 220 are switched in a plurality of stages as in the present embodiment, the DC potential of the reference voltage also changes according to the gain switching.

  Therefore, when the filter circuit is always operated with such a configuration, a change occurs in the reference voltage at the time of gain switching according to the time constant of the capacitor element and the feedback resistor of the filter circuit, and the transimpedance amplifier The followability of the output voltage Vout with respect to the change of the input current Iin decreases.

  In this embodiment, since the filter circuit is set to the operating state only when the gain of the transimpedance amplifier core circuit is maximum, the capacitive element of the filter circuit is disconnected at the time of gain switching and the gain switching is performed. No delay occurs in the change of the reference voltage, the followability of the output voltage Vout with respect to the change of the input current Iin of the transimpedance amplifier is improved, and the instantaneous response of the transimpedance amplifier can be maintained.

Further, the high frequency component generated in the reference voltage due to noise is conspicuous when the gain is high. By operating the filter circuit only when the gain is maximum, low noise characteristics sufficient as a transimpedance amplifier can be obtained.
In the present embodiment, focusing on the fact that the gain switching signal SEL1 indicates “medium gain” in a state other than the case where the gain is maximum, a configuration in which the switch SWc of the filter circuit is controlled by the gain switching signal SEL1. Although described as an example, when the gain switching signal SEL1 adopts a configuration indicating “high gain” in a state other than the case where the gain is maximum, a signal indicating the case where the gain is maximum is generated from each gain switching signal by a logic circuit Then, SWc may be controlled based on the signal.

[Third Embodiment]
Next, a specific example of the transimpedance amplifier core circuit used in the transimpedance amplifier according to the third embodiment of the present invention will be described with reference to FIGS. FIG. 13 is a circuit diagram showing a configuration example of a main part of a first transimpedance amplifier core circuit used in the transimpedance amplifier according to the third embodiment of the present invention. FIG. 14 is a circuit diagram showing a configuration example of a main part of a second transimpedance amplifier core circuit used in the transimpedance amplifier according to the third embodiment of the present invention.

  The transimpedance amplifier core circuit 210B shown in FIG. 13 includes a feedback resistor RF1, which determines the transimpedance gain, as a gain switching circuit 212B that performs two-stage switching of “high gain”, “medium gain”, and “low gain”. RF2 and RF3 and load resistors RL1, RL2 and RL3 for determining an open loop gain are provided, and these feedback resistors and load resistors are switched to desired resistance values using the NMOS transistors MN1 to MN4 as switches. Note that the NMOS transistors MN1 to MN4 as switches for switching the feedback resistance and the load resistance can also be realized by PMOS transistors if the logic of the switching signal is inverted.

  On the other hand, the transimpedance amplifier core circuit 220B of FIG. 14 is provided with a filter circuit 223B including a series connection circuit of a MOS transistor MP5 corresponding to the capacitive element C and the switch SWc in addition to the configuration of FIG. The PMOS transistor MP5 as a switch for connecting / opening the capacitive element C can also be realized by an NMOS transistor if the logic of the switching signal is inverted.

  In FIGS. 13 and 14, the substrate terminals of the NMOS transistors MN1 and MN2 used for the switch for switching the feedback resistor are connected to the ground potential (GND) instead of the source, and the substrate potential is set lower than the source potential. By doing so, the depletion layer is widened, the parasitic capacitance between the drain and source of the NMOS transistor can be reduced, and the band of the transimpedance amplifier can be improved, so that high-speed operation is possible.

  This transimpedance amplifier is an optical receiver that converts an optical signal into an electrical signal in an optical transmission circuit such as an optical transmission system, an optical interconnection, a passive optical network (hereinafter referred to as a PON) system that enables high-speed data transmission. Suitable for circuit.

It is a block diagram which shows the structure of the transimpedance amplifier concerning the 1st Embodiment of this invention. FIG. 2 is a circuit diagram showing a configuration of a first transimpedance amplifier core circuit used in the transimpedance amplifier according to the first exemplary embodiment of the present invention. It is a circuit diagram which shows the structure of the 2nd transimpedance amplifier core circuit used with the transimpedance amplifier concerning the 1st Embodiment of this invention. It is an example of the signal waveform in each part of the transimpedance amplifier concerning the 1st Embodiment of this invention. It is an example of a hysteresis characteristic which a gain switching comparator has. It is an example of the operating characteristic of a gain switching comparator. 3 is a timing chart showing an operation example of the transimpedance amplifier according to the first exemplary embodiment of the present invention. It is a circuit diagram which shows the structure of the gain switching judgment circuit used with the transimpedance amplifier concerning the 2nd Embodiment of this invention. It is a circuit diagram which shows the structural example of the 1st transimpedance amplifier core circuit used with the transimpedance amplifier concerning the 2nd Embodiment of this invention. It is a circuit diagram which shows the structural example of the 2nd transimpedance amplifier core circuit used with the transimpedance amplifier concerning the 2nd Embodiment of this invention. It is an example of the operating characteristic of a gain switching comparator. It is a timing chart which shows the operation example of the transimpedance amplifier concerning the 2nd Embodiment of this invention. It is a circuit diagram which shows the principal part structural example of the 1st transimpedance amplifier core circuit used with the transimpedance amplifier concerning the 3rd Embodiment of this invention. It is a circuit diagram which shows the principal part structural example of the 2nd transimpedance amplifier core circuit used with the transimpedance amplifier concerning the 3rd Embodiment of this invention. It is a circuit diagram of the conventional transimpedance amplifier. It is a circuit diagram of the transimpedance amplifier of another example conventionally. It is a structural example of a general PON system. It is a structural example of a packet transmitted as upstream data of a general PON system. It is a circuit diagram which shows the structural example of the holding circuit used with the conventional transimpedance amplifier.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 ... Light receiving element, 200 ... Transimpedance amplifier, 210, 210A, 210B ... 1st transimpedance amplifier core circuit, 211 ... Amplifier circuit, 212, 212A, 212B ... Gain switching circuit, 220, 220A, 220B ... 2nd Transimpedance amplifier core circuit, 221... Amplifier circuit, 222, 222A, 222B ... Gain switching circuit, 223, 223A, 223B ... Filter circuit, 230 ... Intermediate stage buffer circuit, 240 ... Output buffer circuit, 250, 250A ... Gain switching judgment Circuits 251, 252 ... Gain switching comparators, 253 ... Switches, 501 ... Station side equipment (OLT), 502 ... Optical coupler, 503 ... Optical fiber, 511-51n ... Home side equipment (ONU), 521-52n ... Packets, Iin: Input current, V1, V2 ... Output voltage (non-inverted output), V4 ... output voltage (inverted output), Vc ... comparison input voltage, Vh ... voltage detection level, SEL, SEL1, SEL2 ... gain switching signal, Vout ... output voltage, Voutp ... output voltage (non-inverted output), Voutn ... output voltage (inverted output).

Claims (8)

A first transimpedance amplifier core circuit that amplifies the current input to the input terminal with a desired gain and outputs it as a voltage signal;
A second transimpedance amplifier core circuit having the same configuration as the first transimpedance amplifier core circuit and having an input terminal opened;
An intermediate buffer circuit that differentially amplifies and outputs the output signals from the first and second transimpedance amplifier core circuits;
The differential output signal output from the intermediate stage buffer circuit is used as a comparison input voltage, and the gains of the first and second transimpedance amplifier core circuits are based on the result of comparing and determining the comparison input voltage with the first hysteresis characteristic. A gain switching determination circuit that outputs a gain switching signal for switching
The first transimpedance amplifier core circuit includes a gain switching circuit that switches a gain based on the gain switching signal;
The second transimpedance amplifier core circuit includes a gain switching circuit that switches a gain based on the gain switching signal, and a filter circuit that attenuates a high-frequency component of a voltage signal output from the second transimpedance amplifier core circuit. Transimpedance amplifier characterized by that. The transimpedance amplifier according to claim 1,
The transimpedance amplifier, wherein the filter circuit includes a capacitive element. The transimpedance amplifier according to claim 1,
The first transimpedance amplifier core circuit includes an amplifier circuit that amplifies a current input to a signal input terminal connected to the input terminal with a gain determined by a feedback resistance value and outputs the current signal as a voltage signal from a signal output terminal. ,
The gain switching circuit is connected between a signal input terminal and a signal output terminal of the amplifier circuit, and switches the feedback resistance value based on the gain switching signal.
The transimpedance amplifier, wherein the filter circuit includes a capacitive element connected between a signal input terminal and a signal output terminal of the amplifier circuit. The transimpedance amplifier according to claim 1,
The first transimpedance amplifier core circuit includes an amplifier circuit that amplifies a current input to a signal input terminal connected to the input terminal with a gain determined by a feedback resistance value and outputs the current signal as a voltage signal from a signal output terminal. ,
The gain switching circuit is connected between a signal input terminal and a signal output terminal of the amplifier circuit, and switches the feedback resistance value based on the gain switching signal.
The transimpedance amplifier, wherein the filter circuit includes a capacitive element connected between a signal input terminal of the amplifier circuit and a predetermined power supply potential. The transimpedance amplifier according to claim 1,
The first transimpedance amplifier core circuit includes an amplifier circuit that amplifies a current input to a signal input terminal connected to the input terminal with a gain determined by a feedback resistance value and outputs the current signal as a voltage signal from a signal output terminal. ,
The gain switching circuit is connected between a signal input terminal and a signal output terminal of the amplifier circuit, and switches the feedback resistance value based on the gain switching signal.
The transimpedance amplifier, wherein the filter circuit includes a capacitive element connected between a signal output terminal of the amplifier circuit and a predetermined power supply potential. In the transimpedance amplifier according to any one of claims 2 to 5,
The transimpedance amplifier, wherein the filter circuit includes a switch that disconnects at least one connection terminal of the capacitive element based on the gain switching signal. The transimpedance amplifier according to claim 6,
The transimpedance amplifier, wherein the switch conducts in a state where the gain switching circuit selects the highest gain. The transimpedance amplifier according to claim 6 or 7,
The transimpedance amplifier, wherein the switch is made of a MOS transistor.

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