JP2006303843A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device with a power MOSFET having a switch control by a signal source having only a small current capacity and a protective function. <P>SOLUTION: A drain is connected at a first terminal, a source for the power MOSFET is connected at a second terminal and a high resistance means is connected between a third terminal and a gate for the power MOSFET. A current limiting circuit limiting a current flowing through the power MOSFET by receiving an output signal from a current detecting means detecting the current flowing through the power MOSFET is fitted between the gate for the power MOSFET and the second terminal. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a technique effective when applied to a semiconductor device as switch means that can be replaced by a relay switch.

As an example of a solid state relay that can be replaced with a relay switch, there is JP-A-10-173505. In this solid state relay, a light emitting diode and a phototransistor constituting a photocoupler and a bipolar transistor driven thereby are used as switches.
JP-A-10-173505

  When the bipolar transistor as described above is used as a switch, there is a problem that the amount of current that can be passed is relatively small and the use as a current switch path is limited. Therefore, it is conceivable to replace the vertical power MOSFET capable of flowing a larger amount of current with a bipolar transistor. That is, a photocap is formed by photoelectric conversion elements such as a light emitting diode and a photodiode, and the vertical power switch MOSFET is driven by the output voltage of the photocoupler.

  Thus, when the vertical power MOSFET is used as a switch, it is necessary to provide a protection circuit for preventing element destruction due to load overcurrent. The voltage supplied from the photodiode is as large as about 10 V, and a voltage sufficient to drive a MOSFET with a high input impedance can be obtained. However, the current formed by the photocoupler is as small as about 500 nA. For this reason, when a general protection circuit that allows a current of several uA (microamperes) to flow is provided, the voltage generated by the photocoupler cannot drive not only the protection circuit but also the MOSFET. did.

  An object of the present invention is to provide a semiconductor device having a switch control and protection function with a signal source having only a small current capability. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The outline of a typical invention among the inventions disclosed in the present application will be briefly described as follows. That is, a drain is connected to the first terminal, a source of the power MOSFET is connected to the second terminal, and a high resistance means is connected between the third terminal and the gate of the power MOSFET. A current limiting circuit is provided between the gate of the power MOSFET and the second terminal for receiving the output signal of the current detecting means for detecting the current flowing in the power MOSFET and limiting the current flowing in the power MOSFET.

  Since the current to the current limiting circuit can be limited by the high resistance means, the output current required for the signal source that forms the input voltage supplied to the third terminal can be reduced.

  FIG. 1 shows a circuit diagram of an embodiment of a semiconductor relay according to the present invention. Each circuit element in the figure is formed on a semiconductor substrate such as a silicon substrate by a known semiconductor manufacturing technique. The semiconductor relay of this embodiment has a vertical power MOSFET Mo as a switch, a first terminal D connected to its drain, and a second terminal S connected to its source. The gate is connected to the third terminal G through the high resistance means R1.

  In this embodiment, in order to detect a current flowing through the power MOSFET Mo, a detection MOSFET Ms having a drain and a gate connected to the MOSFET Mo is provided. A resistance element Rs is provided between the source of the MOSFET Ms and the second terminal S. A drain-source path of a limiting MOSFET M1 that limits overcurrent is connected between the gate and source of the power MOSFET Mo. The gate of the limiting MOSFET M1 is connected to the connection point between the detection MOSFET Ms and the resistor Rs. The limiting MOSFET M1 constitutes an overcurrent limiting circuit together with the high resistance R1.

  Although not particularly limited, the MOSFETs Mo, Ms, and M1 are composed of n-channel vertical MOSFETs. The MOSFETs Mo and Ms are set to a size ratio such as 1000: 1, for example, and a small current such as about 1/1000 of the current flowing through the power MOSFET Mo corresponding to the size ratio 1000: 1. The current flows through the detection MOSFET Ms. The limiting MOSFET M1 is formed of an n-channel lateral MOSFE from the MOSFETs Mo and Ms because it is necessary to electrically isolate the drain.

  The resistor R1 is connected to a high resistance value corresponding to a current of about 500 nA supplied from a photodiode constituting a photocoupler as a signal source connected to the third terminal G, for example. Although not particularly limited, the resistance is set to about 50 MΩ (only 200 nA flows even at 10 V). By inserting the resistor R1 having such a high resistance value into the third terminal G that is the control terminal, the current flowing from the third terminal that is the control terminal is limited, and the power MOSFET Mo can be controlled. The current flowing in the power MOSFET Mo is monitored by the detection MOSFET Mo and converted into a voltage signal by the resistor Rs. Judgment is made based on this voltage signal and the threshold voltage of the MOSFET M1, and when the voltage signal becomes equal to or higher than the threshold voltage, the MOSFET M1 is turned on and a current flows between the drain and source, thereby causing the gate voltages of the MOSFETs Mo and Ms. To limit the current.

  FIG. 2 shows a circuit diagram of another embodiment of the semiconductor relay according to the present invention. In this embodiment, the resistor R1 is replaced with a diode D. For example, if the resistor R1 having a resistance value of about 50 MΩ is configured using a polysilicon layer such as a sheet resistance of 10 KΩ, a relatively large occupation area is required and the chip size of the semiconductor device is increased. Therefore, in this embodiment, the reverse leakage resistance of the diode D is used. When such a diode D is used, the element size can be significantly reduced as compared with the case where the polysilicon resistance element is used.

  FIG. 3 shows a circuit diagram of a further embodiment of the semiconductor relay according to the present invention. In this embodiment, a timer function is added to prevent the overcurrent limiting circuit from malfunctioning due to a surge or the like. In this embodiment, the third terminal G is directly connected to the gates of MOSFETs Mo and Ms similar to those described above. An overcurrent limiting circuit having a timer function is provided between the third terminal G and the second terminal S. Also in this embodiment, as described above, the power MOSFET Mo and the detection MOSFET Ms are configured by vertical MOSFETs, and the MOSFETs M1 to M3 are configured by horizontal MOSFETs.

  Between the third terminal G and the second terminal S, the same resistor R1 and MOSFET M1 are provided. The gate of the MOSFET M1 is connected to the connection point between the MOSFET Ms and the resistor Rs as described above. The drain of MOSFET M1 is connected to the gate of MOSFET M2. A high resistance R2 similar to that described above is provided between the drain of the MOSFET M2 and the third terminal G. A capacitor C is provided between the drain of the MOSFET M2 and the second terminal S. The voltage of the capacitor C is supplied to the gate of the MOSFET M3. The drain and source of the MOSFET M3 are connected to the third terminal G and the second terminal S, respectively, for current limitation of the power MOSFET Mo and the detection MOSFET Ms.

  In this embodiment, if the power MOSFET Mo is on and no excess current flows, the MOSFET M1 is off. When the MOSFET M1 is turned off, the MOSFET M2 is turned on to short-circuit both ends of the capacitor C. As a result, the MOSFET M3 is turned off. At this time, the current flowing from the third terminal G is limited by the resistors R1 and R2. For example, a current of about 500 nA supplied from a photodiode constituting a photocoupler that is a signal source connected to the third terminal G raises the gate voltage of the MOSFET M2 through the resistor R1, and the MOSFET M2 is turned on. The current flowing through the MOSFET M2 is limited by the resistor R2. Therefore, in the state where 10V is supplied to the third terminal G, current flows through the resistors R1 and R2 in a complementary manner as described above. Even if a current of 200 nA flows through the resistor R1 or R2, The remaining 300 nA is used to maintain the gate voltages of MOSFETMo and Ms at 10V.

  When the power MOSFET Mo is turned on by the control voltage from the third terminal G, the MOSFET M1 is turned on if an overcurrent temporarily flows when the MOSFET Mo is turned on. The MOSFET M2 is turned off by the on state of the MOSFET M1. Therefore, the charging operation of the capacitor C is started through the resistor R2. When this charging operation continues and reaches the threshold voltage of the MOSFET M3, the MOSFET M3 is turned on to start the current limiting operation of the MOSFETs Mo and Ms.

  However, if the overcurrent of the MOSFETMo returns to a normal value before the charging voltage of the capacitor C reaches the threshold voltage of the MOSFETM3, the MOSFETM1 is turned off. As the MOSFET M1 is turned off, the MOSFET M2 is turned on as described above, and the capacitor C is discharged. Thereby, the MOSFET M3 is maintained in the off state. Therefore, the timer function of the overcurrent limiting circuit prevents the current limiting function from responding to a temporary excess current when the power MOSFET Mo is turned on.

  FIG. 4 shows a circuit diagram of a further embodiment of the semiconductor relay according to the present invention. In this embodiment, the resistors R1 and R2 are replaced with diodes D1 and D2 similar to those in the embodiment of FIG. In this embodiment as well, a timer function is added in order to prevent malfunction of the overcurrent limiting circuit against surges and the like as described above. Compared to the case where polysilicon resistors are used as the resistors R1 and R2 as shown in FIG. 3, the device size can be significantly reduced by using the diodes D1 and D2.

  FIG. 5 shows a schematic chip layout diagram of one embodiment of the semiconductor relay of FIG. The semiconductor relay of this embodiment includes a power MOSFET Mo, detection MOSFET Ms, MOSFETs M1 to M3, diodes D1 and D2, and a resistor Rs and a capacitor C corresponding to the embodiment of FIG. The power MOSFET Mo is formed so as to occupy most of the right side of the semiconductor chip. The power MOSFET Mo is formed so as to occupy most of the right side of the semiconductor chip, and is provided with a source electrode. The remaining circuit elements are arranged on the left side of the semiconductor chip.

  Although a detailed connection relationship of wiring is omitted in the figure, a gate pad (third terminal) connected to the gate electrodes of the power MOSFET Mo and the detection MOSFET Ms is provided on the left side of the semiconductor chip. A wiring connected to one end of the diodes D1 and D2 extends from the gate pad. One end of the diodes D1 and D2 is provided with a wiring connected to the drains of the MOSFETs M1 and M2. The other end of the diode D1 is provided with a wiring connected to the gate of the MOSFET M2 on the other side. The other end side of the diode D2 is provided with a wiring connected to the gate of the MOSFET M3 on the other side. A wiring connected to the drain of the MOSFET M3 is provided from the gate pad.

  The detection MOSFET Ms is provided in a small area adjacent to the power MOSFET Mo, and a source electrode is provided on the surface thereof. A wiring extending from the source electrode to the detection resistor Rs is provided. The capacitor C is provided adjacent to the resistor Rs. This capacitor is provided with a wiring extending to the gate of the MOSFET M3 by a wiring. The source electrode of the MOSFETMo, the source electrodes of the MOSFETs M1 to M3, and the surface of the capacitor are connected to the second terminal (S).

  FIG. 6 shows a block diagram of an embodiment of the diode shown in FIG. In the diode pattern shown in FIG. 5A, a cathode electrode connected to a wiring extending from a gate pad (not shown) is provided in the central portion as in the pattern of FIG. 5, and the wiring extending from the bottom so as to sandwich the cathode electrode is provided. An anode electrode connected to is provided.

  As shown in FIG. 6B, in the diode, the p-type polysilicon layer poly-Si (p) is provided on both sides of the n-type polysilicon layer poly-Si (n). A wiring layer constituting the cathode electrode is provided on the surfaces of the n-type polysilicon layer poly-Si (n) and the p-type polysilicon layer poly-Si (p) provided on both sides thereof. The polysilicon layer poly-Si (n) and the polysilicon layer poly-Si (p) are formed on the first layer silicon oxide film SiO2 formed on the substrate, and the wiring layer on the surface thereof is formed. A second layer silicon oxide film SiO2 is formed except for the contact portion to be formed.

  FIG. 7 shows a current characteristic diagram of the diode shown in FIG. FIG. 8 shows a resistance conversion characteristic diagram of the diode shown in FIG. A resistance value of about 50 MΩ can be obtained when the both-end voltage VR is about 4V. As described above, the photodiode can obtain a voltage output of about 10 V at the maximum. However, about 4 to 5 V is sufficient to turn on the power MOSFETs Mo and Ms. Therefore, as a semiconductor relay, there is no problem if the operation of the current limiting circuit and the switch control of the power MOSFET Mo can be performed when the input voltage is about 4,5V.

  FIG. 9 shows an equivalent circuit diagram of a measurement circuit using the semiconductor relay according to the present invention. The semiconductor relay of this embodiment includes a power detection circuit IS and MOSFETs M1 to M3, diodes D1 and D2, and a capacitor C, each of which includes a power MOSFET Mo, the detection MOSFET Ms, the detection MOSFET Ms, and a resistor Rs similar to the embodiment of FIG. It is comprised from the current limiting circuit CNT which consists of. The diodes D1 and D2 are exemplarily shown as a diode D. A photodiode PV is connected between the third terminal G and the second terminal S, and a light emitting diode LED is incorporated therein to constitute a photocoupler, which serves as an input signal source for such a semiconductor relay. A load resistor RL is provided at the drain of the MOSFET Mo, and the power supply voltage VD is supplied. The source which is the second terminal is supplied with the ground potential GND. Although not particularly limited, the load resistance RL is, for example, a lamp for an automobile or the like.

  FIG. 10 is a waveform diagram of the measurement circuit. When the input voltage Vin rises by the input signal source by the photocoupler, the power MOSFET Mo is turned on. As a result, the resistance value of the lamp, which is the load resistance RL, becomes a low resistance due to the low temperature of the filament, and a current IC that can be regarded as an overcurrent flows. Corresponding to such an overcurrent, the source and drain voltages of the MOSFET Mo drop greatly. In this embodiment, since the timer function as described above is provided, the current limiting function does not work. The large current as described above causes the temperature of the filament of the lamp to rise rapidly and its resistance value increases. As a result, the current flowing through the MOSFETMo decreases to the vicinity of the suppression current corresponding to the change of the filament to a large resistance value. If an overcurrent due to a load short circuit or the like continues to flow for a time longer than the time set for the timer function, the current limiting function by the MOSFET M3 is activated, and the above-described overcurrent continues to flow. Prevent the destruction of.

  FIG. 11 is a block diagram showing an embodiment of an automotive lamp circuit using a semiconductor relay according to the present invention. The vehicle battery voltage 12V is applied to the first terminal (D) of the semiconductor relay. A lamp LP as a load is provided between the second terminal (S) and the ground potential (automobile chassis) GND. The third terminal (G) and the second terminal (S) are connected to the photocoupler including the light emitting diode LED and the photodiode PV as described above. In a lamp circuit for an automobile, a high-side driver in which the power switch is provided on the power source side causes a disadvantage that the lamp is damaged due to an accident or the like and the chassis and the battery are directly connected to each other and an excessive current flows. Have been to avoid.

  FIG. 12 is a block diagram showing another embodiment of the semiconductor relay according to the present invention. In this embodiment, two semiconductor relays are combined so that current flows in both directions at both ends of the switch. That is, the first semiconductor relay RLY1 having the first terminal (D), the second terminal (S), and the third terminal (G), the first terminal (D ′), the second terminal (S ′), and the third terminal. The second semiconductor relay RLY2 having (G ′) is connected as follows. The third terminals (G and G ′) are commonly connected, and the second terminals (S and S ′) are commonly connected. Then, the third terminal (G, G ') and the second terminal (S and S') are connected to a photocoupler including a photodiode as exemplarily shown above to perform switch control. Thereby, the current I from the terminal D to the terminal D ′ and the current I ′ from the terminal D ′ to the terminal D can be made to flow using the parasitic diodes Di and Di ′ of the power MOSFETs Mo and Mo ′.

  FIG. 13 is a plan view showing an example of a power MOSFET according to another embodiment of the present invention, and FIG. 14 is a cross-sectional view showing the cross section of the power MOSFET of FIG. The power MOSFET has a cell region 1A and a peripheral circuit region 1B on a semiconductor substrate 1. A power MOSFET Mo is formed in the cell region 1A. In the peripheral circuit region 1B, the gate pad G is exemplarily shown as a representative, and in addition, the detection MOSFET Ms as shown in FIG. 5 is formed. A source pad S is formed at the center of the source electrode 10. An inner lead such as a gold wire is connected to the gate pad G and the source pad S, and is connected to an outer lead outside the package of the semiconductor device.

An n ⁻ type epitaxial layer 2 is formed on the main surface of the semiconductor substrate 1. Although not shown, a drain electrode D is formed on the back side of the semiconductor substrate 1 and is electrically connected to the n ⁻ type epitaxial layer 2 through the n ⁺ type region. A thick field insulating film 3 made of a silicon oxide film is formed on the main surface of the semiconductor substrate 1, that is, the main surface of the n ⁻ -type epitaxial layer 2. The field insulating film 3 is formed by, for example, a LOCSO (Local Oxidation of Silicon) method. A p ⁺ type well region 4 is formed below the field insulating film 3. Although the field insulating film 3 by the LOCSO method is illustrated in the present embodiment, an element isolation structure in which a silicon oxide film is embedded in a trench (groove) such as a shallow groove or a U groove may be used.

The main surface of the n ⁻ -type epitaxial layer 2 where the field insulating film 3 is not formed functions as an active region of the power MOSFET, and active elements of the vertical power MOSFET Mo (Ms) and the lateral MOSFET M1 are formed. On the other hand, in the region where the field insulating film 3 is formed, a diode D1, a resistor Rs, and the like are formed on the field insulating film 3.

  The vertical power MOSFET Mo in the cell region 1A is an n-channel double diffusion structure MOSFET. In the power MOSFET of this embodiment, hundreds of thousands of cells of MOSFETMo are formed in the cell region 1A, and a load current IL of several A or more can be controlled. However, the present invention is not limited to this, and millions of cells of transistors may be formed. In this case, the current capacity is further increased.

Cell MOSFETMo is, n ^- -type epitaxial layer gate electrode 6 formed through a gate insulating film 5 on the main surface of the 2, on both sides of the gate electrode 6 n ^- semiconductor formed on the main surface of the type epitaxial layer 2 And having a region. The semiconductor region has a double diffusion structure including an n ⁺ type semiconductor region 7 and a p-type semiconductor region 8 surrounding it. The gate insulating film 5 is a silicon oxide film, for example, and is formed by a thermal oxidation method. The gate electrode 6 is made of, for example, a polysilicon film and is formed integrally with each cell MOSFET Mo. Although not shown, the planar shape of the gate electrode 6 is a mesh type, for example, a pattern having an octagonal opening. The opening shape is not limited to an octagon but may be a polygon such as a hexagon or a round shape. The planar shape of the gate electrode 6 is not limited to the mesh type but may be a stripe type.

The n ⁺ type semiconductor region 7 functions as a source region of the cell MOSFETMo, and the p-type semiconductor region 8 functions as a channel region of the MOSFETMo. The n ⁻ type epitaxial layer 2 functions as a drain region of the MOSFET Mo. That is, the channel of the MOSFET Mo is the p-type semiconductor region 8 between the n ⁺ -type semiconductor region 7 and the n ⁻ -type epitaxial layer 2 and is formed directly under the gate electrode 6. The load current flows from the drain terminal D on the back surface of the semiconductor substrate 1 through the n ⁻ type epitaxial layer 2, the channel region of the p type semiconductor region 8, and the n ⁺ type semiconductor region 7 to the source region 7 on the surface side of the semiconductor substrate 1. Will flow.

An insulating film 9 made of, for example, a silicon oxide film is formed so as to cover the gate electrode 6 of the MOSFETMo. A source electrode 10 is formed on one surface on the insulating film 9. The source electrode 10 is formed on almost the entire surface of the cell region 1A and is common to each cell MOSFETMo. Source electrode 10 is made of, for example, an aluminum film, and is connected to n ⁺ type semiconductor region 7 and p type semiconductor region 8 through an octagonal opening of gate electrode 6. That is, the channel region of MOSFETMo is held at the source potential.

  A lead region 11 for the gate electrode 6 is formed around the cell region 1A. A gate finger 12 is connected to the extraction region 11 through an insulating film 9. The gate finger 12 is processed and formed simultaneously with the source electrode 10 and is made of, for example, an aluminum film.

  Although not shown in FIGS. 13 and 14, the detection MOSFET Ms is formed in the peripheral region 1B. The MOSFET Ms has a configuration similar to that of the MOSFET Mo and is formed for monitoring a load current flowing through the MOSFET Mo. The detection MOSFET Ms is formed at a ratio of one cell MOSFET Mo to 1000 cells, and is arranged so as to be connected in parallel to the MOSFET Mo. Although not shown in FIGS. 13 and 14, the resistor Rs is connected to the source side of the MOSFET Ms to convert the drain current of the MOSFET Ms into a voltage signal. In addition, MOSFET Ms for limiting current and diode D1 for limiting input current are formed in association with MOSFET Ms.

A MOSFET M1 and the like are formed in a region where the field insulating film 3 is not formed in the peripheral circuit region 1B. The MOSFET M1 is an n-channel lateral MOSFET, and is formed in a p ⁻ type well region 13 formed on the main surface of the n ⁻ type epitaxial layer 2. The p ⁻ type well region 13 functions as a channel region of the MOSFET M1. The p ⁻ type well region 13 is connected to the p ⁺ type well region 4 below the field insulating film 3 and is electrically connected to the p type semiconductor region 8 which is the channel region of the MOSFET Mo through the p ⁺ type well region 4. Connected.

MOSFET M1 has a gate electrode 6 formed through gate insulating film 5 on p ⁻ type well region 13, and a source region and a drain region on both sides of gate electrode 6. The gate electrode 6 of the MOSFET M1 is made of a polysilicon film like the MOSFET Mo and is covered with an insulating film 9. The source region of the MOSFET M1 includes an n ⁺ type semiconductor region 14 and a p ⁺ type semiconductor region 15 disposed at the center of the n ⁺ type semiconductor region 14. The p ⁺ type semiconductor region 15 is connected to the p ⁻ type well region 13 at the bottom surface. N ⁺ type semiconductor region 14 and p ⁺ type semiconductor region 15 are connected to source electrode 16 formed on insulating film 9. Further, the source electrode 16 is connected to the MOSFET Mo source electrode 10 through a common wiring COM as shown in FIG. 13, for example. That is, the source and channel of the MOSFET M1 are maintained at the source potential similarly to the MOSFET Mo.

The drain region of the MOSFET M1 includes an n ⁻ type semiconductor region 17 and an n ⁺ type semiconductor region 18. The n ⁻ type semiconductor region 17 is arranged closer to the channel than the n ⁺ type semiconductor region 18 and has a so-called LDD (Lightly Doped Drain) structure. The diode D1 for limiting the input current is formed on the field insulating film 3 of the peripheral circuit. The diode D1 is formed of a polysilicon film as shown in FIG. 6, and a diode is formed by, for example, a pn junction of a p-type region and an n-type region formed by an ion implantation method. The n-type terminal of the diode D1 is a card electrode. The p-type side terminal of the diode D1 is an anode electrode and is connected to the drain regions 17 and 18 of the MOSFET M1 through the wiring 20. A detection resistor Rs is also formed on the field insulating film 3 of the peripheral circuit. Although not shown in the sectional view of FIG. 14, the gate pad G is formed on the field insulating film 3. The gate pad G is formed in the same manner as the source electrodes 10 and 16, and the wirings 19, 20, and 21, and is made of, for example, an aluminum film.

  Although the invention made by the inventor has been specifically described based on the above embodiment, the present invention is not limited to the above embodiment, and various modifications can be made without departing from the scope of the invention. For example, a minute resistor may be connected to the source side of the power MOSFET Mo and used as the detection resistor Rs. The MOSFET may be a lateral MOSFET as long as a necessary current can be obtained. The input signal source connected to the third terminal may be anything as long as it has a current supply capability equivalent to that of the photocoupler using the photodiode as described above. In the embodiment of FIG. 1 or FIG. 2, the resistor R1 and the diode D may be used as an electrostatic breakdown preventing circuit for the power MOSFET. In the embodiments of FIGS. 3 and 4, an electrostatic breakdown prevention circuit is separately provided. The present invention can be widely used for a semiconductor device as a switching element such as a semiconductor relay.

It is a circuit diagram which shows one Example of the semiconductor relay which concerns on this invention. It is a circuit diagram which shows another Example of the semiconductor relay which concerns on this invention. It is a circuit diagram which shows further one Example of the semiconductor relay which concerns on this invention. It is a circuit diagram which shows further one Example of the semiconductor relay which concerns on this invention. FIG. 5 is a schematic chip layout diagram showing an embodiment of the semiconductor relay of FIG. 4. FIG. 5 is a configuration diagram illustrating an example of the diode of FIG. 4. FIG. 7 is a current characteristic diagram of the diode shown in FIG. 6. FIG. 7 is a resistance conversion characteristic diagram of the diode shown in FIG. 6. It is an equivalent circuit diagram of a measurement circuit using the semiconductor relay according to the present invention. It is a wave form diagram in the measurement circuit of FIG. It is a block diagram which shows one Example of the lamp circuit for motor vehicles using the semiconductor relay which concerns on this invention. It is a block diagram which shows another Example of the semiconductor relay which concerns on this invention. It is a top view which shows an example of power MOSFET which is other one Embodiment of this invention. It is sectional drawing which showed the cross section of the said power MOSFET of FIG. 13 in combination.

Explanation of symbols

Mo ... power MOSFET, Ms ... detection MOSFET, Rs ... detection resistance, M1-M3 ... MOSFET, R1, R2 ... high resistance, D, D1, D2 ... diode, C ... capacitor, LED ... light emitting diode, PV ... photodiode, Is ... current detection circuit, CNT ... current limiting circuit, LP ... lamp, RL ... load, RLY1, RLY2 ... semiconductor relay 1 ... semiconductor substrate, 1A ... cell region, 1B ... peripheral circuit region, 2 ... n ^- type epitaxial layer, DESCRIPTION OF SYMBOLS 3 ... Field insulating film, 4 ... p ^<+> type well region, 5 ... Gate insulating film, 6 ... Gate electrode, 7 ... N ^<+> type semiconductor region, 8 ... P type semiconductor region, 9 ... Insulating film, 10 ... Source electrode, 11 ... gate extraction region, 12 ... gate finger, 13 ... p ^- -type well region, 14 ... n ⁺ -type semiconductor region, 15 ... p ⁺ -type semiconductor region, 16 ... source electrode , 17... N ⁻ type semiconductor region, 18... N ⁺ type semiconductor region, 19.

Claims (11)

A first terminal;
A second terminal;
A third terminal;
A power MOSFET having a drain connected to the first terminal and a source connected to the second terminal;
High resistance means having one end connected to the third terminal and the other end connected to the gate of the power MOSFET;
Current detection means for detecting a current flowing in the power MOSFET;
A current limiting circuit that receives an output signal of the current detection means and limits a current flowing through the power MOSFET;
The semiconductor device according to claim 1, wherein the current limiting circuit is provided between a gate of the power MOSFET and the second terminal. In claim 1,
The high resistance means is a diode composed of a P-type polysilicon layer and an n-type polysilicon layer, the cathode electrode side being the one end and connected to the third terminal, and the anode electrode being the other end and the above-mentioned A semiconductor device connected to the gate of a power MOSFET. In claim 2,
The power MOSFET is composed of a vertical MOSFET, and is composed of a plurality of cells having a vertical MOS structure.
The current detection means is composed of a cell of the vertical MOS structure, has a device size of 1 / m of the power MOSFET, and has a detection MOSFET in which the power MOSFET and the gate and drain are connected in common, and A semiconductor device comprising a resistance element provided at the source of a detection MOSFET. In claim 3,
The semiconductor device according to claim 1, wherein the current limiting circuit comprises a limiting MOSFET that receives a voltage across the resistance element at a gate and a source, and a drain connected to the gate of the power MOSFET. In claim 4,
The semiconductor device according to claim 1, wherein both ends of a photodiode optically coupled to the light emitting diode are connected to the first terminal and the second terminal. A first terminal;
A second terminal;
A third terminal;
A power MOSFET having a drain connected to the first terminal, a source connected to the second terminal, and a gate connected to the third terminal;
Current detection means for detecting a current flowing in the power MOSFET;
High resistance means having one end connected to the third terminal;
A current limiting circuit provided between the other end of the high-resistance means and the second terminal and configured to receive an output signal of the current detection means and limit a current flowing through the power MOSFET; Semiconductor device. In claim 6,
The high resistance means is a diode composed of a p-type polysilicon layer and an n-type polysilicon layer, the cathode electrode side being one end and connected to the third terminal, and the anode electrode being the other end and the current A semiconductor device connected to a limiting circuit. In claim 7,
The power MOSFET is composed of a vertical MOSFET, and is composed of a plurality of cells having a vertical MOS structure.
The current detection means is composed of a cell of the vertical MOS structure, has a device size of 1 / m of the power MOSFET, and has a detection MOSFET in which the power MOSFET and the gate and drain are connected in common, and A semiconductor device comprising a resistance element provided at the source of a detection MOSFET. In claim 8,
The diode is composed of a first diode and a second diode,
The current limiting circuit is
A first control MOSFET that receives a voltage across the resistor element at a gate and a source, and a drain connected to the third terminal via the first diode;
A second control MOSFET having a gate connected to the drain of the first control MOSFET, a source connected to the second terminal, and a drain connected to the third terminal via the second diode;
Capacitive means provided between the drain and source of the second control MOSFET;
A semiconductor device comprising a third control MOSFET having a gate connected to the drain of the second control MOSFET, a drain connected to the third terminal, and a source connected to the second terminal. In claim 9,
The first, second, and third control MOSFETs are lateral MOSFETs. In claim 10,
The semiconductor device according to claim 1, wherein both ends of a photodiode optically coupled to the light emitting diode are connected to the first terminal and the second terminal.

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