JP2006352798A - Video signal processing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform high-performance vertical processing with a small memory capacity.
As a video signal processing device, a frame memory for storing input image data, a first memory control unit for reading image data stored in the frame memory, and the frame memory by the first memory control unit A first block memory for storing image data of a block of horizontal N pixels and vertical M pixels read out from the image data, and K pixels arranged in the vertical direction with respect to the image data stored in the first block memory. A vertical processing unit that performs vertical processing to obtain pixels, a second block memory that stores pixel data of blocks of horizontal N pixels and vertical L pixels obtained by the vertical processing unit, and storage in the second block memory The written image data is written to the frame memory, and read from the second block memory and written to the frame memory. And a second memory control unit that reads the input image data.
[Selection] Figure 1

Description

  The present invention relates to a video signal processing apparatus that processes image data that is input in the scanning order, such as a television signal.

  FIG. 9 is a block diagram illustrating a configuration example of a conventional video signal processing apparatus. This video signal processing apparatus is disclosed in Patent Document 1 below.

  Please refer to FIG. The synchronization processing unit 92 generates and outputs clocks CLK1, CLK2, and CLK3 in synchronization with the clock CK. Image data DI is input to the horizontal filter 81 in the scanning order. The horizontal filter 81 sequentially performs horizontal filtering on the image data DI according to the clock CLK1, and stores the result in the line memory 82. The memory control unit 84 reads the image data stored in the line memory 82 in accordance with the clock CLK2 and stores it in the field memory 83.

The memory control unit 84 reads out the image data stored in the field memory 83 and stores it in the line memory 85. After that, the IP conversion unit 86 performs vertical filter processing and line interpolation processing on the stored data. And stored in the line memory 87. The scanning line conversion unit 88 performs conversion processing of the number of scanning lines in the vertical direction on the image data stored in the line memory 87. In response to the result, the horizontal compression unit 89 performs a reduction process for changing the number of pixels in the horizontal direction and stores the result in the line memory 90. The horizontal enlargement unit 91 performs an enlargement process for changing the number of pixels in the horizontal direction on the image data stored in the line memory 90, and outputs the obtained result as image data DP.
JP 2001-222251 A

  However, in the configuration as shown in FIG. 9, when performing vertical processing such as IP conversion and scanning line conversion, a line memory is required to store image data for the number of lines necessary for the processing. For example, when an NTSC standard television signal is processed as image data, a memory for storing data of 720 × 8 × 2 (= 11520) bits per line is required.

  In a system that performs high-performance vertical filter processing, computation is performed using a large number of pixels in the vertical direction, and thus the number of lines used for processing is large. That is, a large-capacity line memory having a capacity of 11520 bits × (the number of lines used for processing) is required, resulting in an expensive system.

  It is an object of the present invention to provide a video signal processing apparatus that performs high-performance vertical processing with a small memory capacity.

  According to the present invention, as a video signal processing apparatus, a horizontal filter that performs horizontal filter processing using a plurality of pixels on input image data, and a processing result of the horizontal filter are stored according to a first clock. A buffer memory, a frame memory for storing the image data, and image data stored in the first buffer memory in accordance with a second clock having a frequency higher than the first clock. A first memory control unit that reads out image data stored in the frame memory in accordance with the second clock; and horizontal N pixels and vertical M pixels (read from the frame memory by the first memory control unit). A first block for storing image data of N and M in accordance with the second clock. A vertical processing unit that performs vertical processing for obtaining pixels based on K pixels (K is an integer of 2 or more) arranged in the vertical direction with respect to image data stored in the first block memory; A second block for storing pixel data of a block of horizontal N pixels and vertical L pixels (L is an integer of 2 or more having a predetermined relationship with M and K) obtained by the vertical processing unit according to the second clock. Write image data stored in the memory and the second block memory to the frame memory in accordance with the second clock, and read image data read from the second block memory and written to the frame memory And a second memory control unit.

  According to this, since the vertical processing is performed on the image data in units of blocks, the capacity of the memory can be suppressed.

  Further, in the video signal processing device, the image data read from the frame memory by the second memory control unit is stored in accordance with the second clock, and the frequency is half of the first clock. A second buffer memory that outputs in accordance with a third clock; and wherein the vertical processing unit performs a vertical filtering process for obtaining a sum of each of the K pixels arranged in the vertical direction multiplied by a predetermined coefficient. It is preferable that the processing is performed as direction processing, and the obtained processing results are thinned out every other pixel in the vertical direction and stored in the second block memory.

  According to this, since the memory used for compression encoding and the memory used for vertical processing can be integrated, it is possible to efficiently use the memory and suppress the memory capacity.

  According to the present invention, high-performance vertical processing can be performed on image data with a small memory capacity.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 is a block diagram of a video signal processing apparatus according to the first embodiment of the present invention. 1 includes a horizontal filter 12, a buffer memory 14, a frame memory 16, a first memory control unit 18, a first block memory 22, a vertical filter 24 serving as a vertical processing unit, A two-block memory 26, a second memory control unit 28, and a buffer memory 32 are provided.

  First, the image data DI is input to the horizontal filter 12 in the scanning order of the video signal. The horizontal filter 12 performs horizontal filtering using a plurality of pixels on the image data DI in accordance with a clock CLK1 that is a sampling clock of the image data DI. The filter process performed here is, for example, a 9-tap FIR filter process. Since this process is a well-known technique, its description is omitted. The horizontal filter 12 writes the image data subjected to the horizontal filter processing (hereinafter referred to as horizontal processed image data) into the buffer memory 14 in accordance with the clock CLK1.

  The buffer memory 14 is a dual port memory, and stores the horizontally processed image data according to the clock CLK1. The first memory control unit 18 reads the horizontally processed image data stored in the buffer memory 14 in accordance with the high-speed clock CLK2 having a frequency higher than that of the clock CLK1 every time a predetermined amount of data is written, and the frame memory 16 Are intermittently transferred and stored. The capacity required for the buffer memory 14 depends on the relationship between the frequency of the clock CLK1 and the frequency of the clock CLK2. Here, it is assumed that the capacity of the buffer memory 14 is, for example, the capacity of data corresponding to the number of effective pixels in one horizontal scanning period of the video signal.

  When the horizontally processed image data for one frame period of the input image data DI is transferred to the frame memory 16, the first memory control unit 18 then converts these horizontally processed image data into horizontal N pixels according to the clock CLK2. * Read out intermittently from the frame memory 16 in units of blocks of vertical M pixels (N and M are integers of 2 or more) and store them in the first block memory 22. The first block memory 22 stores the pixel data of the block of horizontal N pixels * vertical M pixels read from the frame memory 16 according to the clock CLK2. In this embodiment, it is assumed that N = 16 and M = 20.

  The vertical filter 24 is composed of a K-tap (K is an integer of 2 or more) FIR filter, and among the horizontally processed image data stored in the first block memory 22, data for K pixels arranged in the vertical direction. The vertical filter process is performed as a vertical process to obtain a vertical filter process result for one pixel (hereinafter referred to as vertical process image data). In the present embodiment, it is assumed that K = 5. The vertical filter 24 stores the obtained vertical processed image data in the second block memory 26 according to the clock CLK2. The capacity of the second block memory 26 is, for example, the data capacity of a block of horizontal 16 pixels * vertical 16 pixels.

  FIG. 2 is an explanatory diagram schematically showing processing performed by the vertical filter 24 of FIG. In FIG. 2, a pixel block (pixel block) FP1 stored in the first block memory 22 is a block of 16 horizontal pixels * 20 vertical pixels. One square of the pixel block FP1 represents one pixel.

  Since the vertical filter 24 performs 5-tap FIR filter processing, for example, in order to obtain a processing result for a pixel that is filled in the pixel block FP2, data of 5 pixels surrounded by a thick frame is used in the pixel block FP1. Is done. The pixel column FP shows such five pixels, and each is represented by Y [0, i] (i = −2, −1, 0, 1, 2).

  As shown in FIG. 2, the vertical filter 24 includes multipliers 41, 42, 43, 44, 45 and an adder 48. Multipliers 41 to 45 respectively multiply Y [0, i] and filter coefficient h [i] (i = −2, −1, 0, 1, 2), and add the obtained results to adder 48. Output to. The adder 48 adds the five multiplication results and outputs the obtained result to the second block memory 26 for storage. The second block memory 26 stores a pixel block FP2 of horizontal N pixels * vertical L pixels (L is an integer of 2 or more having a predetermined relationship with M and K). Since there is a relationship of L = M−K + 1, here, L = 16. The vertical processing image data obtained now corresponds to the filled pixels of the pixel block FP2 in FIG.

  The vertical filter 24 sequentially performs such processing on each pixel of a block of horizontal 16 pixels * vertical 16 pixels surrounded by a broken line in the pixel block FP1, and the result is used as all the pixels of the pixel block FP2. It is stored in the block memory 26. The second memory control unit 28 intermittently writes the vertically processed image data stored in the second block memory 26 to the frame memory 16 according to the clock CLK2 for each block of horizontal 16 pixels * vertical 16 pixels.

  FIG. 3 is an explanatory diagram showing pixels for one frame period divided by the pixel block FP2 stored in the second block memory 26 of FIG. FIG. 3 shows an NTSC standard television signal as an example in which the number of pixels for one frame period is horizontal 720 pixels * vertical 480 pixels. In this case, it is divided into a total of 1350 blocks of 45 horizontal blocks * 30 vertical blocks, the same processing is performed, and processing for one frame period is performed.

  When the vertically processed image data for one frame period is stored in the frame memory 16, the second memory control unit 28 reads the vertically processed image data from the frame memory 16 intermittently according to the scanning order, and the buffer memory 32. Write to. The buffer memory 32 is a dual port memory, and writing is performed according to the clock CLK2.

  The vertically processed image data stored in the buffer memory 32 is continuously read according to the clock CLK1 slower than the clock CLK2, and is output as image data DFF. The capacity required for the buffer memory 32 depends on the relationship between the frequency of the clock CLK1 and the frequency of the clock CLK2. Here, it is assumed that the capacity of the buffer memory 32 is, for example, the capacity of effective pixel data in one horizontal scanning period of the video signal.

  As described above, the video signal processing apparatus according to the first embodiment of the present invention is configured to perform vertical filter processing by dividing image data of one frame period into blocks each having 16 horizontal pixels * 20 vertical pixels. ing. Therefore, for example, when 5-tap vertical filter processing is performed, the first block memory 22 that stores a pixel block of horizontal 16 pixels * vertical 20 pixels and a pixel block of horizontal 16 pixels * vertical 16 pixels are stored. Vertical filter processing can be realized using the second block memory 26. Assuming that the data amount per pixel is 2 bytes, the memory capacity required for the vertical filter processing is (16 * 20 + 16 * 16) * 2 = 1152 bytes, so 720 * required for the conventional video signal processing apparatus. Compared with 5 * 2 = 7200 bytes, the memory capacity can be greatly reduced.

  In the present embodiment, the case where a 5-tap FIR filter is used as the vertical filter has been described as an example. However, the number of taps K of the FIR filter may be increased to perform higher-performance vertical filter processing. In this case, the number of pixels in the vertical direction of the pixel block that needs to be stored in the first block memory is increased by a maximum of K pixels. The increase in capacity required for the first block memory is 16 * K * 2 bytes, which is smaller than the increase of 720 * K * 2 bytes in the conventional example.

  Further, the second block memory 26 has been described as having a relationship of L = M−K + 1, but may be L = M−K.

(Second Embodiment)
FIG. 4 is a block diagram of a video signal processing apparatus according to the second embodiment of the present invention. 4 includes a horizontal filter 212, a buffer memory 214, a frame memory 216, a first memory control unit 218, a first block memory 222, an IP conversion unit 224 as a vertical processing unit, A second block memory 226, a second memory control unit 228, and a buffer memory 232 are provided. The horizontal filter 212 and the buffer memory 214 are the same as the horizontal filter 12 and the buffer memory 14 shown in FIG.

  The first memory control unit 218 reads the horizontally processed image data stored in the buffer memory 214 according to the clock CLK2 every time a predetermined amount of data is written, and intermittently transfers the data to the frame memory 216 for storage.

  When the horizontally processed image data for one frame period of the input image data DI is transferred to the frame memory 216, the first memory control unit 218 then converts these horizontally processed image data into horizontal N pixels according to the clock CLK2. * Intermittently read from the frame memory 216 in units of vertical M pixel blocks and stored in the first block memory 222. The first block memory 222 stores the pixel data of the block of horizontal N pixels * vertical M pixels read from the frame memory 216 according to the clock CLK2. In this embodiment, it is assumed that N = 16 and M = 12.

  The IP conversion unit 224 performs IP conversion processing that doubles the number of pixels in the vertical direction of the image and converts the interlaced image into a progressive image. At this time, the IP conversion unit 224 uses the data of K pixels (K is an integer of 2 or more) arranged in the vertical direction from the horizontally processed image data stored in the first block memory 222 to convert the interpolation image to 1 Generate pixels. In the present embodiment, it is assumed that K = 5. Hereinafter, the generated image data after the IP conversion processing is referred to as vertical processing image data.

  The IP conversion unit 224 stores the data read from the first block memory 222 and the obtained vertical processing image data in the second block memory 226 in accordance with the clock CLK2. The capacity of the second block memory 226 is, for example, the data capacity of a block of horizontal 16 pixels * vertical 16 pixels.

  FIG. 5 is an explanatory diagram schematically showing processing performed by the IP conversion unit 224 of FIG. In FIG. 5, the pixel block CP1 stored in the first block memory 222 is a block of horizontal 16 pixels * vertical 12 pixels. One square of the pixel block CP1 represents one pixel.

  The IP conversion unit 224 outputs the processing result to the second block memory 226 for storage. The second block memory 226 stores a pixel block CP2 of horizontal N pixels * vertical L pixels (L is an integer of 2 or more having a predetermined relationship with M and K). Since there is a relationship of L = 2 * (M−K + 1), L = 16 here.

  The IP conversion unit 224 outputs the pixels in the row as it is for each row of the block of horizontal 16 pixels * vertical 8 pixels surrounded by the broken line in the pixel block CP1 (pixels in the broken line of the pixel block CP2, for example, pixels And outputs the result of interpolation processing using the upper and lower rows of the block CP2 (pixels in the next row of the pixels in the broken line of the pixel block CP2, for example, hatching of the pixel block CP2) The pixel to which is applied.

  In the interpolation process, the IP conversion unit 224 performs the process using five pixels. For example, in order to obtain the interpolation process result for the pixel subjected to the hatching of the pixel block CP2, the IP block 224 Data of 5 pixels surrounded by a frame is used. The pixel column CP shows such five pixels, and each is represented by Y [0, i] (i = −2, −1, 0, 1, 2).

  As shown in FIG. 5, the IP conversion unit 224 includes multipliers 241, 242, 243, 244, 245 and an adder 248. Multipliers 241 to 245 perform multiplication of Y [0, i] and interpolation coefficient h [i] (i = −2, −1, 0, 1, 2), respectively, and add the obtained results to adder 248. Output to. The adder 248 adds the five multiplication results and outputs the obtained result to the second block memory 226 for storage.

  The IP conversion unit 224 sequentially performs the above processing for each pixel of a block of horizontal 16 pixels * vertical 8 pixels surrounded by a broken line in the pixel block CP1, and the result is set as all the pixels of the pixel block CP2. It is stored in the second block memory 226. The second memory control unit 228 intermittently writes the vertically processed image data stored in the second block memory 226 to the frame memory 216 for each block of horizontal 16 pixels * vertical 16 pixels in accordance with the clock CLK2.

  As described above, the IP conversion unit 224 relates to the block stored in the first block memory 226, and one row of pixels obtained based on the image data for one row of the block and the K pixels arranged in the vertical direction. The IP conversion processing for obtaining image data in which the image data for the corresponding minutes are alternately arranged is performed as vertical processing. When IP conversion processing is performed in the IP conversion unit 224, the number of pixels in the vertical direction is doubled.

  When the vertically processed image data for one frame period is stored in the frame memory 216, the second memory control unit 228 reads the vertically processed image data from the frame memory 216 intermittently according to the scanning order, and the buffer memory 232. Write to. The buffer memory 232 is a dual port memory, and writing is performed according to the clock CLK2.

  The vertically processed image data stored in the buffer memory 232 is continuously read according to the clock CLK3 having a frequency twice that of the clock CLK1, and is output as image data DCC. The capacity required for the buffer memory 232 depends on the relationship between the frequency of the clock CLK2 and the frequency of the clock CLK3. Here, it is assumed that the capacity of the buffer memory 232 is, for example, twice the capacity of effective pixel data in one horizontal scanning period of the video signal.

  As described above, the video signal processing apparatus according to the second embodiment of the present invention is configured to perform the IP conversion process by dividing the image data of one frame period into blocks of horizontal 16 pixels * vertical 12 pixels. ing. Therefore, for example, when performing a 5-tap IP conversion process, a first block memory 222 that stores a pixel block of horizontal 16 pixels * vertical 12 pixels and a pixel block of horizontal 16 pixels * vertical 16 pixels are stored. Processing can be realized using the second block memory 226. If the amount of data per pixel is 2 bytes, the memory capacity required for the IP conversion process is (16 * 12 + 16 * 16) * 2 = 896 bytes, so 720 * required for the conventional video signal processing apparatus. Compared with 5 * 2 = 7200 bytes, the memory capacity can be greatly reduced.

  In the present embodiment, the case of performing the 5-tap interpolation filter process during the IP conversion process has been described as an example. However, the number of interpolation filter taps K may be increased to perform higher-performance IP conversion process. Good. In this case, the number of pixels in the vertical direction of the pixel block that needs to be stored in the first block memory is increased by a maximum of K pixels. The increase in capacity required for the first block memory is 16 * K * 2 bytes, which is smaller than the increase of 720 * K * 2 bytes in the conventional example.

  Further, the second block memory 226 has been described as having a relationship of L = 2 * (M−K + 1), but may be L = 2 * (M−K).

(Third embodiment)
FIG. 6 is a block diagram of a video signal processing apparatus according to the third embodiment of the present invention. The video signal processing device of FIG. 6 includes a second memory control unit 328 and a third block memory 332 in place of the second memory control unit 28 and the buffer memory 32 in the video signal processing device of FIG. An encoding unit 334 is provided. The other components are the same as those described with reference to FIG. 1, and thus the same reference numerals are assigned and description thereof is omitted.

  When the entire vertically processed image data of the block of horizontal 16 pixels * vertical 16 pixels is stored in the second block memory 26, the second memory control unit 328 stores these data in the frame memory 16, and The compression encoding unit 334 receives these data from the second memory control unit 328. In addition, the second memory control unit 328 intermittently transfers the past vertical processing image data stored in the frame memory 16 to the third block memory 332 as reference image data for compression encoding processing.

  The compression encoding unit 334 refers to the data in the third block memory 332 and performs compression encoding processing on the block data stored in the second block memory 26 in units of the block. The compressed encoded data DFM is output. The compression encoding unit 334 performs, for example, an MPEG-2 (moving picture experts group-2) method as the compression encoding process.

  As described above, the video signal processing apparatus according to the third embodiment of the present invention divides the image data of one frame period into blocks each having 16 horizontal pixels and 20 vertical pixels, and performs vertical filter processing to generate a result. The compression encoding process is performed in units of blocks each composed of 16 horizontal pixels and 16 vertical pixels. Since the size of the pixel block obtained as a result of the vertical filter process is the same as the unit of the compression encoding process, the memory of the block unit that was originally required for the compression encoding process is reduced for the vertical filter process. It can be shared as memory. That is, the second block memory 26 can be shared by the vertical filter 24 and the compression encoding unit 334.

  Note that after the vertical filter processing, the vertical filter may thin out the processed pixels every other pixel in the vertical direction and store them in the second block memory 26. Then, compression encoding of image data down-sampled in the vertical direction like SIF (source input format) can be realized. In this case, for example, if a first block memory storing a block of horizontal 16 pixels * vertical 36 pixels and a second block memory storing a block of horizontal 16 pixels * vertical 16 pixels are used, the second block memory is used. The block memory can be shared by the vertical filter and the compression encoder.

(Fourth embodiment)
FIG. 7 is a block diagram of a video signal processing apparatus according to the fourth embodiment of the present invention. The video signal processing device of FIG. 7 includes a second memory control unit 428 and a third block memory 432 in place of the second memory control unit 228 and the buffer memory 232 in the video signal processing device of FIG. An encoding unit 434 is provided. The other components are the same as those described with reference to FIG. 4, and thus the same reference numerals are given and description thereof is omitted.

  When the entire vertically processed image data of the block of horizontal 16 pixels * vertical 16 pixels is stored in the second block memory 226, the second memory control unit 428 stores these data in the frame memory 216, and The compression encoding unit 434 receives these data from the second memory control unit 428. In addition, the second memory control unit 428 intermittently transfers the past vertically processed image data stored in the frame memory 216 to the third block memory 432 as reference image data for compression encoding processing.

  The compression encoding unit 434 refers to the data in the third block memory 432 and performs compression encoding processing on the block data stored in the second block memory 226 in units of the block. The compression encoded data DCM is output. The compression encoding unit 434 performs, for example, processing according to the MPEG-2 system as compression encoding processing.

  As described above, the video signal processing apparatus according to the fourth embodiment of the present invention divides the image data of one frame period into blocks each having 16 horizontal pixels and 12 vertical pixels, performs IP conversion processing, and generates the result. The compression encoding process is performed in units of blocks each composed of 16 horizontal pixels and 16 vertical pixels. Since the size of the pixel block obtained as a result of the IP conversion process is the same as the unit of the compression encoding process, the memory of the block unit originally required for the compression encoding process is reduced to the IP conversion process. It can be shared as memory. That is, the second block memory 226 can be shared by the IP conversion unit 224 and the compression encoding unit 434.

(Fifth embodiment)
FIG. 8 is a block diagram of a video signal processing apparatus according to the fifth embodiment of the present invention. The video signal processing device of FIG. 8 is the same as the video signal processing device of FIG. 1, except that the vertical filter 524, the second block memory 26, the second memory control unit 28, and the buffer memory 32 are replaced by a vertical filter 524, a second block memory. 526, a second memory control unit 528, and a third block memory 532, respectively. The other constituent elements are the same as those described with reference to FIG.

  The second block memory 526 stores a pixel block of horizontal N pixels * vertical L pixels (L is an integer of 2 or more having a predetermined relationship with M and K). Since there is a relationship of L = (M−K + 1) / 2, here, L = 8.

  The vertical filter 524 performs vertical filter processing in the same manner as the vertical filter 24 of FIG. 1, and the second vertical filter processing result of the obtained block of horizontal 16 pixels * vertical 16 pixels is thinned out every other pixel in the vertical direction. It is stored in the block memory 526. That is, the second block memory 526 stores a block of horizontal 16 pixels * vertical 8 pixels. The second memory control unit 528 intermittently writes the vertically processed image data stored in the second block memory 526 to the frame memory 16 for each block of 16 horizontal pixels × 8 vertical pixels in accordance with the clock CLK2.

  When the vertically processed image data for one frame period is stored in the frame memory 16, the second memory control unit 528 reads the vertically processed image data from the frame memory 16 intermittently according to the scanning order, and the buffer memory 532. Write to. The buffer memory 532 is a dual port memory, and writing is performed according to the clock CLK2.

  The vertically processed image data stored in the buffer memory 532 is continuously read out according to the clock CLK3 having a frequency half the clock CLK1, and is output as image data DFS. Image data DFS is image data obtained by down-converting input image data DI in the vertical direction.

  As described above, the video signal processing apparatus according to the fifth embodiment of the present invention divides image data of one frame period into blocks and performs vertical filter processing, and thins out the obtained results in the vertical direction. It is configured. Therefore, for example, when performing a 5-tap vertical filter process, a first block memory 22 that stores a pixel block of horizontal 16 pixels * vertical 20 pixels and a pixel block of horizontal 16 pixels * vertical 8 pixels are stored. Vertical filter processing can be realized using the second block memory 526. If the data amount per pixel is 2 bytes, the memory capacity required for the vertical filter processing is (16 * 20 + 16 * 8) * 2 = 896 bytes, so 720 * necessary for the conventional video signal processing apparatus. Compared with 5 * 2 = 7200 bytes, the memory capacity can be greatly reduced.

  The second block memory 526 has been described as having a relationship of L = (M−K + 1) / 2, but may be L = (M−K) / 2.

  In the above embodiment, the number of pixels in the horizontal direction of the pixel block stored in the first and second block memories has been described as 16 pixels. However, other numbers of pixels may be used. The smaller the number of pixels in the horizontal direction, the smaller the capacity required for the block memory.

  As described above, since the present invention can perform high-performance vertical processing with a small memory capacity, it is useful for video signal processing apparatuses and the like.

1 is a block diagram of a video signal processing apparatus according to a first embodiment of the present invention. It is explanatory drawing which shows typically the process performed with the vertical filter of FIG. FIG. 3 is an explanatory diagram showing pixels for one frame period divided by a pixel block stored in a second block memory of FIG. 1. It is a block diagram of the video signal processing apparatus which concerns on the 2nd Embodiment of this invention. It is explanatory drawing which shows typically the process performed in the IP conversion part of FIG. It is a block diagram of the video signal processing apparatus which concerns on the 3rd Embodiment of this invention. It is a block diagram of the video signal processing device concerning a 4th embodiment of the present invention. It is a block diagram of the video signal processing device concerning a 5th embodiment of the present invention. It is a block diagram which shows the structural example of the conventional video signal processing apparatus.

Explanation of symbols

12, 212 Horizontal filter 14, 32, 214, 232, 532 Buffer memory 16, 216 Frame memory 18, 218 First memory control unit 22, 222 First block memory 24, 524 Vertical filter (vertical processing unit)
26, 226, 526 Second block memory 28, 228, 328, 428, 528 Second memory control unit 224 IP conversion unit (vertical processing unit)
332, 432 Third block memory 334, 434 Compression encoding unit

Claims (13)

A horizontal filter that performs horizontal filtering using a plurality of pixels on the input image data;
A first buffer memory for storing the processing result of the horizontal filter according to a first clock;
A frame memory for storing the image data;
The image data stored in the first buffer memory is stored in the frame memory in accordance with a second clock having a frequency higher than that of the first clock, and the image data stored in the frame memory is stored in the first memory. A first memory controller that reads in accordance with two clocks;
A first block that stores image data of blocks of horizontal N pixels and vertical M pixels (N and M are integers of 2 or more) read from the frame memory by the first memory control unit according to the second clock. Memory,
A vertical processing unit that performs vertical processing for obtaining pixels based on K pixels (K is an integer of 2 or more) arranged in the vertical direction with respect to the image data stored in the first block memory;
A second pixel block that stores pixel data of a block of horizontal N pixels and vertical L pixels (L is an integer of 2 or more having a predetermined relationship with M and K) obtained by the vertical processing unit in accordance with the second clock. Block memory,
Second memory for writing image data stored in the second block memory to the frame memory according to the second clock, and reading image data read from the second block memory and written to the frame memory A video signal processing apparatus comprising a control unit. The video signal processing device according to claim 1,
A second buffer memory that stores the image data read from the frame memory by the second memory control unit according to the second clock and outputs the image data in the scanning order according to the first clock;
The vertical processing unit includes:
A video signal processing apparatus, characterized in that vertical filter processing for obtaining a sum of multiplication of a predetermined coefficient for each of the K pixels arranged in the vertical direction is performed as the vertical processing. The video signal processing device according to claim 1,
A third block memory for storing image data of a block of horizontal N pixels and vertical L pixels read from the frame memory by the second memory control unit according to the second clock;
Compression that performs compression coding processing on the image data stored in the second block memory using the image data stored in the second block memory and the image data stored in the third block memory Encoding means,
The vertical processing unit includes:
A vertical filter process for obtaining a sum of the K pixels arranged in the vertical direction multiplied by a predetermined coefficient is performed as the vertical direction process;
The second memory control unit
A video signal processing apparatus, wherein image data of a past frame is read from the frame memory and output to the third block memory. In the video signal processing device according to claim 2 or 3,
A video signal processing apparatus, wherein L = M−K + 1. In the video signal processing device according to claim 2 or 3,
A video signal processing apparatus characterized by L = M−K. The video signal processing device according to claim 1,
The image data read from the frame memory by the second memory control unit is stored according to the second clock, and is output in the scanning order according to a third clock having a frequency twice that of the first clock. Further comprising a second buffer memory
The vertical processing unit includes:
With respect to the block stored in the first block memory, image data for one row of the block and image data for one row of pixels obtained based on the K pixels arranged in the vertical direction are alternately arranged. A video signal processing apparatus characterized in that an IP conversion process for obtaining received image data is performed as the vertical direction process. The video signal processing device according to claim 1,
A third block memory for storing image data of a block of horizontal N pixels and vertical L pixels read from the frame memory by the second memory control unit according to the second clock;
Compression that performs compression coding processing on the image data stored in the second block memory using the image data stored in the second block memory and the image data stored in the third block memory Encoding means,
The vertical processing unit includes:
With respect to the block stored in the first block memory, image data for one row of the block and image data for one row of pixels obtained based on the K pixels arranged in the vertical direction are alternately arranged. IP conversion processing for obtaining the obtained image data is performed as the vertical processing,
The second memory control unit
A video signal processing apparatus, wherein image data of a past frame is read from the frame memory and output to the third block memory. The video signal processing device according to claim 6 or 7,
A video signal processing apparatus, wherein L = 2 * (M−K + 1). The video signal processing device according to claim 6 or 7,
A video signal processing apparatus characterized by L = 2 * (M−K). The video signal processing device according to claim 1,
Second image data read from the frame memory by the second memory control unit is stored according to the second clock, and is output according to a third clock whose frequency is half of the first clock. A buffer memory,
The vertical processing unit includes:
The vertical filter processing for obtaining the sum of the K pixels arranged in the vertical direction multiplied by a predetermined coefficient is performed as the vertical processing, and the obtained processing result is thinned out every other pixel in the vertical direction. The video signal processing apparatus is stored in the second block memory. The video signal processing apparatus according to claim 10, wherein
A video signal processing apparatus, wherein L = (M−K + 1) / 2. The video signal processing apparatus according to claim 10, wherein
A video signal processing apparatus, wherein L = (M−K) / 2. The video signal processing device according to claim 1,
A video signal processing apparatus, wherein N = 16.

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