JP2006352304A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit capable of surely generating a reset signal by accurately detecting malfunction of its internal circuit when a power supply voltage decreases. <P>SOLUTION: Monitor latch circuits 4a, 4b, ... have the same configuration as that of latch circuits included in a peripheral circuit. When any of latched data of the monitor latch circuits 4a, 4b, ... is inverted due to a drop of the power supply voltage VCC on the occurrence of a momentary interruption, a sub reset signal/POR2 from a malfunction detection circuit 3 is brought into an "L" level being an active level and a reset signal/POR3 from a logic circuit 2 is brought into an "L" level being an active level. Thus, the semiconductor integrated circuit can accurately detect malfunction of the peripheral circuit and surely generate the reset signal. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit including a power-on reset circuit for initializing an internal circuit when power is turned on and when a power supply voltage is lowered.

  A peripheral circuit of the semiconductor integrated circuit device includes a large number of latch circuits constituted by transistors. When the power is turned on, the operation state of the latch circuit included in the peripheral circuit is unstable. In addition, when a momentary power failure in which the power supply is momentarily stopped occurs and the data held in the latch circuit is inverted, the peripheral circuit malfunctions. For this reason, a power-on reset circuit is provided that generates a reset signal for initializing the peripheral circuit at the time of power-on and at the momentary power stop when the power supply is momentarily stopped.

  In the conventional power-on reset circuit, the power supply voltage is lowered and lower than a predetermined detection level during a period from when the power is turned on until the power supply voltage reaches a predetermined detection level, and at the momentary power failure. When this happens, a reset signal is generated.

  The detection level of the power-on reset circuit is set to a level lower than the power supply voltage lower limit value of the product standard. However, since the configuration of the peripheral circuit is different from the configuration of the power-on reset circuit, it is difficult to make the detection level of the power-on reset circuit exactly match the potential level when the peripheral circuit malfunctions. For this reason, even if the power supply potential drops during a momentary power failure and a peripheral circuit malfunctions, a reset signal is not generated if the potential during the momentary power failure is higher than the detection level.

  Patent Document 1 below discloses a power-on reset circuit that can accurately generate a reset signal even when a power supply voltage is instantaneously interrupted and recovered instantaneously. According to this, when the power supply voltage rises, a reset release signal is generated after the voltage value rises sufficiently, and when the power supply voltage falls, the output signal transitions according to the voltage transition.

Patent Document 2 below discloses a power-on reset circuit that can reliably generate a power-on reset signal when the power supply voltage once rises and then rises again. According to this, a level type function that generates a power-on reset signal / POR for a predetermined period when the power supply voltage VCC gradually increases after power-on, and a power-on reset signal for a predetermined period when the power-supply voltage VCC rapidly increases after power-on. / POR has a timer type function to be generated.
JP 2000-332586 A JP 11-86525 A

  As described above, in the conventional power-on reset circuit, a reset signal may not be generated even when the power supply potential is lowered during a momentary power failure and a peripheral circuit malfunctions. In this case, since the latch circuit included in the peripheral circuit is not initialized while holding erroneous data, the semiconductor integrated circuit cannot operate normally even if the power supply potential VCC returns to a normal level after a momentary power failure. .

  Therefore, a main object of the present invention is to provide a semiconductor integrated circuit capable of accurately detecting a malfunction of an internal circuit and reliably generating a reset signal when a power supply voltage is lowered.

  A semiconductor integrated circuit according to the present invention includes an internal circuit including a latch circuit that holds data, a power-on reset circuit that generates a reset signal for initializing the internal circuit when the power is turned on and when the power supply voltage is lowered, The power-on reset circuit includes a period from when the power is turned on until the power supply voltage reaches a predetermined value, and after the power is turned on, the power supply voltage decreases and is predetermined. The reset signal generation circuit that outputs the first sub-reset signal and the latch circuit included in the internal circuit have substantially the same configuration and are generated by the power-on reset circuit when the power is turned on. The monitor latch circuit is initialized in response to the reset signal, and the power supply voltage drops after the power is turned on so that the data held in the monitor latch circuit is A malfunction detection circuit that outputs a second sub-reset signal in the case of rotation, and a logic circuit that outputs a reset signal when receiving at least one of the first and second sub-reset signals Including.

  Preferably, the malfunction detection circuit includes a plurality of monitor latch circuits having substantially the same configuration as the latch circuit included in the internal circuit, and the data held in at least one monitor latch circuit among the plurality of monitor latch circuits is When inverted, a second sub-reset signal is generated.

  Preferably, the internal circuit includes a plurality of latch circuits having different configurations. The malfunction detection circuit includes a plurality of monitor latch circuits each corresponding to a plurality of latch circuits, and the second sub-circuit is detected when data held in at least one monitor latch circuit among the plurality of monitor latch circuits is inverted. Generate a reset signal.

  Preferably, the plurality of monitor latch circuits are arranged at different locations on the semiconductor chip.

  In the semiconductor integrated circuit according to the present invention, the power-on reset circuit is predetermined by a period from when the power is turned on until the power supply voltage reaches a predetermined value, and after the power is turned on, the power supply voltage decreases. The reset signal generation circuit that outputs the first sub-reset signal and the latch circuit included in the internal circuit have substantially the same configuration when the power is turned on, and is generated by the power-on reset circuit when the power is turned on. A malfunction detection circuit that includes a monitor latch circuit that is initialized in response to a reset signal, and that outputs a second sub-reset signal when the power supply voltage drops after the power is turned on and the data held in the monitor latch circuit is inverted; A logic circuit that outputs a reset signal when receiving at least one of the first and second sub-reset signals. Therefore, when the power supply voltage drops during an instantaneous power failure, it is possible to accurately detect a malfunction of the peripheral circuit and reliably generate a reset signal.

  FIG. 1 is a block diagram showing a schematic configuration of a power-on reset circuit according to an embodiment of the present invention. In FIG. 1, the power-on reset circuit includes a level detection type reset signal generation circuit 1, a logic circuit 2, and a malfunction detection circuit 3.

  Logic circuit 2 includes a NAND gate 11 and an inverter 12. The malfunction detection circuit 3 includes a plurality of monitor latch circuits 4 a, 4 b,..., A NAND gate 13, and an inverter 14. The monitor latch circuit 4 a is composed of NAND gates 15 and 16. The monitor latch circuit 4 b includes a NAND gate 17 and an inverter 18.

  FIG. 2 is a diagram showing the configuration of the level detection type reset signal generating circuit 1 shown in FIG. In FIG. 2, the level detection type reset signal generation circuit 1 is a reset signal generation circuit conventionally used, and includes a resistance element 21, an N channel MOS transistor 22, and an inverter 23.

  Resistance element 21 for limiting the through current is connected between power supply potential VCC line and node N11. N channel MOS transistor 22 has its gate and drain connected to node N11, and N channel MOS transistor 22 has its source connected to the line of ground potential GND. Inverter 23 inverts the logic level of the signal appearing at node N11 and outputs the inverted signal as sub-reset signal / POR1.

  FIG. 3 is a time chart for explaining the operation of the level detection type reset signal generating circuit 1 shown in FIG. 2 when the power is turned on. In FIG. 3, power supply potential VCC rises in proportion to time t from the time power is turned on at time t0, and reaches a constant level after reaching potential VCCCH at time t3.

  The potential V_N11 of the node N11 rises following the power supply potential VCC during the period from the time t0 to the time t1, and becomes a constant level after reaching the threshold value Vth_TR of the N-channel MOS transistor 22 at the time t1. The logical threshold value Vth_INV of the inverter 23 rises gently in proportion to the time t during the period from the time t0 to the time t3, and after the time t3, the power supply potential VCC is maintained at a predetermined level because it maintains the predetermined potential VCCH. Become.

  The sub-reset signal / POR1 output from the inverter 23 has an activation level “L” because the potential V_N11 of the node N11 is higher than the logic threshold value Vth_INV of the inverter 23 during the period from time t0 to time t2. To the level. Then, at time t2, in response to the potential V_N11 of the node N11 becoming lower than the logical threshold value Vth_INV of the inverter 23, it is set to the inactivation level “H” level. The potential V_N11 of the node N11 at time t2 is set to a potential Vdet (detection level). After time t2, it rises following the power supply potential VCC and reaches the potential VCCH at time t3.

  In the event of a momentary power failure in which power supply stops instantaneously after time t3, when the power supply potential VCC becomes lower than the detection level Vdet, the sub-reset signal / POR1 is set to the activation level “L” level.

  FIG. 4 is a diagram showing how the power supply potential VCC changes during an instantaneous power failure. Referring to FIG. 4, power supply potential VCC decreases from potential VCCH to potential VCCL when an instantaneous power failure occurs, and then recovers to potential VCCH immediately thereafter.

  FIG. 5 is a diagram for explaining the operation of the level detection type reset signal generating circuit 1 shown in FIG. Referring to FIG. 5, when potential VCCL at the time of instantaneous power failure becomes lower than detection level Vdet, sub-reset signal / POR1 output from level detection type reset signal generation circuit 1 has an activation level of “L”. To the level.

  In a peripheral circuit including a large number of latch circuits constituted by transistors, when the power supply potential VCC becomes lower than a predetermined level Vfal, the data held in the latch circuit is inverted and a malfunction occurs. That is, the peripheral circuit operates normally when the power supply potential VCC is in the range from the potential VCCH to the predetermined level Vfal. However, if the power supply potential VCC is lower than the predetermined level Vfal, the peripheral circuit malfunctions. In such a case, it is necessary to initialize the peripheral circuit.

  However, if the potential VCCL at the momentary power failure is lower than the predetermined level Vfal and higher than the detection level Vdet, the peripheral circuit malfunctions but the sub-reset signal / POR1 is not activated. The detection level Vdet is set to a level lower than the power supply voltage lower limit value of the product standard. However, since the configuration of the peripheral circuit is different from the configuration of the level detection type reset signal generation circuit 1, the detection level Vdet is It is difficult to exactly match the predetermined level Vfal when a malfunction occurs. Therefore, in this embodiment, as shown in FIG. 1, a logic circuit 2 and monitor latch circuits 4a, 4b,.

  Returning to FIG. 1, in the logic circuit 2, the NAND gate 11 calculates a logical product of the sub reset signal / POR 1 from the level detection type reset signal generation circuit 1 and the sub reset signal / POR 2 from the malfunction detection circuit 3. Then, a signal obtained by inverting the calculation result is output. Inverter 12 provides reset signal / POR1 obtained by inverting the output signal of NAND gate 11 to output node N1. Then, reset signal / POR1 is applied from output node N1 to the peripheral circuit.

  In the monitor latch circuit 4a of the malfunction detection circuit 3, the NAND gate 16 calculates a logical product of the output signal of the NAND gate 15 and the signal from the power supply potential VCC line, and outputs a signal obtained by inverting the calculation result. To do. The NAND gate 15 calculates a logical product of the signal from the output node N1 and the output signal of the NAND gate 16, and outputs a signal obtained by inverting the calculation result to the NAND gate 13.

  In the monitor latch circuit 4b, the inverter 18 outputs a signal obtained by inverting the output signal of the NAND gate 17. NAND gate 17 calculates the logical product of the signal from output node N1 and the output signal of inverter 18, and outputs a signal obtained by inverting the calculation result to NAND gate 13.

  The configuration of the monitor latch circuits 4a, 4b,... Is the same as that of the latch circuit included in the peripheral circuit. Corresponding to a plurality of types of latch circuits included in the peripheral circuit, the monitor latch circuits 4a, 4b,.

  The NAND gate 13 calculates the logical product of the output signals of the monitor latch circuits 4a, 4b,... And outputs a signal obtained by inverting the calculation result. Inverter 14 outputs sub-reset signal / POR2 obtained by inverting the output signal of NAND gate 13.

  FIG. 6 is a time chart for explaining the operation of the power-on reset circuit shown in FIG. In FIG. 6, during a period from when power is turned on at time t10 to time t11, the sub-reset signal / POR1 from the level detection type reset signal generation circuit 1 is set to the activation level “L”. In response, reset signal / POR3 from logic circuit 2 is set to the “L” level of the activation level. Monitor latch circuits 4a, 4b,... Are initialized by reset signal / POR3. That is, the logic level of the output signal of monitor latch circuits 4a, 4b,..., Which was in an indefinite state when the power is turned on, is fixed to the “H” level. Thereby, sub reset signal / POR2 from malfunction detection circuit 3 is fixed to the “H” level of the inactivation level.

  After power is turned on, power supply potential VCC gradually rises (not shown), and at time t11, sub-reset signal / POR1 from level detection type reset signal generation circuit 1 is at the “H” level which is an inactive level. To be. In response, reset signal / POR3 from logic circuit 2 is set to the “H” level of the inactivation level. The sub-reset signal / POR2 from the malfunction detection circuit 3 maintains the “H” level of the inactivation level.

  Next, it is assumed that an unexpected momentary power failure occurs during a period from time t12 to time t13, and the power supply potential VCC decreases to the potential VCCL. However, referring to FIG. 5, it is assumed that the potential VCCL at the momentary power failure is lower than the predetermined level Vfal and higher than the detection level Vdet. In this case, since the potential VCCL at the momentary power failure is higher than the detection level Vdet, the sub-reset signal / POR1 from the level detection type reset signal generation circuit 1 maintains the “H” level of the inactivation level. However, when the data held in any one of the monitor latch circuits 4a, 4b,... Is inverted, the output signal of the monitor latch circuit is set to “L” level, and the sub reset from the malfunction detection circuit 3 is performed. Signal / POR2 is set to the “L” level of the activation level. In response to this, the reset signal / POR3 from the logic circuit 2 is set to the “L” level of the activation level, and the peripheral circuit is initialized.

  Although not shown, when the potential VCCL at the momentary power failure is lower than the detection level Vdet, the sub-reset signal / POR1 from the level detection type reset signal generation circuit 1 is set to the activation level “L” level. In response, reset signal / POR3 from logic circuit 2 is set to the “L” level of the activation level, and the peripheral circuit is initialized.

  FIG. 7 is a diagram for explaining the operation of the power-on reset circuit shown in FIG. Referring to FIG. 7, when the potential VCCL at the momentary power failure is lower than a predetermined level Vfal and at least one holding data of the monitor latch circuits 4 a, 4 b,. The reset signal / POR3 is set to the activation level “L” level.

  A peripheral circuit including a large number of latch circuits formed of transistors malfunctions when the power supply potential VCC is lower than a predetermined level Vfal. Since the monitor latch circuits 4a, 4b,... Have the same configuration as the latch circuit included in the peripheral circuit, when the power supply potential VCC becomes lower than the predetermined level Vfal, the monitor latch circuits 4a, 4b,. Also malfunction occurs. As a result, the sub-reset signal / POR2 from the malfunction detection circuit 3 is set to the activation level “L”, and the reset signal / POR3 from the logic circuit 2 is set to the activation level “L” accordingly. The

  Therefore, potentials 0 (V) to Vfal in which the peripheral circuit malfunctions coincide with potentials 0 (V) to Vfal at which reset signal / POR3 is set to the “L” level of the activation level. As a result, when the power supply potential VCC drops during a momentary power failure, it is possible to accurately detect a malfunction of the peripheral circuit and reliably generate a reset signal.

  FIG. 8 is a diagram showing a layout of a semiconductor integrated circuit device including the power-on reset circuit shown in FIG. Referring to FIG. 7, memory arrays 34 and 35 including a plurality of memory cells arranged in a matrix are provided on semiconductor chip 31. A peripheral circuit 36 including a sense amplifier for driving memory cells is disposed between the memory arrays 34 and 35. Input / output pads 32 and 33 which are input / output interfaces with the outside are arranged above and below the memory arrays 34 and 35.

  The level detection type reset signal generation circuit 1, the logic circuit 2, and the malfunction detection circuit 3 shown in FIG. 1 are arranged between the peripheral circuit 36 and the input / output pad 33. As described above, the level detection type reset signal generation circuit 1, the logic circuit 2, and the malfunction detection circuit 3 constituting the power-on reset circuit may be arranged at one place on the semiconductor chip 31.

  FIG. 9 is a diagram illustrating a modification of FIG. Referring to FIG. 9, malfunction detection circuit 3 a is disposed between peripheral circuit 36 and input / output pad 33, and malfunction detection circuits 3 b, 3 c, 3 d, 3 e are disposed at the four corners of semiconductor chip 31. Here, the malfunction detection circuits 3a, 3b, 3c, 3d, and 3e include monitor latch circuits 4a, 4b, 4c, 4d, and 4e, respectively. However, the monitor latch circuits 4a, 4b, 4c, 4d, and 4e may have different configurations or may have the same configuration. As described above, if the plurality of monitor latch circuits 4a, 4b, 4c, 4d, and 4e for detecting malfunction are arranged at different locations, the accuracy of malfunction detection is improved.

  It is also possible to improve the accuracy of malfunction detection by varying the sizes of the transistors constituting the plurality of monitor latch circuits for malfunction detection.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

1 is a block diagram showing a schematic configuration of a power-on reset circuit according to an embodiment of the present invention. FIG. FIG. 2 is a diagram showing a configuration of a level detection type reset signal generation circuit shown in FIG. 1. 3 is a time chart for explaining the operation of the level detection type reset signal generating circuit shown in FIG. 2 when power is turned on. It is a figure which shows the mode of the change of the power supply potential VCC at the time of a momentary power failure. FIG. 3 is a diagram for explaining an operation during a momentary power failure of the level detection type reset signal generation circuit shown in FIG. 2. 3 is a time chart for explaining the operation of the power-on reset circuit shown in FIG. 1. It is a figure for demonstrating the operation | movement at the time of the momentary power failure of the power-on reset circuit shown in FIG. FIG. 2 is a diagram showing a layout of a semiconductor integrated circuit device including the power-on reset circuit shown in FIG. 1. It is a figure which shows the example of a change of FIG.

Explanation of symbols

  1 level detection type reset signal generation circuit, 2 logic circuit, 3, 3a, 3b, 3c, 3d, 3e malfunction detection circuit, 11, 13, 15, 16, 17 NAND gate, 12, 14, 18, 23 inverter, 4a 4b,... Monitor latch circuit, 21 resistance element, 22 N channel MOS transistor, 31 semiconductor chip, 32, 33 input / output pad, 34, 35 memory array, 36 peripheral circuit.

Claims (4)

A semiconductor integrated circuit comprising an internal circuit including a latch circuit that holds data, and a power-on reset circuit that generates a reset signal for initializing the internal circuit when power is turned on and when the power supply voltage drops. And
The power-on reset circuit is
The first sub-reset signal when the power supply voltage reaches a predetermined value after the power is turned on, and when the power supply voltage decreases after the power is turned on and becomes lower than the predetermined value. Reset signal generation circuit that outputs
The latch circuit includes substantially the same configuration as the latch circuit included in the internal circuit, and includes a monitor latch circuit that is initialized by receiving the reset signal generated by the power-on reset circuit when the power is turned on. A malfunction detection circuit for outputting a second sub-reset signal when the voltage drops and the data held in the monitor latch circuit is inverted; and at least one sub-reset of the first and second sub-reset signals A semiconductor integrated circuit including a logic circuit that outputs the reset signal when receiving a signal.   The malfunction detection circuit includes a plurality of monitor latch circuits having substantially the same configuration as the latch circuit included in the internal circuit, and held data of at least one monitor latch circuit among the plurality of monitor latch circuits The semiconductor integrated circuit according to claim 1, wherein the second sub-reset signal is generated when the signal is inverted. The internal circuit includes a plurality of latch circuits having different configurations from each other,
The malfunction detection circuit includes a plurality of monitor latch circuits corresponding to the plurality of latch circuits, respectively, and the data held in at least one monitor latch circuit of the plurality of monitor latch circuits is inverted. The semiconductor integrated circuit according to claim 1, wherein the second sub-reset signal is generated.   4. The semiconductor integrated circuit according to claim 2, wherein the plurality of monitor latch circuits are arranged at different locations on the semiconductor chip.

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