JP2006351779A - Memory cell and storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily perform writing and erasing processing when a memory element that stores and holds information according to the state of electric resistance is used.
SOLUTION: A variable resistance element 1, a MOS transistor 2 as a switching element for controlling a voltage applied to both ends of the variable resistance element 1, and between the variable resistance element 1 and the MOS transistor 2 (or a drain of the MOS transistor 2) And a resistive element 6 having a non-linear current-voltage characteristic connected in series. In addition, the memory device including the memory cell is configured. With this configuration, the voltage applied to the gate of the MOS transistor can be equalized during writing and reading.
[Selection] Figure 1

Description

  The present invention relates to a memory cell using a memory element that stores and holds information according to an electrical resistance state, and a memory device including the memory cell.

  In information equipment such as a computer, a high-speed and high-density DRAM is widely used as a random access memory. However, since DRAM is a volatile memory in which information disappears when the power is turned off, a nonvolatile memory in which information does not disappear is desired.

  As nonvolatile memories that are expected to be promising in the future, resistance change memories such as FeRAM (ferroelectric memory), MRAM (magnetic memory), phase change memory, PMC (Programmable Metallization Cell), and RRAM have been proposed. In the case of these memories, it is possible to keep the written information for a long time without supplying power. In addition, in the case of these memories, it is considered that by making them non-volatile, the refresh operation is unnecessary and the power consumption can be reduced accordingly.

  However, at present, FeRAM is difficult to perform non-destructive reading, and reading speed is slow because destructive reading is performed. In addition, since the number of polarization inversions by reading or recording is limited, there is a limit to the number of rewrites.

  Since the MRAM requires a magnetic field for recording, the magnetic field is generated by a current flowing through the wiring. For this reason, a large amount of current is required for recording.

  The phase change memory is a memory that performs recording by applying voltage pulses of the same polarity and different magnitudes. This phase change memory has a problem that it is sensitive to a change in environmental temperature because switching occurs depending on the temperature.

  In a resistance change type nonvolatile memory such as PMC or RRAM, a material having a characteristic in which a resistance value is changed by applying a voltage or a current is used for a storage layer for storing and holding information. Patent Document 1 discloses a configuration for storing and holding information with resistance values.

  FIG. 9 is a diagram showing a memory cell configuration example of a resistance change type memory element that has been conventionally proposed. In this example, one end of the memory element 1 as a variable resistance element is connected to the source of a MOS transistor 2 as a switching element, and the gate of the MOS transistor 2 is connected to the word line 3. The other end of the storage element 1 is connected to the source line 4. The drain of the MOS transistor 2 is connected to the bit line 5. A large number of memory cells shown in FIG. 9 are arranged in a matrix in the vertical and horizontal directions to constitute a memory device.

  FIG. 10 shows a timing chart when writing, erasing, and reading to the memory cell shown in FIG. Here, writing to the memory cell means that data “1” is written to the memory element 1, and erasing means that data “0” is written to the memory element 1. These writing, erasing and reading are executed under the control of a circuit connected to the periphery of the memory cell.

  A write cycle, an erase cycle, and a read cycle are set in order in synchronization with the clock shown in FIG. 10A, and at a timing synchronized with the write enable signal (WE signal) shown in FIG. Writing or erasing is performed. First, in the write cycle, a predetermined word line (FIG. 10 (b)) corresponding to the data “1” input in FIG. 10 (d) is applied to the cell at the address specified by the address input shown in FIG. 10 (b). f)) and a bit line (FIG. 10G) are applied with a write voltage.

  In the erase cycle, a predetermined word line (FIG. 10 (f)) corresponding to the data “0” input in FIG. 10 (d) is applied to the cell at the address specified by the address input shown in FIG. 10 (b). )) And a bit line (FIG. 10G) are applied with an erasing voltage. The voltage applied to the word line and the bit line differs between writing and erasing. The difference in the voltage between the word line waveform in FIG. 10 (f) and the bit line waveform in FIG. 10 (g) between writing and erasing indicates this voltage difference. For example, as the word line voltage, 1.5 V is applied during writing and 2.5 V is applied during erasing. The reason why the voltages are different will be described later.

In the read cycle, the precharge input shown in FIG. 10 (e) is applied to the cell at the address specified by the address input shown in FIG. 10 (b), and the word line is applied as shown in FIG. Also, a potential is applied to obtain a sense amplifier output as shown in FIG. 10 (h), and a data output shown in FIG. 10 (i) is obtained based on the output.
Special Table 2002-536840 Publication

  As shown in FIG. 10, the writing and erasing are performed at different timings in the memory cell configuration shown in FIG. 9 when the memory element 1 is programmed and erased. This is because the word line potential has to be set separately for the write operation and the erase operation due to the material characteristics of the element.

  When it is necessary to change the word line potential between the writing operation and the erasing operation in this way, writing and erasing are simultaneously performed on a plurality of memory cells arranged on the same word line, which is necessary in a multi-bit memory. It was impossible.

  Here, the necessity of changing the word line potential between the write operation and the erase operation will be described. In this type of memory cell, the resistance value of the memory element after writing is the resistance value of elements connected in series (for example, FIG. 9). In this example, the ON resistance value of the switching MOS transistor 2 is determined. In this case, when the series connection resistance value is high, the resistance value after writing of the memory element is also high, and when the series connection resistance value is low, the resistance value after writing of the memory element is also set low. Therefore, in order to set the resistance value after writing high, the word line potential as the gate voltage of the MOS transistor needs to be set low, and in order to set the resistance value after writing low, it is necessary to set the word line potential high. is there.

  On the other hand, in the erase operation mechanism, the element temperature rises due to the Joule heat generated by the current flowing through the memory element, Cu atoms in the insulating film that is the source of the electric conduction function are ionized, and the electric field moves from the insulating film to the outside As a result, the resistance of the memory element is increased. In this case, the higher the voltage applied across the storage element, the faster and more stably the erase operation is performed. For this purpose, it is desirable to set the resistance value of the memory element after writing high (for example, 10 kΩ to 20 kΩ), and the ON resistance value of the MOS transistors connected in series at the time of erasing is low.

  Thus, in order to perform writing and erasing operations at high speed and stably, it is necessary to set the word line potential as the gate voltage of the MOS transistor low during the writing operation, while setting the word line potential high during the erasing operation. It is.

  By the way, when a multi-bit memory is configured, disposing a plurality of memory cells that are accessed simultaneously on the same word line reduces the chip size and provides excellent electrical performance (high speed and low power consumption). It is important to show it. However, when a conventional memory cell is used, it is necessary to set the word line potential to different values for writing and erasing, so that writing and erasing are simultaneously performed on a plurality of memory cells arranged on the same word line. However, there is a problem that writing and erasing are inefficient. In addition, since it is necessary to change the word line potential between the write timing and the read timing, there is a problem that the voltage application configuration of the drive unit that applies the potential to the word line becomes complicated.

  An object of the present invention is to make it easy to perform writing and erasing when a storage element that stores and holds information according to the state of electrical resistance is used.

  The present invention provides a variable resistance element, a MOS transistor as a switching element for controlling a voltage applied to both ends of the variable resistance element, and a nonlinear current-voltage characteristic connected in series between the variable resistance element and the MOS transistor. The memory cell includes a resistive element having the same. In addition, the memory device includes the memory cell.

  With this configuration, at the time of writing, the resistance value of the resistance element having nonlinear current-voltage characteristics is added in series to the variable resistance element. At the time of erasing, the resistance value of the resistance element becomes low due to the non-linear current-voltage characteristics, and the resistance element is almost not connected to the variable resistance element. Since the two states can be set, the voltage applied to the gate of the MOS transistor can be equalized during writing and erasing.

  According to the present invention, it is possible to set the same word line potential during a write operation and an erase operation, and a multi-bit having a small chip size and excellent electrical performance (high speed and low power consumption) A memory having a configuration can be realized.

  Hereinafter, a first embodiment of the present invention will be described with reference to FIGS. In this example, the present invention is applied to a memory cell using a resistance change type storage element that stores and holds information according to the state of electrical resistance.

  FIG. 1 is a diagram showing a memory cell configuration example of a resistance change type memory element. In this example, one end of the memory element 1 as a variable resistance element is connected to the source of a MOS transistor 2 as a switching element via a diode 6, and the gate of the MOS transistor 2 is connected to the word line 3. is there. The diode 6 has an anode connected to the source of the MOS transistor 2 and a cathode connected to one end of the memory element 1. The other end of the storage element 1 is connected to the source line 4. The drain of the MOS transistor 2 is connected to the bit line 5.

  The diode 6 is provided as an element for controlling the write resistance, and functions as a resistance element having nonlinear current-voltage characteristics. The diode 6 is used as a resistance element having a non-linear current-voltage characteristic in which the resistance value changes at the time of writing and erasing in the memory cell, that is, the polarity of the applied voltage. In the case of this example, the diode 6 is constituted by a PN junction type diode, and the reverse characteristic has a resistive leak component. During the write operation, this resistance value is added to the storage element 1 in series. On the other hand, at the time of erasing, the diode is forward-biased, so that no series resistance is added to the memory element 1.

  FIG. 2 is an example of a cross section when the memory cell having the configuration shown in FIG. 1 is configured as a semiconductor device. In this example, the diode 6 is an example using a PN junction diode. The memory element 1 is disposed between the source line 4 and the wiring material 11. The wiring material 11 is made of metal, polysilicon, silicide, or the like. This wiring material 11 is connected to a source region (N + diffusion layer) 14 on a P-type substrate 15 constituting a MOS transistor, and an N-type silicon layer 12 and a P-type silicon layer 13 are formed at the connection point. I'm allowed. The interface at the connection portion between the N-type silicon layer 12 and the P-type silicon layer 13 becomes a PN junction, and a PN junction diode that exhibits nonlinear current-voltage characteristics (rectification characteristics) is formed. This diode corresponds to the diode 6 in FIG. The N-type silicon layer 12 and the P-type silicon layer 13 are formed by a method such as selective epitaxial, for example.

  The drain region (N + diffusion layer) 16 on the P-type substrate 15 constituting the MOS transistor is connected to the bit line 5 through the wiring material 17, and the word line 3 is connected to the gate. It is arranged in.

  In the wiring configuration shown in FIG. 2, the P-type silicon layer 13 and the N + diffusion layer 14 also have a PN junction. Since both the P layer and the N layer are high-concentration impurity regions, rectification is performed. It shows ohmic resistance without showing any characteristics.

  FIG. 3 is a diagram illustrating an example of current-voltage characteristics of a PN junction diode. As shown in FIG. 3, it is a characteristic having a nonlinear current-voltage characteristic. The diode in this example is a characteristic when the voltage is a negative value. The reverse characteristic is a characteristic when the voltage is a positive value. Sometimes it does not have such a resistive leak component.

  FIG. 4 is a diagram showing an example in which a memory device is configured by arranging a large number of memory cells of this example vertically and horizontally in a matrix. A large number of memory cells including the memory element 1, the MOS transistor 2, and the diode 6 shown in FIG. 1 are arranged in a matrix in the vertical and horizontal directions, and each word line 3 is connected to the word line driving unit 21. The source line 22 is connected to the source line driving unit 22, and the bit line 5 is connected to the bit line driving unit 23. In the word line driving unit 21, a decoder for selecting a word line for writing, erasing and reading is prepared. A decoder for selecting a bit line for writing, erasing and reading is prepared in the bit line driving unit 23. Then, a signal read from the bit line selected by the decoder in the bit line driving unit 23 is supplied to the read circuit 24, and the storage information of the storage element of the selected memory cell is read.

  FIG. 5 shows a timing chart when writing, erasing, and reading to the memory cell of this example. Here, writing to the memory cell means that data “1” is written to the memory element 1, and erasing means that data “0” is written to the memory element 1.

  The write / erase cycle and the read cycle are alternately set in synchronization with the clock shown in FIG. 5A, and at a timing synchronized with the write enable signal (WE signal) shown in FIG. Writing or erasing is performed within the write / erase cycle period. First, in the write / erase cycle, a predetermined number of cells corresponding to the data “1” or “0” input in FIG. 10D is assigned to the cell at the address specified by the address input shown in FIG. A predetermined voltage pulse is applied to the word line (FIG. 5 (f)) and the bit line (FIG. 5 (g)). As a voltage pulse to be applied to the word line, for example, 2.5 V is applied in both writing and erasing. As a voltage to be applied to the bit line, a positive voltage pulse is applied when data “1” is written, and a negative voltage pulse is applied when data “0” is written (erased).

  In the read cycle, the precharge input shown in FIG. 5 (e) is applied to the cell at the address specified by the address input shown in FIG. 5 (b), and the word line is applied as shown in FIG. 5 (f). Also, a potential is applied to obtain a sense amplifier output as shown in FIG. 5 (h), and a data output shown in FIG. 5 (i) is obtained based on the output.

  As described above, according to the configuration of this example, the MOS transistor constituting the memory cell serves only as a switching function for turning on and off, and the role of resistance control after writing the memory element is played by the non-linear characteristic resistance element. It becomes. Therefore, it is possible to set the same word line potential during the write operation and the erase operation, the chip has a small chip size, and has an excellent electrical performance (high speed and low power consumption). Can be realized.

  Next, a second embodiment of the present invention will be described with reference to FIGS. The present embodiment is also applied to a memory cell using a resistance change type storage element that stores and holds information according to the state of electrical resistance. In the case of this example, the connection position of a diode as a resistance element having nonlinear current-voltage characteristics is changed.

  That is, as shown in FIG. 6, one end of the memory element 1 as the variable resistance element is connected to the source of the MOS transistor 2 as the switching element, and the gate of the MOS transistor 2 is connected to the word line 3. is there. Further, the drain of the MOS transistor 2 is connected to the bit line 5 via the diode 6. The diode 6 has an anode connected to the bit line 5 and a cathode connected to the drain of the MOS transistor 2.

  FIG. 7 is an example of a cross section when the memory cell having the configuration shown in FIG. 6 is configured as a semiconductor device. In this example, the diode 6 is an example using a PN junction diode. The memory element 1 is disposed between the source line 4 and the wiring material 11. This wiring material 11 is connected to the source region (N + diffusion layer) 14 on the P-type substrate 15 constituting the MOS transistor.

  The drain region (N + diffusion layer) 16 on the P-type substrate 15 constituting the MOS transistor is connected to the bit line 5 through the wiring material 17, and the wiring at the junction point with the N + diffusion layer 16 is connected. A P-type silicon layer 18 is provided on the material 17. The interface between the P-type silicon layer 18 and the N + diffusion layer 16 becomes a PN junction, and a PN junction diode that exhibits nonlinear current-voltage characteristics (rectification characteristics) is formed. Further, the word line 3 is arranged to be gate-connected.

  FIG. 8 is a diagram illustrating an example in which a memory device is configured by arranging a large number of memory cells of this example vertically and horizontally in a matrix. A large number of memory cells including the memory element 1, the MOS transistor 2, and the diode 6 shown in FIG. 8 are arranged in a matrix in the vertical and horizontal directions, and each word line 3 is connected to the word line driving unit 21. The source line 22 is connected to the source line driving unit 22, and the bit line 5 is connected to the bit line driving unit 23. The peripheral configuration of these memory cells is the same as that of the example of FIG. 4, and the configuration of reading with the readout circuit 24 is the same as that of FIG.

  The principle of the write, erase, and read operations according to the second embodiment is the same as that of the first embodiment already described, and has the same effect.

  In the first and second embodiments described above, an example in which a PN junction diode is used has been described. However, the nonlinear characteristic resistance element referred to in the present invention is not limited to metal. It goes without saying that the case where the same characteristics can be obtained by using other means and materials such as a Schottky junction with silicon and a transition metal oxide film is included.

  2 and 7 described in each embodiment, one end of the memory element 1 formed of a variable resistance element is connected to the source line 4, but one end of the memory element 1 is connected. It is good also as a structure connected to the cell plate electrode which connects a some cell in common.

1 is a circuit diagram showing a configuration example of a memory cell according to a first embodiment of the present invention. 1 is a cross-sectional view showing an example of a cross section of a memory cell according to a first embodiment of the present invention. It is a characteristic view which shows the example of the current voltage characteristic of a diode. It is a block diagram which shows the example of a memory | storage device by the 1st Embodiment of this invention. It is a timing chart which shows the operation example by the 1st Embodiment of this invention. FIG. 6 is a circuit diagram showing a configuration example of a memory cell according to a second embodiment of the present invention. FIG. 6 is a cross-sectional view showing an example of a cross section of a memory cell according to a second embodiment of the present invention. It is a block diagram which shows the example of a memory | storage device by the 2nd Embodiment of this invention. It is a circuit diagram which shows the structural example of the conventional memory cell. It is a timing chart which shows the example of a conventional operation | movement.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Memory element, 2 ... MOS transistor, 3 ... Word line, 4 ... Source line, 5 ... Bit line, 6 ... Diode, 21 ... Word line drive part, 22 ... Source line drive part, 23 ... Bit line drive part, 24 ... Reading circuit

Claims (7)

A variable resistance element;
A MOS transistor as a switching element for controlling a voltage applied to both ends of the variable resistance element;
A memory cell comprising: a resistance element having a nonlinear current-voltage characteristic connected in series between the variable resistance element and the MOS transistor. The memory cell of claim 1, wherein
A memory cell, wherein the resistance element having the nonlinear current-voltage characteristic is connected to a drain side of the MOS transistor instead of between the variable resistance element and the MOS transistor. The memory cell of claim 1, wherein
The memory cell, wherein the resistance element having the nonlinear current-voltage characteristic is configured by a PN junction type diode. A variable resistance element;
A MOS transistor as a switching element for controlling a voltage applied to both ends of the variable resistance element;
Memory cells configured by including a resistance element having a nonlinear current-voltage characteristic connected in series between the variable resistance element and the MOS transistor are arranged in a matrix,
A word line commonly connecting the gates of the MOS transistors;
A bit line commonly connecting the drains of the MOS transistors;
A storage device comprising: a source line commonly connecting one ends of the variable resistance elements. The storage device according to claim 4.
A resistance element having a nonlinear current-voltage characteristic in the memory cell is connected to the drain side of the MOS transistor instead of between the variable resistance element and the MOS transistor,
The memory device according to claim 1, wherein the word line is connected to a drain of the MOS transistor through a resistance element having the nonlinear current-voltage characteristic. The storage device according to claim 4.
A memory device comprising a cell plate electrode for commonly connecting one end of the variable resistance element in an upper part of the memory cell array. The storage device according to claim 4.
A first decoder for selecting the word line;
A second decoder for selecting the bit line;
A storage device comprising: a read circuit for reading storage information of a memory cell selected by the second decoder.

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