JP2006351061A - Memory circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide reliability as a whole memory when a single storage element can be switched between a multi-value mode operating at a large capacity, low reliability and low speed and a binary mode operating at a low capacity, high reliability and high speed. Increase sex.
A thin film having a plurality of resistance states, each of the resistance states having a different resistance value, and made of a first thin film material serving as a multi-value resistance memory, and using 2 ⁿ resistance states. A first memory array region composed of memory cells capable of switching between a multi-value mode operated as n bits and a binary mode operated as one bit using two resistance states, and a second thin film material were used. A highly reliable second memory array region for storing information, which is composed of memory cells operated in the binary mode, and the second memory array region is for the operation mode of the first memory array region for data storage Stores the information.
[Selection] Figure 9

Description

  The present invention relates to a memory circuit using a material whose resistance value changes as a memory element.

  In recent years, with the advancement of digital technology in electronic devices, in order to store data such as images, there has been an increasing demand for increased capacity and faster data transfer for solid-state storage elements.

In response to such a requirement, it is possible to construct a solid-state memory element using a material whose resistance value is changed by an electric pulse, such as Pr1-xCaxMnO3 (PCMO), LaSrMnO3 (LSMO), GdBaCoxOy (GBCO), etc. This is proposed in the specification of 473,332. These materials are used as nonvolatile memory elements by increasing or decreasing the resistance value depending on the polarity of the electric pulse and using the changed resistance value state for storing different numerical values.
US Pat. No. 6,204,139 US Pat. No. 6,473,332

  A memory element using a resistance change material can store multi-value information of 2 bits or more in one memory cell, so that it can meet the demand for large capacity, but the probability of error is high and the speed is high. slow. On the other hand, when operating in the binary mode, the capacity is lower than when operating in the multi-level mode, but the error probability is low and the speed is high. Depending on the characteristics required by the data handled by the memory element, one memory element can be used for multi-value mode that operates at large capacity, low reliability, and low speed and binary mode that operates at low capacity, high reliability, and high speed. In order to make this possible, an information storage memory array area comprising memory cells operated in the binary mode is provided in the memory array, and information for the operation mode of the data storage memory array area is stored in the area. Can be operated in multiple modes, but Pr1-xCaxMnO3 (PCMO), LaSrMnO3 (LSMO), GdBaCoxOy (GBCO), etc. do not have enough number of rewrites (Endurance characteristics) and store information for operation mode For use, the reliability was not sufficient.

It is a thin film having a plurality of resistance states, each resistance state having a different resistance value, and made of a first thin film material that becomes a multi-value resistance memory, and operates as n bits using 2 ⁿ resistance states A first memory array region composed of memory cells that can be switched between a multi-value mode to be operated and a binary mode to be operated as one bit by using two resistance states, and a binary mode using a second thin film material And a second memory array area having high reliability for storing information comprising memory cells to be operated, and storing information for the operation mode of the first memory array area for data storage in the second memory array area To do. For example, a ferroelectric thin film is used as the second thin film material.

  Depending on the characteristics required by the data handled by the storage element, a multi-value mode that operates at large capacity, low reliability, and low speed and a binary mode that operates at low capacity, high reliability, and high speed can be combined into one storage element ( It is possible to provide means for enabling switching by a memory cell.

  Embodiments of the present invention will be described below with reference to the drawings.

The first material used for the memory element of the present invention is, for example, an oxide CMR material having a perovskite structure, a high-temperature superconducting material, and specifically, for example, Pr1-xCaxMnO3 (PCMO), LaSrMnO3, GdBaCoxOy, or the like. FIG. 1 is a schematic view showing a resistance change material and electrodes constituting a part of the memory cell. Pr0.7Ca0.3MnO3 is formed as a variable resistance material 2 on the substrate 4 by a sol-gel method, and an upper electrode 1 and a lower electrode 3 (for example, Pt) of the variable resistance material 2 are provided. An electric pulse is applied between the electrodes to change the resistance. The magnitude of the change in electrical resistance varies depending on the voltage and width of the pulse. An electrical pulse as shown in FIG. 2 is applied between the electrodes 1 and 3. The resistance R1 of the resistance change material 2 changes from r10 → r11 → r12 → r13 by the pulses a, b, and c having the voltage vw2, and returns to r10 by the reset pulse r having the opposite polarity and the amplitude vw1 larger than vw2 (FIG. 3). The resistance values r10, r11, r12, r13 are made to correspond to 00, 01, 10, 11 respectively as binary values. In order to operate as a memory using the resistance change material 2, for example, as shown in FIG. 4, a fixed resistance portion R0 having no resistance change and a resistance portion R1 made of a resistance change material are realized in a series structure. Is possible. An electric pulse for recording shown in FIG. 2 is applied between the terminal 6 and the terminal 7 in FIG. As a result, the resistance value of the resistor R1 changes to r10, r11, r12, r13, r10 as shown in FIG. Since the resistance state having each resistance value is maintained unless a new recording pulse is applied, it operates as a nonvolatile memory element. When reading the stored state, the terminal 7 is grounded, the voltage Ecc is applied to the terminal 5, and the voltage V1 of the terminal 6 given by the following equation is read.
・ V1 = Ecc × R1 / (R0 + R1)
FIG. 5 shows the output voltage V1 of the terminal 6. In this case, four different output values v10, v11, v12, and v13 can be read as binary values as 00, 01, 10, and 11, respectively, so that the multivalue mode can be operated.

  Electric pulses a, b, and c for recording shown in FIG. 6 are applied between the terminals 6 and 7 of the memory element shown in FIG. As a result, the resistance value of the resistor R1 changes from r10 → r13 → r10 → r13 as shown in FIG. The resistance values r10 and r13 are made to correspond to binary 0 and 1. FIG. 8 shows the output voltage v1 of the terminal 6. In this case, it is possible to operate in the binary mode by reading two different output values v10 and v13 as 0 and 1 as 1 bit, respectively. Reading can be performed by using only the upper bits of the output of the multi-bit sense amplifier as a sense amplifier for the binary mode.

  When comparing the multi-value mode and the binary mode, the storage capacity is larger in the multi-value mode. As can be seen by comparing FIG. 5 and FIG. 8, the difference between r10 and r13 in the binary mode is larger than the difference between four different resistance values r10, r11, r12 and r13 in the multi-value mode. And the S / N is high, the error probability is greater in the multi-value mode. Further, when writing in the multi-value mode, as shown in FIGS. 2 and 3, in order to set the resistance value to r11, r12, r13, once set to r10 by a reset pulse, once each, 2 times Since it is necessary to add three or three times, the operation speed is slower than the binary mode in which the single pulse changes to r10 and r13.

  Usually, the binary mode is used when high speed and high data reliability are required, and the multilevel mode is used when a large capacity is required. As a means for switching between the binary mode and the multi-value mode by one type of memory cell, the memory area 8 is divided into two blocks 9 and 10 as shown in FIG. 9 and switched to the binary mode or the multi-value mode. A data storage area (first memory array area) 9 composed of possible memory arrays and an information storage area (second memory array area) 10 are configured. As the information storage area 10, a ferroelectric material perovskite material: SrBi2Ta2O9 was formed by a sol-gel method as a second material instead of the variable resistance material 2 in FIG. The storage elements in the data storage area 9 have the storage element configuration shown in FIG. 10, and the storage elements in the information storage area 10 have the storage element configuration shown in FIG. 11 or the storage element configuration shown in FIG. The number of rewrites of the memory element shown in FIG. 10 using the resistance change material is about 1E5, and the reliability is not sufficient. On the other hand, the number of rewrites of the memory element shown in FIG. 11 or FIG. 12 is 1E12 or more, and has higher reliability than that using a resistance change material. Therefore, the information storage area 10 functions due to characteristic deterioration. It can be prevented from disappearing.

A memory element using a perovskite material used as a resistance change material, such as Pr1-xCaxMnO3 (PCMO), can change its resistance value at high speed by an electric pulse, and can use a plurality of resistance values. Although it can be operated as a multi-value memory element, it has been found that when an electric pulse is repeatedly applied to an element using these materials, the characteristics deteriorate and the element does not function as a memory element. Therefore, when these materials are used for the information storage area 10 that requires the highest reliability, the entire memory may not function. Since the variable resistance material used for the region 9 and the ferroelectric material used for the region 10 have almost the same film forming process, they can be easily formed in different regions on the same substrate. In this embodiment, the resistance change material Pr0.7Ca0.3MnO3 and the ferroelectric material SrBi2Ta2O9 are formed by the sol-gel method, but can also be formed by using a thin film forming technique such as MOCVD method. Information for switching between the binary mode and the multi-value mode that need to be stored in the information storage area 10 is as follows.
(1) Flag for mode selection (2) Amplitude and width of electric pulse for recording (3) Operation mode of sense amplifier at the time of reading (4) Memory map information It is operated by providing the information storage area 10 as described above. By writing the information for the mode in the information storage area 10, it is possible to optimize the operation of the storage element according to the characteristics required by the data handled by the storage element.

  The multi-value mode shown in this embodiment is an example of 2 bits. However, when the error probability is low and the operation speed is sufficient within an allowable range, the operation can be performed with 3 bits or more. It is.

  INDUSTRIAL APPLICABILITY The present invention can be applied to a memory that can switch between a multi-value mode that operates at large capacity, low reliability, and low speed and a binary mode that operates at low capacity, high reliability, and high speed with a single storage element. .

Diagram showing variable resistance material and electrode configuration Example of electrical pulses for recording in multilevel mode Example of resistance change when operating in multi-value mode Some examples of memory cell configurations Example of output voltage for reading when operating in multi-value mode Example of electrical pulses for recording in binary mode Example of resistance change when operating in binary mode Example of output voltage for reading when operating in binary mode Schematic showing a storage element comprising an information storage area and a data storage area Examples of storage elements in the data storage area Example of storage element in information storage area Example of storage element in information storage area

Explanation of symbols

1: Upper electrode 2: Variable resistance material 3: Lower electrode 4: Substrates 5, 6, 7: Memory cell terminals 8: Memory array area 9: Data storage area 10: Information storage area

Claims (4)

A first memory array region and a second memory array region formed on the same substrate;
In the first memory array area,
A variable resistance thin film having a plurality of resistance states having different resistance values due to an electric pulse, and formed using a first thin film material that becomes a multi-value resistance memory, and n bits using 2 ⁿ resistance states A plurality of memory cells capable of switching between a multi-value mode to be operated and a binary mode to be operated using two resistance states are formed.
In the second memory array area,
A plurality of memory cells using the second thin film material are formed,
Information for an operation mode of the first memory array area is stored in the second memory array area.
A memory circuit characterized by that. In claim 1,
In the second memory array area,
Information on whether to operate the first memory array area as a binary mode or a multi-value mode is stored.
A memory circuit characterized by that. In claim 1 or 2,
The second thin film material is a ferroelectric thin film.
A memory circuit characterized by that. In any one of Claims 1-3,
In the second memory array area,
Memory map information is stored according to whether the first memory array area is operated in a binary mode or a multi-value mode.
A memory circuit characterized by that.

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