JP2006340169A - Packet communication apparatus and packet communication method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce power consumption and circuit scale by dispersing processing load while suppressing an increase in additional circuits.
An HS-DSCH reception unit 700 includes a reordering buffer 710, a load prediction unit 703 that detects a processing load of a HARQ unit 701, and a load detection unit 706 that detects a processing load of a MAC-d / RLC unit 702. The load distribution unit 705 delays data transfer from the packet buffer 110 to the MAC-d / RLC unit 702 based on the detected processing load, and performs control to distribute the load applied to the MAC-d / RLC unit 702. Do.
[Selection] Figure 6

Description

  The present invention relates to a packet communication apparatus and a packet communication method in which a buffer is prepared for order control or the like, particularly in a lower layer of a protocol stack such as HSDPA (High Speed Downlink Packet Access).

  Conventionally, in the field of wireless communication systems, a plurality of communication terminal devices share a high-speed and large-capacity downlink channel in addition to a communication method in which transmission is performed to a communication terminal device using a dedicated physical channel (DPCH). A communication method called HSDPA that performs high-speed packet transmission in the downlink is standardized.

  In wireless communication, the propagation state is extremely unstable, and the channel capacity varies greatly from moment to moment. HSDPA is a technology that improves peak throughput (Throughput) by using this and performing high-speed transmission using multi-level modulation / low coding rate when the communication condition is good.

  In such an HSDPA system, a base station apparatus transmits a signal indicating a modulation method and a coding rate of packet data that can be demodulated in a communication terminal apparatus called CQI (Channel Quality Indicator: adaptive modulation request) from the communication terminal apparatus. get. The base station apparatus that has received the CQI performs scheduling using the CQI transmitted from each communication terminal apparatus and selects an optimal modulation scheme and coding rate. The base station apparatus modulates and encodes transmission data using the selected modulation scheme, coding rate, and the like, and transmits data to each communication terminal apparatus based on the scheduling result. Thereby, in order to adaptively change the transmission rate according to the radio wave propagation environment, HSDPA can transmit a large amount of data from the base station apparatus to the communication terminal apparatus as compared with DPCH.

  Also, in this HSDPA system, the communication terminal apparatus has received a downlink packet called HS-PDSCH (High Speed Physical Downlink Shared Channel) on HS-DPCCH (Dedicated Physical Control Channel (uplink) for HS-DSCH). An ACK / NACK signal or a CQI signal indicating that is transmitted and transmitted (for example, Non-Patent Document 1). In this method, HS-DPCCH is code-multiplexed with DPCCH (Dedicated Physical Control Channel) or DPDCH (Dedicated Physical Data Channel) and transmitted.

  FIG. 10 is a diagram illustrating a protocol configuration of a user plane when HSDPA is applied. In the figure, protocols implemented in a mobile station apparatus, a base station apparatus, and a control station apparatus that controls the base station apparatus are shown.

  Of the protocols shown in FIG. 10, RLC (Radio Link Control) is a selective retransmission type retransmission control protocol described in Non-Patent Document 2, and is implemented in the mobile station apparatus and the control station apparatus. MAC-hs (Medium Access Control used for high speed) is a protocol that performs processing such as scheduling of downlink data transfer and retransmission control by HARQ (Hybrid-Automatic Repeat reQuest), and is implemented in mobile station apparatuses and base station apparatuses. The HS-DSCH FP (High Speed Downlink Shared Channel Frame Protocol) is a protocol for performing flow control between a base station apparatus and a control station apparatus, and is implemented in the base station apparatus and the control station apparatus. Transmission / reception is performed between the mobile station terminal device and the base station device via a radio section (Uu), and between the base station device and the radio network controller (RNC) via a wired section (Iub / Iur).

  FIG. 11 is a diagram illustrating a configuration of the MAC-hs portion of HSDPA, and FIG. 12 is a diagram illustrating a more detailed configuration of the MAC-hs portion.

  A signal transmitted from a base station apparatus (hereinafter referred to as a base station) is transmitted to a mobile terminal through a radio section (Uu) that is an interface between the base station and the mobile station terminal apparatus (hereinafter referred to as a mobile terminal). Is transmitted. The PHY unit performs processing such as radio reception and demodulation, and passes data to the MAC-hs unit. In the MAC-hs section, HARQ (Hybrid ARQ) processing and Reordering processing that arranges arrival packets in order are performed. Further, the MAC-d unit reconstructs the packet, passes it to RLC, which is an upper layer, and further passes to RRC. That is, in the MAC-hs section in the mobile terminal, a process of providing a buffer and rearranging so as to be safe even if the order of arrival is switched by retransmission of the packet or the like is essential.

  Here, packets that arrive in order are usually passed to the MAC-d unit, RLC, which is the upper layer immediately (TS 25.321). The size of data passed from the MAC-hs part to the upper level is variable. The size of one packet is 0 to 27952 in the specification, and changes every 2 ms. In addition, since the packet is not always sent, it changes in a so-called burst.

  If the packets do not arrive in order, the packets stay in the reordering buffer and wait until the order is aligned. In FIG. 12, in the HSDPA Reordering queue distribution, the arrival packet is temporarily stored in the Reordering buffer. The maximum waiting time is defined as one cycle of TSN (Transmission Sequence Number) or until the timer expires (TS 25.321). If this rearrangement results in the order or the maximum waiting time is exceeded, a plurality of packets staying in the reordering buffer are collectively delivered to the upper layer. In the example of FIG. 9, Packet # 1 has not arrived as shown in FIG. 9A, and when Packet # 1 arrives as shown in FIG. 9B, Packet # 1 is sent to the upper layer (here, RLC). Transfer # 7 to Packet # 1 all at once. When viewed from the upper layer (RLC), packets do not come during reordering, and a large amount of packets are sent at once after reordering is completed, which is more bursty than when packets arrive in order. .

In order to distribute and average burst loads, for example, flow control of packets in Patent Document 1 is generally used (for example, refer to Patent Document 1).
「3GPP, TS 25.213 V5.3.0 4.2.1」 「3GPP, TS 25.306 V5.5.0 5.1」 JP 2002-171572 A

  However, in such a conventional packet communication apparatus, the amount of data to be processed fluctuates greatly, so that high-speed processing is required to process the peak amount of data. For example, when the load changes in a burst manner in the MAC-d unit or RLC, when processing without delay, the peak data processing amount increases, and high processing capacity is required, which increases the circuit scale and power consumption. There is.

  On the other hand, when the processing amount is originally set to be low, packet loss occurs and throughput decreases.

  In addition, a device that performs packet flow control, such as the device described in Patent Document 1, requires a new buffer for flow control, which increases the circuit scale.

  The present invention has been made in view of the above points, and provides a packet communication device and a packet communication method capable of reducing power consumption and circuit scale by distributing processing loads while suppressing an increase in additional circuits. The purpose is to provide.

  The packet communication device of the present invention is provided with a packet data rearrangement buffer, a first processing means provided in a preceding stage of the buffer, for outputting a processing result to the buffer, and a second for processing the data output from the buffer. Processing means, load detection means for detecting the processing load of the first processing means and / or the second processing means, and when the detected processing load exceeds a predetermined allowable processing load, And a load distribution unit that delays data transfer to the second processing unit and distributes the load applied to the second processing unit.

  The packet communication device of the present invention is provided with a packet data rearrangement buffer, a first processing means provided in a preceding stage of the buffer, for outputting a processing result to the buffer, and a second for processing the data output from the buffer. Processing means, load detection means for detecting the processing load of the first processing means and / or the second processing means, and when the detected processing load exceeds a predetermined allowable processing load, And a load distribution unit that thins out data transferred to the second processing unit and distributes the load applied to the second processing unit.

  The packet communication method of the present invention includes a step of performing a first process and outputting a processing result to a packet data rearrangement buffer, a step of processing data output from the buffer, the first process and / or the A step of detecting a processing load in the second process, and a step of performing a control to delay the data transfer output from the buffer when the detected processing load exceeds a predetermined allowable processing load.

  According to the present invention, the peak processing capability of the CPU can be reduced, and the circuit scale and power consumption can be reduced. By using the existing reordering buffer, there is an effect that a new additional circuit is not required and the implementation is low cost.

  Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

(Principle explanation)
The basic concept of the present invention will be described.

  In wireless communication, the propagation state is extremely unstable, and the channel capacity varies greatly from moment to moment. HSDPA is a technology that improves peak throughput by using this and performing high-speed transmission using multi-level modulation / low coding rate when the communication condition is good. However, since the amount of data to be processed fluctuates greatly for layer 2 and above, high-speed processing is required to process the peak data amount.

  The present inventor noticed that the peak processing amount and the average processing amount are different due to the adaptive modulation of the HSDPA system, and the buffer is essential for packet rearrangement. It has been found that the processing load on the upper level can be distributed temporally by using the system. As a result, the throughput can be increased while reducing the required processing amount of layer 2 without increasing the circuit scale and without affecting the system.

  1 to 4 are diagrams showing a basic configuration of a packet communication apparatus according to the present invention.

  In FIG. 1, the packet communication device 100 includes a packet buffer 110, a first processing unit 111 in the previous stage of the buffer, a second processing unit 112 in the subsequent stage of the buffer, a load prediction unit 121 that detects the processing load of the first processing unit 111, and a detection. The load distribution unit 122 is configured to distribute the load of the packet buffer 110 in accordance with the processed processing load.

  The packet buffer 110 is a buffer for reordering processing that arranges packets in order, and is an existing memory.

  The load prediction unit 121 determines the load from the data rate transferred so far.

  The load distribution unit 122 delays the transfer when the allowable processing load is exceeded. More preferably, when the allowable processing load is exceeded, the load distribution unit 122 delays the transfer and transfers at a (constant) rate equal to or lower than the allowable processing load.

  According to this configuration, by diverting the existing buffer 110, the processing load can be distributed and the power consumption and circuit scale can be reduced without increasing the circuit scale. Further, throughput can be improved by reducing packet loss. Further, feedback information from the subsequent processing becomes unnecessary, and the power consumption and circuit scale can be further reduced.

  In FIG. 2, the packet communication device 200 includes a packet buffer 110, a first processing unit 111 in the previous stage of the buffer, a second processing unit 112 in the subsequent stage of the buffer, a load detection unit 131 that detects a processing load of the second processing unit 112, and a detection. And a load distribution unit 132 that distributes the load of the packet buffer 110 according to the processing load.

  According to this configuration, similarly to the packet communication device 100 of FIG. 1, by diverting the existing buffer 110, the processing load can be distributed and the power consumption and circuit scale can be reduced without increasing the circuit scale. Can do. Further, throughput can be improved by reducing packet loss.

  Further, since the load detection unit 131 determines the load from the load status notified from the second processing unit 112 at the latter stage of the buffer, the packet communication device 200 can perform load distribution based on more accurate processing load detection. it can. In other words, even when the subsequent processing is performing a plurality of task processing, the processing load including other processing other than data processing can be taken into consideration, so load distribution can be performed with higher accuracy and more power consumption.・ The circuit scale can be reduced.

  In FIG. 3, the packet communication device 300 includes a packet buffer 110, a first processing unit 111 in the previous stage of the buffer, a second processing unit 112 in the subsequent stage of the buffer, a load prediction unit 121 that detects the processing load of the first processing unit 111, The load detection unit 131 that detects the processing load of the two processing units 112 and the load distribution unit 142 that distributes the load of the packet buffer 110 according to the detected processing load.

  According to this configuration, the effects of both the packet communication device 100 of FIG. 1 and the packet communication device 200 of FIG. 2 can be obtained.

  In FIG. 4, the packet communication apparatus 400 replaces the load distribution unit 142 in FIG. 3 with the QoS determination unit 151 that determines the propagation environment, control information, and the like, and the output from the QoS determination unit 151 and the detected processing load. Accordingly, a load distribution unit 152 that distributes the load of the packet buffer 110 is provided. The propagation environment by the QoS determination unit 151 uses, for example, information related to QoS (Quality of Service) of the service. The load distribution unit 152 estimates a future reception rate from the propagation environment, control information, and the like, and performs load distribution only when possible.

  According to this configuration, since load distribution can be accurately controlled by service, service quality can be improved while further reducing power consumption and circuit scale.

  Further, the load balancing units 122, 132, 142, 152 may be configured to thin out packets when the allowable processing load is exceeded. According to this configuration, the packet can be discarded or retransmitted in the lower layer, whereby the delay can be minimized, and the service quality can be improved while further reducing power consumption and circuit scale.

(Embodiment)
FIG. 5 is a block diagram showing a configuration of a packet communication apparatus according to an embodiment of the present invention based on the above basic concept. This embodiment is an example in which the packet communication device is a mobile station device.

  In FIG. 5, the mobile station device 500 includes an antenna 501, a radio reception unit 502, a MAC unit 503, an RLC processing unit 504, and an RRC unit 505.

  In addition, a MAC-hs unit 600 is mounted on a base station device that performs wireless communication with mobile station device 500. The MAC-hs unit 600 includes a HARQ unit 601 that performs HARQ processing, and a Reordering unit 602 that performs processing such as scheduling. The RLC unit 504 of the mobile station device 500 performs flow control with the MAC-hs unit 600 of the base station device.

  The wireless reception unit 502 performs wireless reception processing (down-conversion, A / D conversion, etc.).

  The MAC unit 503 performs the MAC processing of the dedicated channel on the received data according to the wireless layer 2 MAC protocol and outputs the processed data to the RLC unit 504.

  The RLC unit 504 performs retransmission control on the data after MAC processing input from the MAC unit 503 according to the wireless layer 2 retransmission protocol. Then, the RLC unit 504 outputs the retransmission control result to the RRC unit 505.

  The RRC unit 505 performs radio resource control on the retransmission control result input from the RLC unit 504.

  FIG. 6 is a diagram illustrating the HS-DSCH reception unit of the mobile station device 500, and illustrates details of the reordering process in the MAC unit 503 and the RLC processing unit 504 in FIG. 4 is a specific example when the packet communication apparatus 400 of FIG. 4 is applied to an HS-DSCH receiving unit.

  In FIG. 6, the HS-DSCH receiving unit 700 of the mobile station device 500 includes a reordering buffer 710, a HARQ unit 701 that is a first processing unit in the previous stage of the buffer, and a MAC-d / RLC unit that is a second processing unit in the subsequent stage of the buffer. 702, a load prediction unit 703 that detects the processing load of the HARQ unit 701, a QoS determination unit 704 that determines propagation environment, control information, etc., a load detection unit 706 that detects the processing load of the MAC-d / RLC unit 702, and a load prediction A load distribution unit 705 that distributes the load of the reordering buffer 710 according to the processing load detected by the unit 703 and the load detection unit 706 and the output from the QoS determination unit 704.

  Hereinafter, an operation of the packet communication apparatus configured as described above will be described.

  The HARQ unit 701 accumulates received HS-PDSCH (High Speed Physical Downlink Shared Channel) data and performs HARQ (Hybrid ARQ). The packet whose CRC is OK in the HARQ unit 701 is transferred to the reordering buffer 710, and the order of the packets is aligned by the reordering queue. The packets that are in order are sent to an upper layer processing unit such as the MAC-d / RLC unit 702 and processed.

  The load detection unit 706 detects the processing load of the MAC-d / RLC unit 702 and notifies the load distribution unit 705 of the processing load. Also, the load prediction unit 703 extracts control information (presence / absence of packet addressed to own station, packet size, etc.) from the HS-SCCH (High Speed Shared Control Channel) decoding result, and notifies the load distribution unit 705 of the control information. On the other hand, the QoS determination unit 704 extracts information on QoS (Quality of Service) from the packet in which CRC = OK, and notifies the load distribution unit 705 of the information.

  In the load distribution unit 705, based on the information notified from the load prediction unit 703, the QoS determination unit 704, and the load detection unit 706, the reordering buffer 710 to the MAC-d / RLC unit 702, which is an upper layer processing unit. Control packet forwarding. Specifically, when the detected processing load exceeds a predetermined allowable processing load, data transfer from the packet buffer 110 to the MAC-d / RLC unit 702 is delayed, and the load applied to the MAC-d / RLC unit 702 Control to distribute. Further, the load detection unit 706 notifies the MAC-d / RLC unit 702 that an excessive processing load is applied, and if the next packet does not arrive from the load prediction unit 703, and the QoS determination unit 704 receives the immediacy. Is notified that it is an unnecessary service, even if packets arrive in order, packet transfer to the MAC-d / RLC unit 702 is temporarily delayed. Thereby, the processing load in the MAC-d / RLC unit 702 is reduced.

  Here, if the next packet arrives and the packet size is large, the HARQ unit 701 may report CRC to NG and report it to the base station side. With this configuration, retransmission is performed in a short time, and it is possible to prevent unnecessary delay.

  Further, when the QoS of the service requires immediacy, the packet transfer may be delayed or the packet discarding process (CRC = NG) may not be performed.

  Note that the amount of free memory in the reordering buffer 710 may be taken into consideration.

  In this embodiment, load detection is performed using information from the upper layer processing unit in the subsequent stage. However, the load amount of the upper layer processing unit is determined based on the amount of packets transferred from the HARQ unit 701 to the Reordering Queue so far. You may make it guess.

  The load distribution operation described above will be described in detail using a flow.

  FIG. 7 is a flowchart showing the operation of the HS-DSCH receiving unit 700. In the figure, S indicates each step of the flow.

  First, based on the information notified from the load prediction unit 703 and the load detection unit 706 in step S1, it is determined whether or not the predicted load is smaller than a predetermined value. When the predicted load is small, it is determined that the load distribution process can be executed, and it is determined in step S2 whether or not the service has a service with an allowable delay smaller than a predetermined value. When the allowable delay is not a service smaller than the predetermined value, it is determined that immediacy is not requested, and it is determined at step S3 whether the CPU load is smaller than the predetermined value. When the CPU load is small, step S4 is performed. The data is transferred to the upper layer processing unit (here, the MAC-d / RLC unit 702), and this flow is finished.

  On the other hand, when the load predicted in step S1 is larger than a predetermined value, when immediacy is requested in step S2, or when the load on the CPU is larger than a predetermined value in step S3, the load for reordering is determined in step S5. It is determined whether or not there is room in the buffer 710. If there is no room in the reordering buffer 710, the process proceeds to step S4. In step S4, the data is transferred to the MAC-d / RLC unit 702, and this flow ends. If there is room in the reordering buffer 710, the flow ends without transferring the data to the MAC-d / RLC unit 702 in step S6.

  As described above, load distribution processing that delays transfer only when possible exceeds the allowable processing load and from the future load estimation result, so that load distribution can be performed accurately while suppressing the circuit scale. .

  FIG. 8 is a diagram for explaining the concept of flow control. The rectangle in the figure indicates a packet received in units of 2 ms, and the size thereof represents the data amount (bit amount). As shown in FIG. 8A, the amount of received packets varies greatly with time due to adaptive control or the like. In order to process the received packet amount that fluctuates with time in real time, a high processing capability as shown by the broken line in FIG. For example, Performance of processing in FIG. 8B is a processing capacity of 14.4 Mbps, for example. However, the use of a CPU having a large peak processing capability is actually avoided because it leads to an increase in circuit scale and power consumption, which in turn increases costs. In this embodiment, the existing reordering buffer 710 provided in advance for the reordering process is used for this load distribution function, and the L2 process in the CPU is averaged over time, so that peak processing is performed. Reduce the amount. FIG. 8C shows an example of controlling the rate of transfer to the subsequent stage according to the processing load of the subsequent stage. In FIG. 8B, the combined packet data is extended in the time axis direction and averaged over time as shown in FIG. 8C. This is realized by the load distribution unit 705 that delays transfer and transfers at a (constant) rate equal to or less than the allowable processing load when the data exceeds the allowable processing load based on the detected processing load.

  By realizing the distributed function shown in FIG. 8C, data processing in the CPU is averaged, and a CPU having a small peak processing capability can be used. FIG. 8D shows that the CPU only needs to have an average processing capability. For example, the performance of processing in FIG. 8D is, for example, a processing capacity of 3 Mbps, which is about 1/4 of the performance of processing in FIG. 8B.

  FIG. 9 is a diagram for explaining a reordering queue using the reordering buffer 710.

  As shown in FIG. 9A, the packets Packet # 7 to Packet # 2 are temporarily stored in the reordering buffer 710 in the order of arrival. Packet # 1 has not arrived. Note that the maximum waiting time is defined as one cycle of the TSN or until the timer expires (TS 25.321).

  When the packets are in the original order by the reordering processing using the reordering buffer 710 or the maximum waiting time is exceeded, a plurality of packets staying in the reordering buffer 710 are collectively collected as the upper layer MAC. Transferred to the d / RLC unit 702. From the viewpoint of the MAC-d / RLC unit 702, no packet is received during the reordering process, and a large number of packets are sent at once after the reordering process is completed. Further, when viewed from the side of the MAC-d / RLC unit 702 that receives data, as shown in FIG. 8A, the amount of received packets varies greatly with time due to adaptive control or the like.

  By the way, when looking at the contents of the packets Packet # 1 to Packet # 7 staying in the reordering buffer 710, the data amount is not constant for each packet as shown in FIG. In this example, Packet # 3, Packet # 5, etc. have a smaller data amount than Packet # 1, Packet # 6, and Packet # 7. In this embodiment, as shown in FIG. 8C, data transferred to the subsequent stage by the load distribution function is temporally averaged, and it is possible to use a CPU having a small processing capability. From the viewpoint of the amount of data, as shown by the broken line in FIG. 9 (d), packets Packet # 1 to Packet # 7 are grouped together on the reordering buffer 710 without any gap by performance of processing with reduced processing capacity. The image is sent to the upper layer.

  As described above, according to the present embodiment, the HS-DSCH receiving unit 700 determines the processing load of the reordering buffer 710, the load prediction unit 703 that detects the processing load of the HARQ unit 701, and the MAC-d / RLC unit 702. And a load distribution unit 705 that delays data transfer from the packet buffer 110 to the MAC-d / RLC unit 702 based on the detected processing load, and the MAC-d / RLC unit 702. Since the control for distributing the load is performed, by averaging the upper layer processing in terms of time, the peak processing capability of the CPU can be reduced, and the circuit scale and power consumption can be reduced.

  In addition, since the existing reordering buffer is used, a new additional circuit is not required and the circuit scale is not increased. In addition, since the existing reordering buffer is used, the change of the constituent elements can be minimized, so that the implementation is easy and can be realized at low cost.

  In addition, although the peak processing capability of the CPU is reduced, the necessary processing amount is secured, so that packet loss can be reduced and throughput can be improved.

  In addition to the above effects, the present embodiment can provide the following effects.

  That is, when the detected processing load exceeds the allowable processing load, the delay time may be increased only by delaying the data transfer. In the present embodiment, when the detected processing load exceeds the allowable processing load, the data transfer is delayed and the data is transferred at a constant rate that is equal to or lower than the allowable processing load. Therefore, the delay time is reduced while keeping the processing load constant. Can do.

  In addition, the future reception rate is estimated from the propagation environment, control information, service QoS information, etc., and load distribution is performed only when delay is possible, so for those where delay is not allowed by the service, forwarding is not delayed, etc. It becomes possible to control the delay so as not to affect the upper layer (MAC-d / RLC unit 702).

  In addition, when the detected processing load exceeds a predetermined allowable processing load, data to be transferred is thinned out. Therefore, if retransmission is performed in the upper layer (MAC-d / RLC unit 702), the delay is large. Can be avoided and the delay can be minimized. Here, the mode of thinning out data includes data discard or retransmission in a lower layer (HARQ unit 701).

  The above description is an illustration of a preferred embodiment of the present invention, and the scope of the present invention is not limited to this.

  In the above embodiment, the names mobile station device, communication terminal device, and packet communication device are used. However, this is for convenience of explanation, and the mobile terminal, wireless communication device, adaptive reception method, and peak processing amount of CPU. Of course, a reduction method or the like may be used.

  In addition, the CPU has been described as an example, but hardware, a DSP, or the like may be used.

  Further, the type, number, connection method, and the like of each circuit unit constituting the packet communication device are not limited to the above-described embodiments.

  The packet communication method described above is also realized by a program for causing the communication method to function. This program is stored in a computer-readable recording medium.

  INDUSTRIAL APPLICABILITY The packet communication apparatus and the packet communication method according to the present invention have an effect of suppressing a decrease in the throughput of the entire system, and are particularly useful in a wireless communication system to which an HSDPA scheme that communicates packets at high speed via a wireless line is applied. .

The figure which shows the basic composition of the packet communication apparatus of this invention The figure which shows the basic composition of the packet communication apparatus of this invention The figure which shows the basic composition of the packet communication apparatus of this invention The figure which shows the basic composition of the packet communication apparatus of this invention The block diagram which shows the structure of the packet communication apparatus which concerns on embodiment of this invention The figure which shows the HS-DSCH receiving part of the packet communication apparatus which concerns on the said embodiment. The flowchart which shows operation | movement of the HS-DSCH receiving part of the packet communication apparatus which concerns on the said embodiment. The figure explaining the concept of the flow control of the packet communication apparatus which concerns on the said embodiment The figure explaining Reordering Queue of the buffer for Reordering of the packet communication apparatus which concerns on the said embodiment The figure which shows the protocol structure of the user plane in the case of applying HSDPA. The figure which shows the structure of the MAC-hs part of HSDPA. The figure which shows the structure of a MAC-hs part.

Explanation of symbols

100, 200, 300, 400 Packet communication device 110 Packet buffer 111 First processing unit 112 Second processing unit 121,703 Load prediction unit 122,132,142,152,705 Load distribution unit 131,706 Load detection unit 151, 704 QoS determination unit 500 mobile station apparatus 501 antenna 502 wireless reception unit 503 MAC unit 504 RLC processing unit 505 RRC unit 600 MAC-hs unit 601 701 HARQ unit 602 Reordering unit 700 HS-DSCH reception unit 702 MAC-d / RLC unit 710 Reordering buffer

Claims (6)

A packet data reordering buffer;
First processing means provided in a preceding stage of the buffer and outputting a processing result to the buffer;
Second processing means for processing data output from the buffer;
Load detecting means for detecting a processing load of the first processing means and / or the second processing means;
Load distribution means for delaying data transfer from the buffer to the second processing means and distributing the load applied to the second processing means when the detected processing load exceeds a predetermined allowable processing load. A packet communication device.   When the detected processing load exceeds a predetermined allowable processing load, the load distribution unit delays data transfer from the buffer to the second processing unit and transfers the data at a rate equal to or lower than the allowable processing load. The packet communication apparatus according to claim 1. A packet data reordering buffer;
First processing means provided in a preceding stage of the buffer and outputting a processing result to the buffer;
Second processing means for processing data output from the buffer;
Load detecting means for detecting a processing load of the first processing means and / or the second processing means;
Load distribution means for thinning out data transferred from the buffer to the second processing means and distributing the load applied to the second processing means when the detected processing load exceeds a predetermined allowable processing load. A packet communication device.   4. The packet communication apparatus according to claim 1, wherein the load distribution unit determines whether or not to perform the load distribution using QoS information indicating quality of service.   4. The packet communication apparatus according to claim 1, wherein the load detection unit detects a processing load from a data rate at which data is transferred from the buffer to the second processing unit. Performing a first process and outputting the processing result to a packet data rearrangement buffer;
Processing data output from the buffer;
Detecting a processing load in the first process and / or the second process;
And a step of performing a control to delay the transfer of data output from the buffer when the detected processing load exceeds a predetermined allowable processing load.

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