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JP2006229112A - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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JP2006229112A
JP2006229112A JP2005043738A JP2005043738A JP2006229112A JP 2006229112 A JP2006229112 A JP 2006229112A JP 2005043738 A JP2005043738 A JP 2005043738A JP 2005043738 A JP2005043738 A JP 2005043738A JP 2006229112 A JP2006229112 A JP 2006229112A
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protective film
semiconductor substrate
semiconductor device
silicon substrate
back surface
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Takeshi Wakabayashi
猛 若林
Ichiro Mihara
一郎 三原
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Casio Computer Co Ltd
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Casio Computer Co Ltd
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Priority to JP2005043738A priority Critical patent/JP2006229112A/en
Priority to US11/349,779 priority patent/US7390688B2/en
Priority to TW095105557A priority patent/TWI322468B/en
Priority to KR1020060016111A priority patent/KR100763079B1/en
Priority to CN2006100087000A priority patent/CN1825590B/en
Publication of JP2006229112A publication Critical patent/JP2006229112A/en
Pending legal-status Critical Current

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    • H10W70/60—
    • H10W72/012—

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Abstract

【課題】 下面を研削されたシリコン基板の下面にクラックが発生しにくいようにする。
【解決手段】 シリコン基板１の下面側を適宜に研削する。この場合、シリコン基板１の下面に微細で鋭角な凸凹（シリコンの結晶破壊層）が形成される。次に、ウェットエッチングにより、シリコン基板１の下面を段差１〜５μｍの粗面仕上げとする。次に、シリコン基板１の下面にエポキシ系樹脂などからなる保護膜１２を形成する。この場合、シリコン基板１の下面は段差１〜５μｍの粗面となっているので、この粗面は保護膜１２によって確実に覆われ、シリコン基板の下面にクラックが発生しにくいようにすることができる。
【選択図】 図１１PROBLEM TO BE SOLVED: To prevent a crack from being generated on a lower surface of a silicon substrate whose lower surface is ground.
A lower surface side of a silicon substrate is appropriately ground. In this case, fine and acute irregularities (silicon crystal breakdown layer) are formed on the lower surface of the silicon substrate 1. Next, the bottom surface of the silicon substrate 1 is finished with a rough surface with a step of 1 to 5 μm by wet etching. Next, a protective film 12 made of an epoxy resin or the like is formed on the lower surface of the silicon substrate 1. In this case, since the lower surface of the silicon substrate 1 is a rough surface having a level difference of 1 to 5 μm, the rough surface is surely covered with the protective film 12 so that cracks are not easily generated on the lower surface of the silicon substrate. it can.
[Selection] FIG.

Description

この発明は半導体装置およびその製造方法に関する。   The present invention relates to a semiconductor device and a manufacturing method thereof.

従来の半導体装置の製造方法には、半導体基板の厚さを薄くするため、ウエハ状態の半導体基板の裏面を研削し、ウエハ状態の半導体基板の裏面に樹脂からなる保護膜を形成し、所定の工程を経た後に、ウエハ状態の半導体基板などを切断して複数個の半導体装置を得るようにした方法がある（例えば、特許文献１参照）。   In the conventional method of manufacturing a semiconductor device, in order to reduce the thickness of the semiconductor substrate, the back surface of the semiconductor substrate in the wafer state is ground, and a protective film made of resin is formed on the back surface of the semiconductor substrate in the wafer state. There is a method in which a plurality of semiconductor devices are obtained by cutting a semiconductor substrate in a wafer state after the process (see, for example, Patent Document 1).

特開２００１−２３０２２４号公報Japanese Patent Laid-Open No. 2001-230224

ところで、上記従来の製造方法により得られた半導体装置では、半導体基板の裏面を研削すると、半導体基板の裏面に微細で鋭角な凸凹が形成され、この微細で鋭角な凸凹面に樹脂からなる保護膜を形成しても、微細で鋭角な凹部の奥にまで樹脂を確実に充填することが難しく、微細で鋭角な凹部の奥が保護膜で覆われていないことに起因して、半導体基板の裏面にクラックが発生するおそれがあるという問題がある。   By the way, in the semiconductor device obtained by the above-described conventional manufacturing method, when the back surface of the semiconductor substrate is ground, fine and acute unevenness is formed on the back surface of the semiconductor substrate, and the protective film made of resin on this fine and acute uneven surface. Even if formed, it is difficult to reliably fill the resin into the back of the fine and sharp recess, and the back of the semiconductor substrate is caused by the fact that the back of the fine and sharp recess is not covered with a protective film. There is a problem that cracks may occur.

そこで、この発明は、半導体基板の裏面にクラックが発生しにくいようにすることができる半導体装置およびその製造方法を提供することを目的とする。   In view of the above, an object of the present invention is to provide a semiconductor device and a method for manufacturing the same that can prevent cracks from being generated on the back surface of the semiconductor substrate.

この発明は、上記目的を達成するため、裏面に段差１〜５μｍの粗面を有する半導体基板と、前記半導体基板の裏面に設けられた保護膜とを有することを特徴とするものである。   In order to achieve the above object, the present invention is characterized by having a semiconductor substrate having a rough surface with a step of 1 to 5 μm on the back surface and a protective film provided on the back surface of the semiconductor substrate.

この発明によれば、半導体基板の裏面を段差１〜５μｍの粗面としているので、この粗面を保護膜で確実に覆うことができ、したがって半導体基板の裏面にクラックが発生しにくいようにすることができる。   According to the present invention, since the back surface of the semiconductor substrate is a rough surface having a level difference of 1 to 5 μm, the rough surface can be reliably covered with the protective film, and therefore, the back surface of the semiconductor substrate is not easily cracked. be able to.

図１はこの発明の一実施形態としての半導体装置の断面図を示す。この半導体装置は、一般的にはＣＳＰ(chip size package)と呼ばれるものであり、シリコン基板（半導体基板）１を備えている。シリコン基板１の上面には所定の機能の集積回路（図示せず）が設けられ、上面周辺部にはアルミニウム系金属などからなる複数の接続パッド２が集積回路に接続されて設けられている。   FIG. 1 is a sectional view of a semiconductor device as an embodiment of the present invention. This semiconductor device is generally called a CSP (chip size package) and includes a silicon substrate (semiconductor substrate) 1. An integrated circuit (not shown) having a predetermined function is provided on the upper surface of the silicon substrate 1, and a plurality of connection pads 2 made of an aluminum-based metal or the like are provided connected to the integrated circuit on the periphery of the upper surface.

接続パッド２の中央部を除くシリコン基板１の上面には酸化シリコンなどからなる絶縁膜３が設けられ、接続パッド２の中央部は絶縁膜３に設けられた開口部４を介して露出されている。絶縁膜３の上面にはエポキシ系樹脂やポリイミド系樹脂などからなる保護膜５が設けられている。この場合、絶縁膜３の開口部４に対応する部分における保護膜５には開口部６が設けられている。   An insulating film 3 made of silicon oxide or the like is provided on the upper surface of the silicon substrate 1 excluding the central portion of the connection pad 2, and the central portion of the connection pad 2 is exposed through an opening 4 provided in the insulating film 3. Yes. A protective film 5 made of epoxy resin or polyimide resin is provided on the upper surface of the insulating film 3. In this case, an opening 6 is provided in the protective film 5 at a portion corresponding to the opening 4 of the insulating film 3.

保護膜５の上面には銅などからなる下地金属層７が設けられている。下地金属層７の上面全体には銅からなる配線８が設けられている。下地金属層７を含む配線８の一端部は、絶縁膜３および保護膜５の開口部４、６を介して接続パッド２に接続されている。配線８の接続パッド部上面には銅からなる柱状電極９が設けられている。   A base metal layer 7 made of copper or the like is provided on the upper surface of the protective film 5. A wiring 8 made of copper is provided on the entire upper surface of the base metal layer 7. One end of the wiring 8 including the base metal layer 7 is connected to the connection pad 2 through the openings 4 and 6 of the insulating film 3 and the protective film 5. A columnar electrode 9 made of copper is provided on the upper surface of the connection pad portion of the wiring 8.

配線８を含む保護膜５の上面にはエポキシ系樹脂やポリイミド系樹脂などからなる封止膜１０がその上面が柱状電極９の上面と面一となるように設けられている。柱状電極９の上面には半田ボール１１が設けられている。シリコン基板１の下面（裏面）にはエポキシ系樹脂やポリイミド系樹脂などからなる保護膜１２が設けられている。   A sealing film 10 made of an epoxy resin or a polyimide resin is provided on the upper surface of the protective film 5 including the wiring 8 so that the upper surface is flush with the upper surface of the columnar electrode 9. A solder ball 11 is provided on the upper surface of the columnar electrode 9. A protective film 12 made of an epoxy resin or a polyimide resin is provided on the lower surface (back surface) of the silicon substrate 1.

次に、この半導体装置の製造方法の一例について説明する。まず、図２に示すように、ウエハ状態のシリコン基板（半導体基板）１上にアルミニウム系金属などからなる接続パッド２、酸化シリコンなどからなる絶縁膜３およびエポキシ系樹脂やポリイミド系樹脂などからなる保護膜５が設けられ、接続パッド２の中央部が絶縁膜３および保護膜５に形成された開口部４、６を介して露出されたものを用意する。   Next, an example of a method for manufacturing this semiconductor device will be described. First, as shown in FIG. 2, on a silicon substrate (semiconductor substrate) 1 in a wafer state, a connection pad 2 made of an aluminum metal, an insulating film 3 made of silicon oxide, an epoxy resin, a polyimide resin, or the like. A protective film 5 is provided, and the connection pad 2 is exposed through the openings 4 and 6 formed in the insulating film 3 and the protective film 5.

この場合、ウエハ状態のシリコン基板１には、各半導体装置が形成される領域に所定の機能の集積回路が形成され、接続パッド２は、それぞれ、対応する領域に形成された集積回路に電気的に接続されている。また、ウエハ状態のシリコン基板１の厚さは、図１に示すシリコン基板１の厚さよりもある程度厚くなっている。なお、図２において、符号２１で示す領域はダイシングストリートに対応する領域である。   In this case, on the silicon substrate 1 in the wafer state, an integrated circuit having a predetermined function is formed in a region where each semiconductor device is formed, and the connection pad 2 is electrically connected to the integrated circuit formed in the corresponding region. It is connected to the. Further, the thickness of the silicon substrate 1 in the wafer state is somewhat larger than the thickness of the silicon substrate 1 shown in FIG. In FIG. 2, an area indicated by reference numeral 21 is an area corresponding to dicing street.

次に、図３に示すように、絶縁膜３および保護膜５の開口部４、６を介して露出された接続パッド２の上面を含む保護膜５の上面全体に下地金属層７を形成する。この場合、下地金属層７は、無電解メッキにより形成された銅層のみであってもよく、またスパッタにより形成された銅層のみであってもよく、さらにスパッタにより形成されたチタンなどの薄膜層上にスパッタにより銅層を形成したものであってもよい。   Next, as shown in FIG. 3, a base metal layer 7 is formed on the entire upper surface of the protective film 5 including the upper surfaces of the connection pads 2 exposed through the openings 4 and 6 of the insulating film 3 and the protective film 5. . In this case, the base metal layer 7 may be only a copper layer formed by electroless plating, or may be only a copper layer formed by sputtering, and a thin film such as titanium formed by sputtering. A copper layer may be formed on the layer by sputtering.

次に、下地金属層７の上面にメッキレジスト膜２２をパターン形成する。この場合、配線８形成領域に対応する部分におけるメッキレジスト膜２２には開口部２３が形成されている。次に、下地金属層７をメッキ電流路として銅の電解メッキを行なうことにより、メッキレジスト膜２２の開口部２３内の下地金属層７の上面に配線８を形成する。次に、メッキレジスト膜２２を剥離する。   Next, a plating resist film 22 is pattern-formed on the upper surface of the base metal layer 7. In this case, an opening 23 is formed in the plating resist film 22 in a portion corresponding to the wiring 8 formation region. Next, by performing copper electroplating using the base metal layer 7 as a plating current path, the wiring 8 is formed on the upper surface of the base metal layer 7 in the opening 23 of the plating resist film 22. Next, the plating resist film 22 is peeled off.

次に、図４に示すように、配線８を含む下地金属層７の上面にメッキレジスト膜２４をパターン形成する。この場合、柱状電極９形成領域に対応する部分におけるメッキレジスト膜２４には開口部２５が形成されている。次に、下地金属層７をメッキ電流路として銅の電解メッキを行なうことにより、メッキレジスト膜２４の開口部２５内の配線８の接続パッド部上面に柱状電極９を形成する。次に、メッキレジスト膜２４を剥離し、次いで、配線８をマスクとして下地金属層７の不要な部分をエッチングして除去すると、図５に示すように、配線８下にのみ下地金属層７が残存される。   Next, as shown in FIG. 4, a plating resist film 24 is formed on the upper surface of the base metal layer 7 including the wiring 8. In this case, an opening 25 is formed in the plating resist film 24 at a portion corresponding to the columnar electrode 9 formation region. Next, the columnar electrode 9 is formed on the upper surface of the connection pad portion of the wiring 8 in the opening 25 of the plating resist film 24 by performing electrolytic plating of copper using the base metal layer 7 as a plating current path. Next, the plating resist film 24 is peeled off, and then unnecessary portions of the base metal layer 7 are removed by etching using the wiring 8 as a mask, so that the base metal layer 7 is formed only under the wiring 8 as shown in FIG. Remain.

次に、図６に示すように、柱状電極９および配線８を含む保護膜５の上面全体に、スクリーン印刷法やスピンコート法などにより、エポキシ系樹脂やポリイミド系樹脂などからなる封止膜１０をその厚さが柱状電極９の高さよりも厚くなるように形成する。したがって、この状態では、柱状電極９の上面は封止膜１０によって覆われている。   Next, as shown in FIG. 6, a sealing film 10 made of an epoxy resin, a polyimide resin, or the like is formed on the entire upper surface of the protective film 5 including the columnar electrodes 9 and the wirings 8 by a screen printing method, a spin coating method, or the like. Is formed so that the thickness thereof is greater than the height of the columnar electrode 9. Therefore, in this state, the upper surface of the columnar electrode 9 is covered with the sealing film 10.

次に、封止膜１０および柱状電極９の上面側を適宜に研磨し、図７に示すように、柱状電極９の上面を露出させ、且つ、この露出された柱状電極９の上面を含む封止膜１０の上面を平坦化する。ここで、柱状電極９の上面側を適宜に研磨するのは、電解メッキにより形成される柱状電極９の高さにばらつきがあるため、このばらつきを解消して、柱状電極９の高さを均一にするためである。   Next, the upper surface side of the sealing film 10 and the columnar electrode 9 is appropriately polished to expose the upper surface of the columnar electrode 9 and to include the exposed upper surface of the columnar electrode 9 as shown in FIG. The upper surface of the stop film 10 is flattened. Here, the reason for appropriately polishing the upper surface side of the columnar electrode 9 is that the height of the columnar electrode 9 formed by electrolytic plating varies, so that this variation is eliminated and the height of the columnar electrode 9 is made uniform. It is to make it.

次に、図８に示すように、シリコン基板１の厚さを薄くするため、シリコン基板１の下面（裏面）側を適宜に研削または研摩する。ここで、ウエハ状態のシリコン基板１の下面を研削または研摩すると、図８のＡ部を詳細に示す部分拡大断面図である図９に示すように、シリコン基板１の下面に微細で鋭角な凸凹（シリコンの結晶破壊層）２６が形成される。この微細で鋭角な凸凹２６は、シリコン基板１の下面にクラックが発生する要因となる。   Next, as shown in FIG. 8, in order to reduce the thickness of the silicon substrate 1, the lower surface (back surface) side of the silicon substrate 1 is appropriately ground or polished. Here, when the lower surface of the silicon substrate 1 in the wafer state is ground or polished, as shown in FIG. 9 which is a partially enlarged sectional view showing in detail the portion A in FIG. (Silicon crystal destruction layer) 26 is formed. The fine and sharp irregularities 26 cause cracks on the lower surface of the silicon substrate 1.

そこで、次に、硝酸−フッ酸−酢酸の混合溶液またはこれに水を加えた混合溶液を用いたウェットエッチングを行なう。このウェットエッチングでは、硝酸でシリコン基板１の下面を酸化させて酸化膜を形成し、フッ酸でこの酸化膜を溶解して除去し、酢酸で反応を制御することになる。この場合、混合溶液の組成比や処理時間などの条件により、シリコン基板１の下面を鏡面仕上げとすることもできるが、シリコン基板１が光の影響を受けにくいようにするために、図１０に示すように、シリコン基板１の下面を段差１〜５μｍの粗面仕上げとする方が好ましい。   Therefore, next, wet etching is performed using a mixed solution of nitric acid-hydrofluoric acid-acetic acid or a mixed solution obtained by adding water. In this wet etching, the lower surface of the silicon substrate 1 is oxidized with nitric acid to form an oxide film, the oxide film is dissolved and removed with hydrofluoric acid, and the reaction is controlled with acetic acid. In this case, the bottom surface of the silicon substrate 1 can be mirror-finished depending on conditions such as the composition ratio of the mixed solution and processing time, but in order to make the silicon substrate 1 less susceptible to light, FIG. As shown, it is preferable that the lower surface of the silicon substrate 1 has a rough surface finish with steps of 1 to 5 μm.

次に、図１１に示すように、シリコン基板１の下面に、スクリーン印刷法やスピンコート法などにより、エポキシ系樹脂やポリイミド系樹脂などからなる保護膜１２をその下面が平坦となるように形成する。予め表面に離型材を有するベースシートに保護膜１２を形成しておき、転写法によってシリコン基板１の裏面に保護膜１２を設けるようにしてもよい。この場合、シリコン基板１の下面は、図１０に示すように、段差１〜５μｍの粗面となっているので、この粗面は保護膜１２によって確実に覆われる。   Next, as shown in FIG. 11, a protective film 12 made of an epoxy resin or a polyimide resin is formed on the lower surface of the silicon substrate 1 by a screen printing method or a spin coating method so that the lower surface thereof is flat. To do. A protective film 12 may be formed in advance on a base sheet having a release material on the surface, and the protective film 12 may be provided on the back surface of the silicon substrate 1 by a transfer method. In this case, as shown in FIG. 10, the lower surface of the silicon substrate 1 is a rough surface having a level difference of 1 to 5 μm, so that the rough surface is reliably covered with the protective film 12.

次に、柱状電極９の上面に半田ボール１１を形成する。次に、図１２に示すように、ダイシングストリート２１に沿って、ダイシング法により、封止膜１０、保護膜５、絶縁膜３、シリコン基板１および保護膜１２を切断すると、図１に示す半導体装置が複数個得られる。   Next, a solder ball 11 is formed on the upper surface of the columnar electrode 9. Next, as shown in FIG. 12, when the sealing film 10, the protective film 5, the insulating film 3, the silicon substrate 1 and the protective film 12 are cut along the dicing street 21 by a dicing method, the semiconductor shown in FIG. Multiple devices are obtained.

このようにして得られた半導体装置では、図１０に示すように、シリコン基板１の下面を段差１〜５μｍの粗面としているので、この粗面を保護膜１２で確実に覆うことができ、したがってシリコン基板１の下面にクラックが発生しにくいようにすることができる。   In the semiconductor device obtained in this way, as shown in FIG. 10, the lower surface of the silicon substrate 1 is a rough surface having a step of 1 to 5 μm, so that the rough surface can be reliably covered with the protective film 12, Therefore, it is possible to prevent cracks from being generated on the lower surface of the silicon substrate 1.

なお、保護膜１２は、樹脂ではなく、金属によって形成するようにしてもよい。金属材料としては、シリコン基板１との密着性が良く、機械的強度が高いものであればよく、一例を挙げればチタンなどである。そして、図１０に示す工程後に、図１３に示すように、シリコン基板１の下面に、スパッタ法などにより、チタンからなる保護膜１２を膜厚１５００Å程度に形成する。この場合、チタンからなる保護膜１２には樹脂のような硬化収縮が発生しないので、シリコン基板１に反りが発生しないようにすることができる。   In addition, you may make it form the protective film 12 with a metal instead of resin. The metal material may be any metal material that has good adhesion to the silicon substrate 1 and high mechanical strength. For example, titanium is used. Then, after the step shown in FIG. 10, as shown in FIG. 13, a protective film 12 made of titanium is formed on the lower surface of the silicon substrate 1 by a sputtering method or the like to a thickness of about 1500 mm. In this case, the protective film 12 made of titanium does not undergo curing shrinkage unlike the resin, so that the silicon substrate 1 can be prevented from warping.

また、この発明は、ＣＳＰと呼ばれる半導体装置に限らず、例えば、絶縁膜３の開口部４を介して露出された接続パッド２上に下地金属層および柱状電極を形成し、柱状電極の周囲における絶縁膜３上に封止膜を形成し、柱状電極上に半田ボールを形成した半導体装置にも適用することができる。   In addition, the present invention is not limited to a semiconductor device called a CSP. For example, a base metal layer and a columnar electrode are formed on the connection pad 2 exposed through the opening 4 of the insulating film 3, and the periphery of the columnar electrode is formed. The present invention can also be applied to a semiconductor device in which a sealing film is formed on the insulating film 3 and solder balls are formed on columnar electrodes.

この発明の一実施形態としての半導体装置の断面図。1 is a cross-sectional view of a semiconductor device as an embodiment of the present invention. 図１に示す半導体装置の製造方法の一例において、当初用意したものの断面 図。Sectional drawing of what was prepared initially in an example of the manufacturing method of the semiconductor device shown in FIG. 図２に続く工程の断面図。Sectional drawing of the process following FIG. 図３に続く工程の断面図。Sectional drawing of the process following FIG. 図４に続く工程の断面図。Sectional drawing of the process following FIG. 図５に続く工程の断面図。Sectional drawing of the process following FIG. 図６に続く工程の断面図。Sectional drawing of the process following FIG. 図７に続く工程の断面図。Sectional drawing of the process following FIG. 図８のＡ部を詳細に示す部分拡大断面図。The partial expanded sectional view which shows the A section of FIG. 8 in detail. 図９に続く工程の部分拡大断面図。FIG. 10 is a partial enlarged cross-sectional view of the process following FIG. 9. 図１０に続く工程の断面図。Sectional drawing of the process following FIG. 図１１に続く工程の断面図。Sectional drawing of the process following FIG. 保護膜を金属で形成した場合の図１０に続く工程の部分拡大断面図。FIG. 11 is a partial enlarged cross-sectional view of the process following FIG. 10 when the protective film is formed of metal.

符号の説明Explanation of symbols

１ シリコン基板
２ 接続パッド
３ 絶縁膜
５ 保護膜
７ 下地金属層
８ 配線
９ 柱状電極
１０ 封止膜
１１ 半田ボール
１２ 保護膜 DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Connection pad 3 Insulating film 5 Protective film 7 Base metal layer 8 Wiring 9 Columnar electrode 10 Sealing film 11 Solder ball 12 Protective film

Claims (11)

裏面に段差１〜５μｍの粗面を有する半導体基板と、前記半導体基板の裏面に設けられた保護膜とを有することを特徴とする半導体装置。   A semiconductor device comprising: a semiconductor substrate having a rough surface with a step of 1 to 5 μm on the back surface; and a protective film provided on the back surface of the semiconductor substrate. 請求項１に記載の発明において、前記保護膜は樹脂からなることを特徴とする半導体装置。   2. The semiconductor device according to claim 1, wherein the protective film is made of a resin. 請求項１に記載の発明において、前記保護膜は金属からなることを特徴とする半導体装置。   2. The semiconductor device according to claim 1, wherein the protective film is made of metal. 請求項１に記載の発明において、前記半導体基板上に複数の柱状電極が設けられ、前記柱状電極の周囲における前記半導体基板上に封止膜が設けられていることを特徴とする半導体装置。   2. The semiconductor device according to claim 1, wherein a plurality of columnar electrodes are provided on the semiconductor substrate, and a sealing film is provided on the semiconductor substrate around the columnar electrodes. 請求項４に記載の発明において、前記柱状電極上に半田ボールが設けられていることを特徴とする半導体装置。   5. The semiconductor device according to claim 4, wherein a solder ball is provided on the columnar electrode. 半導体基板の微細で鋭角な凸凹の裏面をウェットエッチングにより粗面化し、前記半導体基板の裏面に保護膜を形成することを特徴とする半導体装置の製造方法。   A method of manufacturing a semiconductor device, comprising: roughening a back surface of a fine and sharp surface of a semiconductor substrate by wet etching to form a protective film on the back surface of the semiconductor substrate. 請求項６に記載の発明において、前記ウェットエッチング工程前に、前記半導体基板の裏面を研削することを特徴とする半導体装置の製造方法。   7. The method of manufacturing a semiconductor device according to claim 6, wherein the back surface of the semiconductor substrate is ground before the wet etching step. 請求項６に記載の発明において、前記保護膜は樹脂によって形成することを特徴とする半導体装置の製造方法。   7. The method of manufacturing a semiconductor device according to claim 6, wherein the protective film is formed of a resin. 請求項６に記載の発明において、前記保護膜は金属によって形成することを特徴とする半導体装置の製造方法。   7. The method of manufacturing a semiconductor device according to claim 6, wherein the protective film is made of metal. 複数の接続パッドを有する半導体基板を準備する工程と、
前記接続パッドに接続される配線を設ける工程と、
前記配線上に柱状電極を設ける工程と、
前記半導体基板上の前記柱状電極間に封止膜を設ける工程と、
前記半導体基板の裏面を研削または研摩し、この後、前記半導体基板の裏面をウェットエッチングする工程と、
前記ウェットエッチングが施された半導体基板の裏面に保護膜を設ける工程と、
前記半導体基板を前記封止膜および前記保護膜と共にダイシングして、個々の半導体装置を得る工程と、
を含むことを特徴とする半導体装置の製造方法。 Preparing a semiconductor substrate having a plurality of connection pads;
Providing a wiring connected to the connection pad;
Providing a columnar electrode on the wiring;
Providing a sealing film between the columnar electrodes on the semiconductor substrate;
Grinding or polishing the back surface of the semiconductor substrate, and then wet etching the back surface of the semiconductor substrate;
Providing a protective film on the back surface of the semiconductor substrate subjected to the wet etching;
Dicing the semiconductor substrate together with the sealing film and the protective film to obtain individual semiconductor devices;
A method for manufacturing a semiconductor device, comprising: 請求項１０に記載の発明において、前記半導体基板をダイシングする前に、前記柱状電極上に半田ボールを設ける工程を有することを特徴とする半導体装置の製造方法。   11. The method of manufacturing a semiconductor device according to claim 10, further comprising a step of providing a solder ball on the columnar electrode before dicing the semiconductor substrate.
JP2005043738A 2005-02-21 2005-02-21 Semiconductor device and manufacturing method thereof Pending JP2006229112A (en)

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