JP2006218704A - Image writing apparatus and image forming apparatus - Google Patents

Abstract

The present invention relates to an image writing apparatus that appropriately drives a plurality of light emitting element array units arranged in a staggered manner according to specifications, and an image forming apparatus using the image writing apparatus.
In a digital copying apparatus 1, LED heads 26a to 26c of an optical writing unit 26 are arranged in a staggered manner, and an LED writing control circuit 51 transfers image data for one line for each LED head 26a to 26c. Are divided into two, and transferred to the LED heads 26a to 26c, and the LEDs of the LED heads 26a to 26c are driven to perform main scanning. These data division patterns, light quantity correction / print selection signals, data transfer methods, A plurality of various signals such as a data transfer clock, a reset signal, a strobe light emission pattern, and an image data latch signal are prepared in advance, and these signals are combined to make the LED heads 26a to 26c binary, multivalue, static light emission, Operate according to various specifications such as dynamic light emission.
[Selection] Figure 2

Description

  The present invention relates to an image writing apparatus and an image forming apparatus, and more specifically, to use an image writing apparatus that appropriately drives a plurality of light emitting element array units arranged in a staggered manner according to specifications, and the image writing apparatus. The present invention relates to an image forming apparatus.

  In an image forming apparatus such as a copying machine, a printer, and a facsimile machine using an electrophotographic method, a uniformly charged photosensitive member is irradiated with writing light modulated by image data by an optical writing unit. Then, an electrostatic latent image is formed on the photosensitive member, and toner (developer) is supplied to the photosensitive member on which the electrostatic latent image is formed by a developing unit to develop the photosensitive member. The image forming apparatus transfers the toner image (developer image) on the photosensitive member to the recording paper at the transfer unit, and then heats and presses the toner image transferred onto the recording paper at the fixing unit to fix the toner image. ing.

  As an image writing unit of such an image forming apparatus, an LD scanning method using a laser beam scanning optical system including an LD (Laser Diode) that emits a laser as a light source and a polygon mirror that is rotationally driven by a polygon motor; As a light source, a light emitting element array system in which light emitting elements such as LEDs (Light Emitting Diodes) are arranged in an array is generally used.

  The light emitting element array method has no moving parts like the polygon mirror of the LD scanning method, is highly reliable, and is used for a wide-width machine that requires a large size print output such as A0 width. An optical space for scanning the light beam in the direction is unnecessary, and an LED head (LPH: LED Print Head) that is a light emitting element array unit in which an optical element such as an LED array and a selfoc lens is integrated is disposed. Since the entire apparatus can be downsized, the LD scanning method has been replaced.

  On the other hand, in the light emitting element array method, it is necessary to use a light emitting element array unit that is longer than the image writing width as the light emitting element array unit, but in a wide machine that requires a large size print output such as A0 width. As the light emitting element array unit becomes longer, the number of LED element driver ICs to be used increases and the production yield decreases, and the light emitting element array unit becomes longer and the accuracy of the writing beam arrangement is maintained. For this reason, it is necessary to use high-precision parts, and the unit unit price is very expensive as compared with a light-emitting element array unit of a small printer or copying machine. Further, if even one dot of the long light emitting element array unit fails, the light emitting element array unit must be replaced, which is also expensive from this viewpoint.

  Therefore, conventionally, as shown in FIG. 21, the cost is reduced by using a method in which three LED heads 1001a to 1001c are arranged in the main scanning direction and divided exposure is performed (see Patent Document 1). In this case, in order to expose the A0 width photoconductor, three LED heads 1001a to 1001c that are slightly larger than the A3 width are arranged in a staggered manner in the main scanning direction as shown in FIG. As a whole, the exposure is divided to the A0 width or more by making the A0 width or more.

  By arranging the LED heads in a staggered manner in this way, positional deviation occurs in the main scanning direction and the sub-scanning direction of the photosensitive member. Since this misalignment causes LED head joints to appear as streaks in the image, various techniques for correcting this misalignment have been proposed.

  For example, the present applicant previously changed the number of divided light emitting elements and the block allocation of each dot arbitrarily for each line so that the number of lighting of one block is always substantially equal to the target lighting number, A technique for preventing fluctuations in driving current and fluctuations in image density due to the above has been proposed (see Patent Document 2).

JP 2001-328292 A JP 2003-25630 A

  However, in the above prior art, in the prior art described in Patent Document 2, it is possible to prevent fluctuations in driving current and fluctuations in image density, but for streaks occurring at the joints of LED heads. , Can not be resolved.

  In recent years, the use of LEDs has been diversified, and the specifications of LED heads are often changed when small-scale improvements are made to image forming apparatuses or when new models are introduced. In such a case, depending on the specifications of each LED head, a significant revision of the interface with the LPH, the ASIC of the LPH, and the FPGA (Field Programmable Gate Array) is required each time, which increases the design period, cost, and burden on personnel.

  Therefore, in order to cope with such problems, LED heads with different specifications can be flexibly adapted to the needs, specifications, and costs required of image forming apparatuses even when small-scale improvements and new models are introduced. There is a demand for an image writing apparatus that can be used.

  Therefore, the present invention uses two types of driving methods, a static lighting method and a dynamic lighting method, which are the mainstream of the current LED driving method, and types of LED heads such as a binary and multi-value LED head, and will be used in the future. When using LED heads that enable writing for wider image forming devices by connecting multiple LED heads for wider image forming devices, even if there is a difference in specifications for each LED head An object of the present invention is to provide a possible image writing apparatus and an image forming apparatus using the image writing apparatus.

  An image writing apparatus according to a first aspect of the present invention includes a light emitting element array in which a plurality of light emitting elements are arranged in one direction, and an image forming unit that forms an image of light emitted from the light emitting element array on a photosensitive member. A plurality of light emitting element array units that are shorter than the axial length of the photosensitive member are arranged in a staggered manner with a predetermined amount of displacement in the sub-scanning direction and a predetermined amount of overlap in the main scanning direction. Based on various signals such as correction / print selection signal, data transfer method, data transfer clock, reset signal, strobe light emission pattern and image data latch signal, one line of image data is divided for each light emitting element array unit. Transfer to each light emitting element array unit to drive each light emitting element of the light emitting element array unit, the data division pattern, Prepare various types of signals such as quantity correction / print selection signal, data transfer method, data transfer clock, reset signal, strobe light emission pattern and image data latch signal in advance, and combine these signals to make the light emitting element array The above object is achieved by operating in accordance with various specifications such as binary, multi-value, static light emission, and dynamic light emission.

  In this case, for example, as described in claim 2, the image writing device may be capable of arbitrarily setting the number of divisions in the main scanning direction of the image data from the outside.

  For example, as described in claim 3, the image writing device takes out the image data every arbitrary number of data in the main scanning direction, rearranges the data, and performs the rearrangement every other data. It may be arbitrarily settable from the outside.

  Further, for example, as described in claim 4, the image writing apparatus includes: a division number setting function for arbitrarily setting a division number in the main scanning direction of the image data; and the image data In addition to taking out and rearranging every arbitrary number of data in the scanning direction, and rearranging setting function for arbitrarily setting the number of data to be rearranged from outside, these division number setting function and rearrangement setting function Either of these may be executed according to the selection.

  Further, for example, as described in claim 5, the image writing apparatus may arbitrarily set whether the light amount correction / print selection signal is set to High active or Low active from the outside. Good.

  Further, for example, as described in claim 6, the image writing device may be able to arbitrarily set the number of switching of High / Low of the light amount correction / print selection signal from the outside.

  Further, for example, as described in claim 7, the image writing device may be capable of arbitrarily setting the number of parallel transfer bits of the image data from the outside.

  Furthermore, for example, as described in claim 8, the image writing device may be able to arbitrarily set an effective width time of each data from the outside.

  For example, as described in claim 9, the image writing device may be able to arbitrarily set the cycle and duty of the data transfer clock from the outside.

  Furthermore, for example, as described in claim 10, the image writing device may be arbitrarily settable from the outside so that the number of clocks of the data transfer clock matches the number of data to be transferred.

  For example, as described in claim 11, the image writing apparatus may be able to arbitrarily set whether the reset signal is made active high or active low.

  Furthermore, for example, as described in claim 12, the image writing device may be able to arbitrarily set a time for activating the reset signal from the outside.

  For example, as described in claim 13, the image writing device may be capable of arbitrarily setting the number of strobe light emission signals from the outside.

  Further, for example, as described in claim 14, the image writing device may be able to arbitrarily set a pulse period and a duty of a strobe light emission signal from the outside for each light emitting element array.

  Further, for example, as described in claim 15, the image writing device may be capable of arbitrarily setting the number of pulses of the latch signal of the image data from the outside.

  Furthermore, for example, as described in claim 16, the image writing device may be capable of arbitrarily setting a pulse width of a latch signal of the image data from the outside.

  In the image forming apparatus according to the seventeenth aspect of the present invention, the image writing unit irradiates the photosensitive member with light to form an electrostatic latent image on the photosensitive member, and develops the electrostatic latent image with a developer. In an image forming apparatus that finally transfers an agent image to a sheet to form an image, the image writing device according to any one of claims 1 to 16 is used as the image writing unit. Has achieved the above objectives.

  According to the image writing apparatus of the present invention, a plurality of light emitting element arrays arranged in a staggered manner shorter than the main scanning width are divided into a data division pattern, a light amount correction / print selection signal, a data transfer method, a data transfer clock. Based on various signals such as a reset signal, a strobe light emission pattern, and an image data latch signal, the image data for one line is divided for each light emitting element array unit and transferred to each light emitting element array unit. Various signals such as data division pattern, light intensity correction / printing selection signal, data transfer method, data transfer clock, reset signal, strobe light emission pattern, and image data latch signal when driving each light emitting element of the array unit for main scanning A plurality of types are prepared in advance, and by combining these signals, the light-emitting element array is binary, multi-value, static light emission, Since it operates in accordance with various specifications such as static light emission, the driving method of static lighting method and dynamic lighting method, the type of light emitting element array such as binary and multi-value, and the possibility of future use When using multiple light emitting element arrays for a wide image forming device to realize writing for a wider image forming device, etc. can do.

  According to the image forming apparatus of the present invention, since the image writing device according to any one of claims 1 to 16 is used as an image writing unit that forms an electrostatic latent image on a photoconductor. By absorbing the specification difference of the light emitting element array of the image writing unit, it is possible to form an image at a low cost in a wide range.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In addition, since the Example described below is a suitable Example of this invention, various technically preferable restrictions are attached | subjected, However, The scope of the present invention limits this invention especially in the following description. As long as there is no description of the effect, it is not restricted to these aspects.

  1 to 20 are diagrams showing an embodiment of an image writing apparatus and an image forming apparatus according to the present invention, and FIG. 1 is an application of an embodiment of the image writing apparatus and the image forming apparatus according to the present invention. 1 is a schematic front configuration diagram of a digital copying apparatus 1. FIG.

  In FIG. 1, a digital copying apparatus 1 contains a paper feed unit 3, a conveyance unit 4, an image forming unit 5, a fixing unit 6, a paper discharge unit 7, an image reading unit 8, and the like in a main body housing 2. Further, a manual feed tray 10, a document table 11, a separation charger 12, a transport tank 13, a paper discharge tray 14, and the like are provided, and an operation unit 15 (see FIG. 2) and the like are provided.

  A plurality of transfer papers 21 are set on the paper feed tray 22 in the paper feed unit 3, and the transport unit 4 includes registration rollers 23 and the like, and appropriate transfer papers 21 in the paper feed unit 3 are transferred to the registration rollers 23. Then, the timing is adjusted and conveyed to the image forming unit 5. The transport unit 4 also transports the transfer paper 21 set on the manual feed tray 10 to the image forming unit 5 after adjusting the timing with the registration rollers 23.

  The image forming unit 5 has a charging unit 25, an optical writing unit (optical writing device) 26, a developing unit 27, a transfer unit 28, and a cleaning unit around the photosensitive member 24 that is driven to rotate counterclockwise in FIG. The charging unit 25 uses a scorotron charger with a grid, for example, and uniformly charges the photoconductor 24. In the image forming unit 5, the optical writing unit 26 irradiates the photoconductor 24 uniformly charged by the charging unit 25 with light whose lighting is controlled based on the image data of the document read by the image reading unit 8. Then, the charge on the surface of the photosensitive member 24 irradiated with light is caused to flow to the ground by a photoconductive phenomenon to disappear, thereby forming an electrostatic latent image, and developing the photosensitive member 24 on which the electrostatic latent image is formed. The unit 27 attaches toner (developer) to form a toner image (developer image). That is, the toner in the developing unit 27 is negatively charged by stirring, the bias is applied to −700 V, and the toner adheres only to the light irradiated portion of the photoreceptor 24. The image forming unit 5 transfers the toner image formed on the photosensitive member 24 to the transfer paper 21 conveyed from the paper feeding unit 3 by the transfer unit 28, and the transfer paper 21 that has been transferred is separated by the separation charger 12. Then, it is transported to the fixing unit 6 by the transport tank 13. Further, the image forming unit 5 cleans the residual toner on the photosensitive member 24 that has been transferred by the cleaning unit 29, removes the cleaned photosensitive member 24 by a neutralizing unit (not shown), and then removes the toner by the charging unit 25. In this way, it is charged and used again for image formation.

  As shown in FIGS. 2 and 3, for example, when the photosensitive member 24 has a writing width of A0 width, the optical writing unit 26 has three LED heads (LPH: LED) having an A3 width. Print head (light emitting element array unit) 26a, 26b, 26c, LED writing control circuit 51, image forming means such as SAL (self-lens lens array) not shown, and the like. LED heads 26a-26c are photosensitive members 24. Are arranged in an array in the axial direction (main scanning direction), and are arranged in a staggered manner with a positional shift in the rotation direction (sub-scanning direction) of the photoconductor 24. Each LED head 26a to 26c is not shown, but a predetermined number, for example, 40 LED arrays (light emitting element arrays) are arranged in a line at equal intervals, and each LED array is, for example, 192, respectively. The LED elements are arranged in a row, and a total of 7680 (192 × 40 = 7680) LED elements are arranged. A driver is connected to each LED element for each LED array, and an LED write control circuit 51 is connected to each driver.

  The LED writing control circuit (image data transfer control means) 51 starts a strobe signal STB for causing each driver of each LED head 26a to 26c to light its LED element for that time, a clock CLK for data transfer, and data transfer. A reset signal RESET, a signal for selecting data, a load signal LOAD for switching light amount correction and normal image data, and the like are output.

  The LED writing control circuit 51 transfers the image data to each driver of each LED head 26a to 26c, and each driver latches the image data transferred inside to turn on / off each LED element. I do.

  In FIG. 1 again, the fixing unit 6 includes a heating roller heated to a predetermined fixing temperature and a pressure roller pressed against the heating roller, and a toner image conveyed from the image forming unit 5 is formed. The transfer sheet 21 is heated and pressurized while being conveyed to fix the toner image on the transfer sheet 21 and the fixed transfer sheet 21 is discharged to the paper discharge unit 7.

  The paper discharge unit 7 includes paper discharge rollers 7a and 7b. The paper discharge rollers 7a and 7b discharge the fixed transfer paper 21 onto the paper discharge tray 14 with the paper discharge rollers 7a and 7b.

  The image reading unit 8 includes a roller 31, a contact sensor 32, a white roller 33 and a roller 34 disposed at positions facing the contact sensor 32, and the document set on the document table 11 is transferred by the roller 31. It is conveyed between the contact sensor 32 and the white roller 33. The image reading unit 8 performs main scanning and sub-scanning on the document by the contact sensor 32 while the document conveyed between the contact sensor 32 and the white roller 33 by the roller 31 is transported by the white roller 33, the roller 31 and the roller 34. Scan the original image. That is, the contact sensor 32 irradiates the original with reading light from the light source (for example, LED), photoelectrically converts reflected light including image information reflected by the original, and outputs an analog image signal. The image reading unit 8 discharges the document that has been read onto the document discharge tray 16 by the roller 34. The white roller 33 is used for shading correction that corrects unevenness due to illumination unevenness and sensitivity unevenness of each pixel of the contact sensor 32, and the digital copying apparatus 1 is in close contact with the white roller 33 when it is read. Shading correction is performed using the data output from the sensor 32 as shading data (white reference data).

  The digital copying apparatus 1 is configured as a circuit block as shown in FIG. 2, and includes the image reading unit 8, the image forming unit 5, the operation unit 15 and the like, and the image processing unit 40 and the like. Yes.

  The image reading unit 8 includes the contact sensor 32, an image amplification circuit 81, an A / D conversion circuit 82, a shading correction circuit 83, an image processing circuit 84, a synchronization control circuit 85, a reading control circuit 86, and a scanner drive. The analog image signal of the document read by the contact sensor 32 is input to the image amplification circuit 81. The image amplification circuit 81 amplifies the analog image signal input from the contact sensor 32 and outputs it to the A / D conversion circuit 82, and the A / D conversion circuit 83 outputs the analog image signal amplified by the image amplification circuit 81. It is converted into multi-value digital image data for each pixel and output to the shading correction circuit 83. The shading correction circuit 83 takes in the multi-value digital image data converted by the A / D conversion circuit 82 in synchronization with the clock input from the synchronization control circuit 85, and the light amount unevenness, contact glass contamination, and the sensitivity of the contact sensor 32. Distortion due to unevenness or the like is corrected and output to the image processing circuit 84. The image processing circuit 84 converts the multivalued digital image data subjected to the shading correction by the shading correction circuit 83 into digital image data (digital recording image data). To the image memory unit 41 of the image processing unit 40.

  The image processing unit 40 includes an image memory unit 41, a system control unit 42, a drive control circuit 43, and the like, and the image forming unit 5 includes the LED heads 26a, 26b, and 26c and the LED write control circuit 51. And a printer driving unit 52.

  Digital image data from the image processing circuit 84 of the image reading unit 8 is written in the image memory unit 41 of the image processing unit 40, and the image data written in the image memory unit 41 is read by the synchronization signal clock. 5 to the LED write control circuit 51.

  The system control unit 42 performs overall control of the digital copying apparatus 1, performs transfer control of image data in the reading control circuit 86, the image memory unit 41, and the LED writing control circuit 51, and also drives the drive control circuit 43. Then, the scanner driving unit 87 and the printer driving unit 52 are controlled to drive a motor or the like, thereby smoothly controlling the conveyance of the document and the transfer paper 21.

  The image forming unit 5 transfers the digital image data from the image memory unit 41 to the LED writing control circuit 51 by the synchronization signal clock, and the LED writing control circuit 51 transfers the transferred digital image data in units of one pixel. Are converted into bits and output to the LED elements of the LED heads 26a, 26b, and 26c to control the light emission of the LED elements.

  The flow of the digital image data from the image memory unit 41 to the LED writing control circuit 51 is as follows. The 2-bit image data of the even (E) and the odd (O) from the image memory unit 41 is 2 lines in parallel at 25 MHz. It is sent to the LED write control circuit 51. The digital storage image data sent to the LED write control circuit 51 in two lines is once combined into one line in the LED write control circuit 51, and then the specifications of each LED head 26a, 26b, 26c. Is converted to a format adapted to the above, and finally transferred to each LED head 26a, 26b, 26c.

The operation unit 15 includes an operation panel 61 for performing various operations for causing the digital copying apparatus 1 to perform an operation, and an operation control circuit 62. The operation control circuit 62 stores the operation content of the operation panel 61 in the image processing unit 40. The information is transferred to the system control unit 42 and information from the system control unit 42 is displayed on the display unit of the operation panel 61.
[LED writing control circuit 51]
Hereinafter, the LED write control circuit 51 will be described. Specifically, the LED write control circuit 51 has a circuit configuration as shown in FIG. 4, and includes an image data input unit 90, a first FPGA control unit 91, a second FPGA control unit 92, and six A group SRAMs 93A_1. 93A_6 and six B-group SRAMs 93B_1 to 93B_6, an image data RAM unit 93, an image data delay unit 94 including FM (field memories) 94a to 94c, a light amount correction ROM unit 95, a double copy RAM unit 96, a download unit 97, A reset circuit unit (RESET IC) 98 and the like are provided. Hereinafter, each part of the LED writing control circuit 51 will be described.
<Image data input unit 90>
The image data input unit 90 receives a 2-bit image signal even (PKDE), odd (PKDO), and timing signal from the image memory unit 41, and these signals are the low-voltage operation signal element LVDS driver of the image memory unit 41. Has been converted from parallel to serial. Therefore, the image data input unit 90 uses an LVDS receiver to convert a serial signal into a parallel signal, two image signals PKDE (1..0), PKDO (1..0), a 25 MHz clock XPCLK, and The timing signals XPLSYNC, XPLGATE, and XPFGATE_IPU are input to the first FPGA control unit 91.

The first FPGA control unit 91 synchronizes the timing signals XPLSYNC and XPFGATE_IPU with the internal clock of the first FPGA control unit 91, delays it by the image signal processing time, and outputs it to the second FPGA control unit 92 as RLSYNC and RFGATE.
<Image Data RAM Unit 93>
The first FPGA control unit 91 internally latches and delays the input image signal, and then processes the image signal as ED (1..0) and OD (1..0) as the SRAM address signal ADRA (10... 0) and BADR (10...) Are transferred to the six group A SRAMs 93A_1 to 93A_6 and the group B SRAMs 93B_1 to 93B_6 of the image data RAM unit 93 at 25 MHz.

  That is, the LED write control circuit 51 includes six SRAMs 93A_1 to 93A_6 as the A group, and stores the image data for one main scanning line, and the image data of the first division of the LED head 26a in the SRAM 93A_1 of the A group. Then, the image data of the second division of the LED head 26a is stored in the SRAM 93A_2 of the A group, the image data of the first division of the LED head 26b is stored in the SRAM 93A_3 of the A group, and the LED head is stored in the SRAM 93A_4 of the A group. 26b, the image data of the second division of the LED head 26c is stored in the SRAM 93A_5 of the A group, and the image data of the second division of the LED head 26c is stored in the SRAM 93A_6 of the A group. To do.

  The image data sequentially stored in the six A group SRAMs 93A_1 to 93A_6 at 25 MHz are sequentially read out from the six A group SRAMs 93A_1 to 93A_6 at 4.75 MHz and read out from the A group SRAM 93A_1 and the A group SRAM 93A_2. The image data of the LED head 26a is input to the second FPGA control unit 92 as SODA1 (3..0), SODA2 (3..0), SODB1 (3..0), and SODB2 (3..0). The image data of the LED head 26b read from the A group SRAM 93A_3 and the A group SRAM 93A_4 and the image data of the LED head 26c read from the A group SRAM 93A_5 and the A group SRAM 93A_6 are FM94a to 94c of the image data delay unit 94 or the first one. 1 sent to the FPGA controller 91

  The LED write control circuit 51 reads the image data of the next line to the B group SRAM 93B_1 to 93B_6 while reading the image data from the six A group SRAMs 93A_1 to 93A_6, and the group A SRAMs 93A_1 to 93A_6. Similarly, store.

The above-described read and write operations are performed between the lines by toggling the group A SRAMs 93A_1 to 93A_6 and the group B SRAMs 93B_1 to 93B_6.
<Image data delay unit 94>
As shown in FIG. 3, since the A3 width LED heads 26a, 26b, and 26c are arranged in a staggered manner in the optical writing unit 26, the LED head 26b is mechanically laid out based on the LED head 26a. Upper, it is shifted in the sub-scanning direction.

  Therefore, when the image signals output from the group A SRAMs 93A_1 to 93A_6 and the group B SRAMs 93B_1 to 93B_6 are simultaneously processed and transferred to the LED head 26b, the LED head 26b may be connected to the LED head 26a depending on the LPH specifications. Printing is shifted in the scanning direction.

  Therefore, the LED write control circuit 51 corrects such a mechanical shift by using the LED head 26b output from the A group SRAM 93A_3, the A group 93A_4, the B group SRAM 93B_3, and the B group SRAM 93B_4 at 4.75 MHz. Two lines of image data are written into the FM 94a of the image data delay unit 94 in the order of transfer lines at 100 lines (fixed) at 4.75 MHz. Next, the LED writing control circuit 51 reads out image data from the FM 94a at 4.75 MHz in the order of writing, and simultaneously writes (variable) the number of lines corresponding to the amount shifted to the cascaded FM 94b. Next, the LED write control circuit 51 reads out the image data at 4.75 MHz in the order written from the FM 94b, and inputs the read image data to the second FPGA control unit 92 as FMOD2 (7.0.0).

  Therefore, the image data to the LED head 26b is delayed by the number of lines corresponding to the amount deviated from the LED head 26a. The number of lines to be delayed varies depending on the component accuracy and assembly variation of the LED head 26b. Therefore, the LED write control circuit 51 can control in units of one line (42.3 μm). .

  Further, as shown in FIG. 3, the optical writing unit 26 has the three A3 width LED heads 26a, 26b, and 26c arranged in a staggered manner, so that the LED head 26c is connected to the LED head 26a. As a reference, they are attached while being shifted in the sub-scanning direction on the mechanical layout.

  Therefore, depending on the specifications of LPH, when image data output from the six A group SRAMs 93A_1 to 93A_6 and the six B group SRAMs 93B_1 to 93B_6 are simultaneously processed and transferred to the LED head 26c, The LED head 26c is printed out of alignment in the sub-scanning direction.

Therefore, the LED write control circuit 51 corrects such a mechanical deviation by dividing the LED head 26c output from the A group SRAMs 93A_5 and 93A_6 and the B group SRAMs 93B_5 and 93B_6 at 4.75 MHz. The image data is written in FM94c by the number of lines corresponding to the amount of deviation at 4.75 MHz in the order of transfer lines. Next, the LED write control circuit 51 reads out image data from the FM 94c at 4.75 MHz in the order written in the FM 94c, and inputs the image data to the second FPGA control unit 92 as FMOD3 (7..0). Therefore, the image data to the LED head 26c is delayed by the number of lines corresponding to the amount of deviation. The number of lines to be delayed varies depending on the component accuracy and assembly variation of the LED head 26c, and can be controlled in units of one line (42.3 μm).
<Light intensity correction ROM unit 95>
In the LED writing control circuit 51, the LED heads 26a, 26b, and 26c have a light amount containing correction data for each LED element and LED array chip correction data for each LED element group in order to correct variation in light amount of each LED element. Light quantity correction ROMs 95a to 95c are mounted in the correction ROM unit 95. When the power of the digital copying apparatus 1 is turned on, the light quantity variation correction data of the light quantity correction ROMs 95a to 95c is transferred to the LED heads 26a, 26b, and 26c. To do.

  That is, when the power is turned on and after the LED write control circuit 51 is reset, the LED write control circuit 51 first receives the address from the second FPGA control unit 92 from the light amount correction ROM 95a mounted in the LED head 26a. The signals are read sequentially from “0000H” by the signal HOSEIADR (12.0), and the light amount correction data is input to the second FPGA control unit 92 as HOSEID (4..0). The LED write control circuit 51 latches the data “0000h” inside the second FPGA control unit 92 and simultaneously transfers the data “0001h” to the LED head 26 a at 9.5 MHz. This process is repeated up to the number of correction data to correct the light amount of the LED head 26a.

  When the LED write control circuit 51 transfers the light amount correction data to the LED head 26a and corrects the light amount of the LED 26a in this way, the light amounts of the LED heads 26b and 26c are sequentially similar to the LED head 26a. Make corrections.

  The light quantity correction data transferred in this way is held inside the LED heads 26a, 26b, and 26c unless the LED heads 26a, 26b, and 26c are turned off.

Further, when the light quantity correction ROM unit 95 including the light quantity correction ROMs 95a to 95c is built in the LED heads 26a, 26b, and 26c in the LPH specification, the SEL signal, the RESET signal, and the RESET signal of the light quantity correction ROMs 95a to 95c, By sending a control signal such as a data latch signal, the light amount of the LED heads 26a, 26b, and 26c can be corrected.
<Double copy RAM unit 96>
In addition, the digital copying apparatus 1 prints an image up to 420 mm (A2 vertical size) in the main scanning direction twice on the same 841 mm (A0 vertical size) sheet, thereby improving the productivity of copying and printer functions. It has a double copy function to double.

At the time of this double copy, the digital copying apparatus 1 transfers the image data (E [1..0], O [1..0]) from the image memory unit 41 to the LED write control circuit 51 at 1/2 or less of XPLSYNC. In order to transfer, dubbing operation of image data is performed in one XPLSYNC using this. That is, the LED write control circuit 51 receives the image signals (E [1..0], O [1..0]) sent from the image memory unit 41 at 25 MHz from the first FPGA control unit 91. 1.0) and ODW (1..0) are transferred to the double copy RAM unit 96 together with the address signal WADR (13..0) and the image data is stored in the double copy RAM unit 96 at the same time. The data is stored in the six group A SRAMs 93A_1 to 93A_6 of the unit 93. The LED writing control circuit 51 reads out the image data stored in the double copy RAM unit 96 simultaneously with the end of storing the image data from the image memory unit 41, inputs it to the first FPGA control unit 91, and sends it from the image memory unit 41. In the same manner as the image data thus obtained, the six A group SRAMs 93A_1 to 93A_6 are additionally read. Accordingly, the six A group SRAMs 93A_1 to 93A_6 store one main scanning line of the double copy image. The LED write control circuit 51 performs the connection between the lines by toggling the six group A SRAMs 93A_1 to 93A_6 and the six group B SRAMs 93B_1 to 93B_6.
<Download unit 97>
The LED write control circuit 51 includes a download unit 97 that stores a write control program, and the download unit 9 includes, for example, an EPROM (Erasable and Programmable ROM). In this way, the download unit 97 includes the first FPGA control unit 91 and the second FPGA control unit 92 which are SRAM (Static RAM) type CPLDs, and the first FPGA control unit 91 is turned off when the power is turned off. This is because, when the write control program in the second FPGA control unit 92 is completely erased and the power is turned on, it is necessary to download (configure) this write control program every time. That is, when the power is turned on, the LED write control circuit 51 sequentially transfers the program as DOWNLOAD from the download unit 97 to the first FPGA control unit 91 and the second FPGA control unit 92 as serial data, and performs the download.
<Reset circuit 98>
Further, the LED write control circuit 51 also includes a reset circuit 98, and initializes the system. That is, the reset circuit 98 outputs the system reset signal RESET when the power is turned on and when the voltage drop of the power supply of the LED write control circuit 51 occurs. The system reset signal RESET is input to the first FPGA control unit 91 and the second FPGA control unit 92, and the first FPGA control unit 91 and the second FPGA control unit 92 reset the internal counter based on the system reset signal RESET, respectively. Perform system initialization.

The system control unit 42 transmits the control signal input data bus LDATA (7..0), the address bus LADR (6..0), the latch signals VDBCS, XPFGATE_IOB, XPSGATE, and XXLGATE to the first FPGA control unit 91 and the first FPGA control unit 91. By inputting to the 2FPGA control unit 92, setting / control of writing conditions (existence of double copying, writing paper size, etc.) to the LED writing control circuit 51 is performed.
[First FPGA Control Unit 91, Second FPGA Control Unit 92]
Next, control of the internal circuit of the LED write control circuit 51 will be described based on FIG. 5 which is a circuit block diagram of the first FPGA control unit 91 and FIG. 6 which is a circuit block diagram of the second FPGA control unit 92.

  The first FPGA control unit 91 performs control to write and read each 2-bit even data and odd data from the image memory unit 41 of the image processing unit 40 to the SRAM, and to select the test pattern and transfer data. The necessary gate signal is generated. The second FPGA control unit 92 synthesizes one line of 2-bit even-odd data stored in the SRAM groups 93A_1 to 93A_6 and 93B_ to 93B_6 under the control of the first FPGA control unit 91, and further combines the 2-bit data with 5-bit data. Is converted to and transferred to the LED head 26a.

  That is, in FIG. 5, the first FPGA control unit 91 includes a signal selection unit 101, a register 102, a data input thinning unit 103, a test pattern generation unit 104, a selector 105, a double copy control unit 106, a data format conversion unit 107, and an SRAM. A write control unit 108, an SRAM read control unit 109, a field memory write control unit 110, a block switching control unit 111, a write pulse generation unit 112, an address selector 113, and the like are provided. The data input thinning unit 103 includes A signal from the image memory unit 41 is input, and a signal from the system control unit 42 is input to the signal selector unit 101 and the register 102.

In FIG. 6, the second FPGA control unit 92 includes a data input unit 121, a selector 122, a register 123, a format conversion unit 124, a test pattern generation circuit 125, a γ correction / binarization unit 126, a γ correction / a joint light amount correction / A binarization unit 127, a γ correction / binarization unit 128, a P sensor 129, a transfer control unit 130, a strobe output control unit 131, a light amount correction ROM read control unit 132, a field memory read control unit 133, and the like are provided.
[First FPGA control unit 91]
Hereinafter, each part of the first FPGA control unit 91 will be described in order.
<Data input thinning unit 103>
The data input thinning unit 103 converts the target pixel in consideration of the data before and after the target pixel. A condition for turning on the thinning of the data input thinning unit 103 is when the thinning signal from the system control unit 42 is input HighH to the register 102.
<Signal Select Unit 101>
The signal selection unit 101 selects and outputs the transfer reference clock XPCLK and the TEST_CLK provided in the internal circuit by selecting the write clock SWCLK to the SRAM write control unit 108 based on the EXTMOD signal from the register 102. A main scanning write start signal WSTTP is generated from the write clock SWCLK using an internal LSYNC circuit and output. Further, the signal selection unit 101 designates the range by the register image mask ISREG and sets the image region signal XPLGATE from the image processing unit 40 as a mask effective region signal PLGATEIS as a main scanning write start signal. Selection with WSTTP is performed by TESTMOD from the register 102, and a write start signal WRSTART signal for main scanning is output. Further, the signal selection unit 101 selects the sub-scan gate signal in the register TESTMOD using the image period signal XPFGATE output from the image processing unit 40 and IOBFGATE synchronized with the internal LSYNC, and the writing period. The signal SWFGATE is output. Next, the signal selection unit 101 selects the TESTMOD signal from the register 102 using the write start signal WSTTP generated by the internal LSYNC generation circuit and the main scanning pixel start signal XPLSYNC output from the image processing unit 40, Output. The signal selector 101 synchronizes the output signal with the internal reference clock SYSCLK by the SYSCLK synchronization circuit, and outputs it as a read main scanning image start signal RLSYNC. Further, the signal selector 101 reads out the read main scanning image start signal RLSYNC in synchronization with the writing period signal SWFGATE selected by the one-line delay circuit, and outputs it as the image period signal RFGATE.

Then, the signal selection unit 101 generates each gate signal output by the above operation from the SRAM write control unit 108, the SRAM read control unit 109, the flock switching control unit 111, the double copy control unit 106, and the test pattern generation in the next stage. The data is transferred to the unit 104.
<Test pattern generation unit 104>
The test pattern generation unit 104 inputs the main scanning write start signal WSTTP and the sub scanning writing period signal SWFGATE generated by the signal selection unit 101 to the main scanning counter and the sub scanning counter, respectively, and the main scanning count value LCOUNT. Then, the sub-scan count value FCOUNT is generated, and the pattern is generated by combining the main scan count value LCOUNT and the sub-scan count value FCOUNT using an internal combinational circuit. The test pattern generation unit 104 selects each generated pattern by selecting a pattern from the register 102, outputs data TPDATA, converts it to 2 bits, and outputs it as 2 bit data PKEDTP and PKODTP. .
<Selector 105>
The selector 105 receives the 2-bit even data PKEDI3 / odd data PKODI3 output from the data input thinning unit 103 and the test pattern 2-bit even data PKEDTP / odd data PKODTP output from the test pattern generation unit 104. Are selected by the pattern selection signal input from the image processing unit 40 and transferred from the register 102, and data PKED4 and PKOD4 are output.
<Double Copy Control Unit 106>
The double copy control unit 106 inputs the transfer reference clock XPCLK, the write start signal WRSTART from the signal selection unit 101 and the double copy signal from the register 102 to the counter generation circuit, and the counter generation circuit counts the count set in the register. The counter synchronized with the transfer reference clock XPCLK is output. The double copy control unit 106 inputs the output signal to the SRAM write control unit 108, the SRAM read control unit 109, and the selector 105. The SRAM write control unit 108 receives a write start signal WRSTART from the counter and the signal selection unit 101 and a double copy signal from the register 102, and writes a write period signal to the A group SRAM 93A_1 to 93A_6 and the B group SRAM 93B_1 to 93B_6. WCP_WEN is output. The SRAM read control unit 109 receives the write period signal WCP_WEN to the group A SRAMs 93A_1 to 93A_6 and the group B SRAMs 93B_1 to 93B_6, and generates the SRAM read period signal WCP_REN after the signals are finished. The double copy control unit 106 outputs a control signal, a write signal WRW, a read signal RDW, and a counter WADR to the group A SRAMs 93A_1 to 93A_6 and the group B SRAMs 93B_1 to 93B_6 of the external circuit, which are output from the SRAM write control unit 108. The generation period signal WCP_WEN and the read period signal WCP_REN output from the SRAM read control unit 109 are generated by a combinational circuit, an inverting circuit, and a selector and output.

  The double copy control unit 106 uses the data input thinning unit 521 and the test pattern generation unit 104 to select and output data selected by the selector 105, PKED4 and PKOD4, and a write period signal from the SRAM write control unit 108. Select by WCP_WEN, the write start signal WRSTART and the write period signal SWFGATE from the signal selection unit 101 to be data PKED5 and PKOD5, and further select the input data by the write period signal WCP_WEN from the SRAM write control unit 108 To output data EDW and ODW. These data EDW and ODW are data of the A group SRAMs 93A_1 to 93A_6 and the B group SRAMs 93B_1 to 93B_6 which are external circuits. By doing so, it is possible to read from the A group SRAMs 93A_1 to 93A_6 and the B group SRAMs 93B_1 to 93B_6.

The double copy control unit 106 selects the input data by the SRAM read period signal WCP_REN to make the data PKEDD and PKODD, and further, the data PKEDD and PKODD and the input data PKED4 and PKOD4 are written from the SRAM write control unit 108. The selection is made by the double period signal WCP_WEN and the double copy signal from the register 102, and the final output data PKED and PKOD are output.
<Block switching control unit 111>
The block switching control unit 111 receives an input write clock SWCLK, a readout main scanning image start signal RLSYNC, and a readout image period signal RFGATE, and outputs a block signal BLOCK that switches for each main scanning line when the readout image period is valid. The group A SRAM 93A_1 to 93A_6 and the group B SRAM 93B_1 to 93B_6 are switched.
<SRAM write control unit 108>
The SRAM write control unit 108 inputs the input write clock SWCLK, the reference synchronization clock SYSCK, and the clear signals MCLR and SRESET from the register 102 to the reset pulse generation circuit, outputs the reset pulse SRESRP, and performs the SRAM write control. Input to the write address counter. The SRAM write control unit 91 determines which group A SRAMs 93A_1 to 93A_6, B based on the write start address HSTADRS and the write start SRAM block HSTBLK from the register 102, and the write end address HENADRS and the write end SRAM block HENBLK. Processing to start the write operation from the group SRAMs 93B_1 to 93B_6, and under what conditions to shift to the next group A SRAM 93A_1 to 93A_6, group B SRAM 93B_1 to 93B_6, or to return to the start position, Write processing sequencer seq_p is output. The SRAM write control unit 108 inputs the SRAM write process sequencer seq_p to the write address counter, and sets and outputs the SRAM write address counter WCNT by the SRAM write process sequencer seq_p.
<SRAM read control unit 109>
The SRAM read control unit 109 inputs the reference synchronization clock SYSCK, the read main scanning image start signal RLSYNC, and the read image period signal RFGATE to the read counter generation circuit, divides the reference synchronization clock SYSCK by 4, and sets the SRAM read timing counter SRRDCCK. To be input to the SRAM read control circuit. Further, the SRAM read control circuit receives the SRAM write processing sequencer seq_p, the SRAM write address counter WCNT, and the reset pulse SRESRP from the SRAM write control unit 108, and outputs the SRAM read address counter RCNT. The SRAM read control unit 109 outputs an output SRAM read address counter RCNT, a line switching BLOCK signal from the block switching control unit 111, a read main scanning image start signal RLSYNC, and a read image period signal RFGATE to a read enable signal generation circuit. The A group SRAM read signal RDA and the B group SRAM read signal RDB which are signals indicating which of the A group SRAM 93A_1 to 93A_6 and the B group SRAM 93B_1 to 93B_6 are to be used are output.
<Write pulse generator 112>
The write pulse generation unit 112 of the first FPGA control unit 91 uses an SRAM write processing sequencer seq_p from the SRAM write control unit 108 and a line switching BLOCK signal from the block switching control unit 111 using a write pulse generation circuit. For example, if the BLOCK signal is High, the write enable signals WEA1 to 6 are selected, and the corresponding A group SRAM 93A_1 to 93A_6 and B group SRAM 93B_1 to 93B_6 of the SRAM write processing sequencer seq_p are set to High enable. Make it bull. Therefore, the write enable signals WEA1 to 6 are sequentially enabled in the first main scanning line, and the write enable signals WEB1 to 6 are sequentially enabled in the next line. Go. The write pulse generation unit 112 inputs the output write enable signals WEA1 to 6 and WEB1 to 6 to the write signal generation circuit, and the write signal generation circuit synchronizes with the input write clock SWCLK. A group SRAM write signals WRA1 to 6 and B group SRAM write signals WRB1 to 6 are output. Further, the write pulse generation unit 112 outputs an A group SRAM buffer gate signal ASEL and a B group SRAM buffer gate signal BSEL by using the SRAM write block signal as a gate signal in order to validate the SRAM write signal.
<Address selector 113>
The address selector 113 of the first FPGA control unit 91 uses the block signal BLOCK to be switched for each main scanning line when the read image period output from the block switching control unit 111 is valid, and the SRAM write output from the SRAM write control unit 108. The group A SRAM address AADR and the group B SRAM address BADR are output by switching the line block signal between the built-in address counter WCNT and the RCNT output from the SRAM read control unit 109.
<Data format conversion unit 107>
As shown in FIG. 7, the data format conversion unit 107 of the first FPGA control unit 91 synthesizes the input 2-bit even data PKED and the input 2-bit odd data PKOD into one line, and then divide1 which is the set value of the register 102 Then, one line of data is divided into a specified number, and the portion of the divided one line data is determined by the application to be designated as one LPH (LED heads 26a to 26c). Here, regarding the data corresponding to the LEDs 26a and 26c, the data format conversion unit 107 reverses the order of the data because the LEDs 26a and 26c are arranged in opposite directions. Thereafter, the data format conversion unit 107 divides the data by means of “divide 2”, sets the divided data group as “Block”, and finally sets the divided block as “minimum data block Data” by “divide 3”.

  Next, the data format conversion unit 107 rearranges the DATA groups. That is, as shown in FIG. 8, the Data Get interval [5: 0] data block DATA is taken out every new Data Get interval [5: 0] data blocks DATA from each block set value of the register 102, and a new data block DATA is extracted. A data group. As shown in FIG. 9, the data format conversion unit 107 extracts the DATA in the ascending order and the descending order according to the register value of Data Order assigned to each data block. The data format conversion unit 107 extracts Data Get number [5: 0] data blocks DATA from all the Blocks, arranges them in order, and finally sets them as divided line data.

As an example performed with each register value, it can be shown as in Example 1 and Example 2 in FIG. 10. In the case where there is no need for delay and seam correction in the register DOFF, it is directly The data is sent to the 2FPGA control unit 92.
<Field memory write control unit 110>
The field memory write control unit 110 of the first FPGA control unit 91 generates gate signals for writing data corresponding to the LED heads 26b and 26c output from the group A SRAMs 93A_1 to 93A_6 and the group B SRAMs 93B_1 to 93B_6 to the FMs 94a to 94c. 2 blocks are used for the data of the LED head 26b. After 100 lines of data are written (stored) in the FM 94a, the data is transferred to the FM 94b. The data of the LED head 26c is Write to FM94c.

  The field memory write control unit 110 first transfers data from the FM 94a to the FM 94b with a delay of 100 lines by the sub-scanning counter generation circuit using the reference synchronization clock SYSCK, the read main scan image start signal RLSYNC, and the read image period signal RFGATE. A line counter SSDCNT for output is output. Next, the field memory write control unit 110 is an FM write address reset signal generation circuit using the SRAM read address counter RCNT from the SRAM read control unit 109 and the SRRDCK obtained by dividing the reference clock SYSCK by 4, and performs read main scanning. When the image start signal RLSYNC is turned on, an FM write address reset signal FMWRST is generated and output so that the addresses of the FMs 94a to 94c are initialized. The field memory write control unit 110 outputs the FM write address reset signal FMWRRST with the converter, and outputs the write address reset signals FM2RSTW and FM3RSTW of FM94a, 94b and FM94c. When the write address reset of the FMs 94a to 94c is input, the field memory write control unit 110 turns on a write enable signal to write data to the FM 94a, as will be described later. When data is written (stored), the read address reset signal FMRRST1 of the FM 94a is output to the read address reset signal generation circuit of the FM 94a in order to reset the read address of the FM 94a and transfer the data to the FM 94b. The field memory write control unit 110 also causes the FM write enable signal generation circuit to output an FM write enable signal FMWE in order to determine the FM write on time. The field memory write control unit 110 converts the FM write enable signal FMWE into FM94b and 94c write enable signals FM2WE and FM3WE using a converter, and FM94c read enable signal FM3RE. use. Further, the field memory write control unit 110 generates the clock FMWCLK using the SRRDCK obtained by dividing the reference clock SYSCK by 4 as the clock of the FMs 94a to 94c, and inputs the output clock FMWCLK to the converter. The write clock signals FM2SWCK and FM3SWCK of FM94b and 94c are changed and output, and also used as the read clock FM2SRCK of FM94b.

The field memory write control unit 110 inputs the read signals RDA and RDB of the A group SRAMs 93A_1 to 93A_6 and the B group SRAM SRAMs 93B_1 to 93B_6 from the SRAM read control unit 109 to the write buffer gates. Select whether to write data or to write B group SRAM data, FM94a A group SRAM data write buffer gate FM1DASEL, FM94a B group SRAM data write buffer gate FM1DBSEL, FM94c A group SRAM data write buffer The B group SRAM data write buffer gate FM3DBSEL for the gate FM3DASEL and FM94c is output. At this time, the gate signal is toggled between the A group and the B group.
<Register 102>
The register 102 of the first FPGA control unit 91 receives the address / data from the image processing unit 40, latches it with the circuit internal clock SYSCLK, determines the input data, and outputs it.
[Second FPGA control unit 92]
Next, the second FPGA control unit 92 will be described with reference to FIG. In the second FPGA control unit 92, the internal clock SYSCK is input to each control block as a reference synchronization clock, and the entire flow is to generate the read gate signal of the data of the FM 94a to 94c and transfer it to the LED heads 26a to 26c. The gate signal is generated. The second FPGA control unit 92 converts the 2-bit even-odd data of the LED head 26a stored in the SRAM 93A_1 to 93A_6, 93B_1 to 93B_6 group from the control in the first FPGA control unit 91, and further performs gamma conversion, The data is binarized and transferred to the LED head 26a. Similarly, the second FPGA control unit 92 reads the data of the LED head 26b and the LED head 26c stored in the FMs 94a to 94c, formats the 2-bit even-odd data like the data of the LED head 26a, and further The 2-bit data is converted into 5-bit data, binarized, and transferred to the LED heads 26b and 26c, respectively. Hereinafter, each block of the second FPGA control unit 92 will be described in detail.
<Test pattern generation circuit 125>
The test pattern generation circuit 125 performs internal counter / LED head transfer control of the second FPGA control unit 92, and uses the reference synchronous clock SYSCK and the read main scanning image start signal RLSYNC output from the first FPGA control unit 91. The main scan LCNT and the sub scan FCNT are output, and the sub scan counter value of the output of the main scan counter value and the sub scan counter value to be output is input to the test pattern generation circuit, and the test pattern generation circuit The internal test pattern TPDATA is output from the scan counter value. On the other hand, the main scanning counter is passed to the P sensor generation, the LED head transfer signal 1, the LED head transfer signal 2, and the clock generation circuit. The P sensor generation circuit 129 uses the main scanning counter for image density detection, and outputs it only to a specified portion of the A block of the LED head 26b. The output signal is PSLGATE. In the LED head transfer signal generation 1, the LED head image data clock effective range signal HCLKEN is output and sent to the LED head transfer signal 2, and the clock HCLK is output only in the image data effective range to the LED heads 26a to 26c. The clock generation circuit outputs a divided clock CLKEN95 obtained by clearing the reference clock SYSCK for each main scanning counter and a CLKEN475 obtained by dividing the reference clock SYSCK by four.
<Light intensity correction ROM read control unit 132>
The light amount correction ROM read control unit 12 of the second FPGA control unit 92 has two light amount correction control methods for the external ROM and the built-in ROM depending on the LRTYPE of the register 123 because the specifications differ for each LED head. select.

  First, the control for the external ROM will be described. When the power of the digital copying apparatus 1 is turned on, the reference synchronization clock SYSCK, the read main scanning image start signal RLSYNC output from the first FPGA control unit 91, and the light amount correction start signal KHSTAT are input to the light amount correction counter FCNT, and the sub-scanning counter KHFCNT is set. Generate and output. Based on the output sub-scanning counter KHFCNT, the light amount correction ROM read control unit 132 outputs access enable signals ROMCE1, 2, and 3 to the ROMs 95a to 95c of the light amount correction PROM unit 95 by the selector / comparison circuit. Output. The three signals are light amount correction PROM access signals for three LED heads 26a to 26c, and perform light amount correction control from the LED head 26a. Further, in this circuit, a light amount correction end signal KHSTCLR and a light amount correction start signal KHLOADR for each of the LED heads 26a to 26c are generated and output as a gate signal. Address settings of the light quantity correction ROMs 95a to 95c are generated by a ROM address generation circuit. In the data transfer in the light quantity correction ROMs 95a to 95c, the light quantity correction data for one LED head is stored, and the LED heads 26a to 26c are of a two-part data transfer method, and therefore the light quantity correction ROMs 95a to 95c. The data stored in is alternately arranged with the first data of the A block and then the first data of the B block. Therefore, the data ROMDT 5-bit data is input to the ROM output data latch circuit, latched by the counter KHLCNT three times, and the data is divided into LED head A block light amount correction data KHDATA1R and B block light amount correction data KHDATA2R, and output simultaneously. . Further, a transfer clock to the LED heads 26a to 26c is generated by the light amount correction effective range circuit, and CTCKR is output.

  Next, a light amount correction method when the LED heads 26a to 26c have a built-in ROM will be described. In the LED heads 26a to 26c having the built-in ROM, it is necessary to send control signals such as a light amount correction select signal, a light amount correction reset signal, a data latch signal, and a strobe clock from the LED head control LSI.

In this case, as shown in FIGS. 11 and 12, these signals are generated by reading the set values for each signal from the register 123, transferred to the LED heads 26a to 26c, and light quantity correction is performed. These controls are selected by the register 123 by the ROMTYPE as shown in FIG.
<Field memory read control unit 133>
The field memory read control unit 133 of the second FPGA control unit 92 delays the data corresponding to the connection of the LED head 26b and the LED head 26c connected to the LED head 26a with the position shifted in the rotation direction of the photosensitive member 24. The gate signals of FM94a to 94c are generated. Although not shown, the field memory read control unit 133 includes a reset signal generation unit for starting reading of the FMs 94b and 94c, and a field memory writing range, which includes a counter sub-scanning circuit, an FM delay period generation circuit, and a field memory read reset generation circuit. The circuit comprises an FM read enable signal part by a circuit and a clock for reading data stored in FMs 94a to 94c by a counter and a circuit for delaying to the rear end of the delayed sub-scan. The reference clock SYSCK is input to each circuit. The field memory read control unit 133 first outputs the read main scanning image start signal RLSYNC generated by the first FPGA control unit 91 to the read start signal generation, and outputs a read signal RLSYNCD synchronized with the clock. The field memory read control unit 133 inputs the read signal RLSYNCD output from the read start signal generation to each block, and in the counter, the reference clock SYSCK is counted and reset by the synchronized read signal RLSYNCD, and then counted up again. .

  The field memory read control unit 133 generates reset signals (FM3RSTR and FM2RSTR) for starting reading of the FMs 94b and 94c as follows. That is, the readout image period signal RFGATE generated by the first FPGA controller 91 and the readout signal RLSYNCD synchronized with the clock are input to the counter sub-scanning circuit, the counter DLCNT2 for FM94b and the counter DLCNT3 for FM94c are output, and FM FM The read reset generation circuit and the circuit for delaying to the rear end of the delayed sub-scan are provided. Further, the field memory read control unit 133 uses the FM2DL for sub-scanning FM and the FM3DL for FM set in the register 123 by key input from the operation unit 15 and the read signal RLSYNC2D synchronized with the clock to the FM delay period generation circuit. Then, the FM delay period generation circuit outputs delay period enable signals DLCNT2 and 3 for FM94b (for LED head 26b) and FM94c (for LED head 26c), respectively. By inputting the signals output from the counter sub-scanning circuit, the FM delay period generating circuit, and the counter to the FM read reset generating circuit, the FM read reset generating circuit outputs the FM read reset signal FM2RSTR and the FM read reset signal FM3RSTR. . The pulse width is 4 counts output from the counter.

  The field memory read control unit 133 generates the clocks (FM3SRCK and FM2SRCK2) of the FMs 94b and 94c as follows. That is, the RDCK output from the counter is input, and the clocks FM3SRCK and FM2SRCK2 divided by 4 by the counter are output.

  The field memory read control unit 133 generates the read ranges (FM3RE and FM2RE2) of the FMs 94b and 94c as follows. That is, the FM read range generation circuit of the field memory read control unit 133 receives the RDCK output from the counter, counts up four clocks as one count, and clears the count with the maximum number of pixels. FM94c data read enable signal FM3RE and FM94b data read enable, which are valid for a read image period signal RFGATE generated by the 1FPGA controller 91 and a delayed DMSK2 period of the LED head 26b described later. Bull signal FM2RE2 is output. Therefore, the sub-scan delay start can be set, and the sub-scan delay FGATE of each of the LED heads 26a to 26c is generated by the FM delay FGATE generation circuit in order to delay the sub-scan by the amount output later. DMSK1, DMSK2, and DMSK3 are output.

Then, the sub-scanning of the three LED heads 26a to 26c can be adjusted by the sub-scanning delay setting values FM2DL for FM and FM3DL for FM set in the register 123 by the key input on the operation unit 15, and the adjusting method The default values are set on the assumption that the LED heads 26a to 26c are mechanically fitted, and a sub-scan adjustment test chart (grating, etc.) is output, taking the deviation into account. Further, key input is performed from the operation unit 15.
<Data input unit 121>
The selection unit 122 performs the main read operation during the read image period by the data switching signal generation circuit that receives the reference synchronous clock SYSCK, the read main scanning image start signal RLSYNC output from the first FPGA control unit 91, and the read image period signal RFGATE. A signal BANKSEL that is switched using the scanning image start signal as a trigger is output and input to the data converter. The data conversion unit receives the clocks CLKEN95 and CLKEN475 generated by the test pattern generation circuit 125 and the sub-scan delays FGATE and DMSK2 of the LED head 26b. The data is data for the LED head 26a, and is output from the A group SRAMs 93A_1 and 93A_2 of the SRAM group and the B group SRAMs 93B_1 and 93B_2. The data of 2 pixels output from the A group SRAM 93A_1 is 4 bits. Data SODA1 is input as a unit. Hereinafter, the data is 2 bits of 2-pixel data output from the B group SRAM 93B_1, 4-bit SODB1, and 2 bits of 2-pixel data output from the A group SRAM 93A_2 is 4-bit SODA2, B The data for 2 pixels in 2-bit units output from the group SRAM 93B_2 is assumed to be 4-bit SODB2. Here, the data format for the A group SRAM 93A_1 and the B group SRAM 93B_1 will be described. For the 4-bit data SODA1 and SODB1 of the A group SRAM 93A_1 and the B group SRAM 93B_1, the selection unit 122 selects the output SODA1 from the A group SRAM 93A_1 and outputs the 4-bit data SODA1 while the data switching signal BANKASEL is High. To do. Next, the selector 122 selects the output SODB1 from the group B SRAM 93B_1 and outputs this 4-bit data SODB1 during the period when the data switching signal BANKASEL is Low. The selector 122 performs the same control as described above and outputs the 4-bit output data SODA2 from the A group SRAM 93A_2 and the 4-bit output data SODB2 from the B group SRAM 93B_2.
<Format conversion unit 124>
The format conversion unit 124 performs data format conversion of the LED head 26b and data format conversion of the LED heads 26a to 26c. Hereinafter, data format conversion for the LED head 26b will be described. The format converter 124 receives the reference synchronization clock SYSCK, the read main scanning image start signal RLSYNC output from the first FPGA controller 91, the read image period signal RFGATE, and the clocks CLKEN95 and CLKEN475 generated by the test pattern generation circuit 125. The 8-bit data from the FM 94b is converted and output as data of the LED head 26b. In the 8-bit output data from the FM 94b, the upper 4 bits are 2-bit data from the SRAM 93A_4 and the SRAM 93B_4, and the lower 4 bits are 2-bit data from the SRAM 93A_3 and the SRAM 93B_3. The format conversion unit 124 outputs the former upper 4 bits to the output data IMDATA2 and the latter lower 4 bits to the output data IMDATA1. The format conversion unit 124 performs conversion from 4-bit data to 2-bit serial in the same manner as the conversion for the LED head 26a, and similarly for the LED head 26c.
<Γ correction / binarization unit 126 and γ correction / binarization unit 128>
The gamma correction / binarization units 126 and 128 for the image data of the LED heads 26a and 26c are data gamma correction / bit conversion and binarization of the LED head 26a, and data gamma correction / bit conversion and binarization of the LED head 26c. I do. Hereinafter, the data gamma correction / bit conversion / binarization in the LED head 26a will be described.

  As shown in FIG. 13, the γ correction / binarization unit 126 has a γ correction / γ table, and, when the data value is “00”, the input 2-bit data IMDATA1 is a 5-bit gamma set in the register. Output as correction data GMDT0, if the data value is "01", output as register-set 5-bit gamma correction data GMDT1, and if the data value is "10", register-set 5-bit gamma correction data When the data value is “11”, it is output as 5-bit gamma correction data GMDT3 set in the register. Further, the γ correction / binarization unit 126 performs the same processing on the (output 5-bit data GMMODAT1) input data IMDATA2, and normally converts the 2-bit data into 5-bit data as described above.

  Further, as shown in FIG. 14, the γ correction / binarization unit 126 turns the binarization ON / OFF by setting the register and sets the binarization threshold value, thereby reducing the binarization threshold value. Is converted to 1-bit data, such as “1” when the threshold value is equal to or greater than “0”, and binarized output is performed.

Further, the γ correction / binarization unit 129 processes the data of the LED head 26 c in the same manner as the case of the γ correction / binarization unit 126.
<Joint Light Amount Correction / Binarization Unit 127>
The γ correction / joint light amount correction / binarization unit 127 of the second FPGA control unit 92 performs gamma correction / bit conversion and joint light amount correction on the data of the LED head 26b.

  That is, first, the bit conversion processing by the joint light amount correction / binarization unit 127 will be described. The joint light amount correction dots are ADJL, ADJL2, ADJL3, ADJR, ADJR2, and ADJR3. The register values used are the LED head 26a-26b joint correction ENABLE signal CNADJL, and the LED head 26a-26b joint part detection signal. CNDAT1, image correction data ADJL1 for the target pixel “01”, image correction data ADJL2 for the target pixel “10”, image correction data ADJL3 for the target pixel “11”, and LED head 26b-26c joint correction ENABLE signal CNADJR, LED head 26b-26c joint detection signal CNDAT2, image correction data ADJR1 for the target pixel “01”, image correction data ADJR2 for the target pixel 10, and image for the target pixel “11” Correction data ADJR3 and That.

  The effective image range of the LED head 26b is fixed, and several hundred dots on the left and right sides of the total number of dots of the LED head 26 are blank areas. Therefore, from this value, the most extreme dot of the left and right image effective areas of the LED head 26b can be obtained.

  Then, the γ correction / joint light quantity correction / binarization unit 127 includes the reference synchronization clock SYSCK, the read main scanning image start signal RLSYNC output from the first FPGA control unit 91, the read image period signal RFGATE, and the test pattern generation circuit 125. A counter is generated from the clock CLKEN95 generated by the above, and when the counter value is counted to the count value at the left end using the counter, the signal CNADAT1 is set to High. This signal CNADAT1 becomes a joint light amount correction effective dot of the A block data IMDATA1 of the LED head 26b. Further, the γ correction / joint light quantity correction / binarization unit 127 sets the signal CNADAT2 to High when the counter value reaches the right end count. This signal CNADAT2 becomes a joint light amount correction effective dot of the B block data IMDATA2 of the LED head 26b.

  The gamma correction / joint light quantity correction / binarization unit 127 gives the generated joint light quantity correction effective dot signals CNADAT1 and CNADAT2 to the data converter, and further, the 5-bit gamma correction set by the register 123. Similarly to the data GMDT0, GMDT1, GMDT2, and GMDT3, the 5-bit joint light amount correction data ADJL1, 2, 3, ADJ2L1, 2, and 3 set by the register 123 and the 2-bit data IMDATA1 and IMDATA2 output from the data input unit 121 are also included. input. As shown in FIG. 13, the data converter of the γ correction / joint light amount correction / binarization unit 127 has a register set when the data value is “00” with respect to the input 2-bit data IMDATA1. When 5-bit gamma correction data GMDT0 is output and the data value is "01", the 5-bit gamma correction data GMDT1 set in the register is output. When the data value is "10", the 5-bit set in the register is output. The gamma correction data GMDT2 is output. When the data value is “11”, the 5-bit gamma correction data GMDT3 set in the register is output. Further, the γ correction / joint light quantity correction / binarization unit 127 processes (output 5-bit data GMMODAT1) input data IMDATA2 in the same manner, and usually converts 2-bit data into 5-bit data as described above. Convert.

  Next, the joint light amount correction processing by the γ correction / joint light amount correction / binarization unit 127 will be described. The LED heads 26a to 26c are arranged with their end portions overlapped, and data can be shifted by the SRAM control of the first FPGA controller 91, but the SRAM control by the first FPGA controller 91 is Data is shifted in units of 1 bit and 1 bit or less. If the terminal bit data of the LED head 26a and the image effective start bit data of the LED head 26b are separated by 1 dot or less, white streaks may occur in the image.

  Therefore, since the effective image range of the LED head 26b is fixed, the image data of the LED head 26a is moved to the 1-dot LED head 26b side by the SRAM control of the first FPGA control unit 91, and the image data is overlapped.

  If it does in this way, a black stripe will occur this time. Therefore, when key input is performed from the operation unit 15 and the joint light amount correction mode is set from the register 123, the input 2-bit data IMDATA1 is input by the joint light amount correction effective dot signal CNDATA1 of the A block data IMDATA1 of the LED head 26b generated above. 5 is variable in accordance with the joint light amount correction data of the registers ADJL1, 2, 3, ADJ2L1, 2, 3. The joint light amount correction data of the registers ADJL1, 2, 3 and ADJ2L1, 2, 3 correspond to the input data “01”, “10”, “11”, respectively, and can convert MAX 32 values. Therefore, when a black streak occurs, if the input 2-bit data IMDATA1 at the left end is “11”, the black light streak becomes inconspicuous by converting the register joint light amount correction data to a small value by 5 bits. The same control can be performed at the right end portion of the LED head 26b.

In addition, the γ correction / joint light amount correction / binarization unit 127 turns ON binarization by register setting, and as shown in FIG. 14, less than the binarization threshold value is “0”, If the threshold value is greater than or equal to the binarized threshold value, the data is binarized into “1” and 1-bit data and binarized output is performed.
<Transfer Control Unit 130, Strobe Output Control Unit 131>
The data transfer control unit 130 and the strobe output control unit 131 that perform data transfer control to the LED heads 26a to 26c of the second FPGA control unit 92 will be described with reference to FIGS.

  First, as shown in FIG. 15, the SEL signal, which is the LPH data transfer light quantity correction / print selection signal, is set to High active or Low active depending on the H / L of the register setting SELTYPE. In addition, while image data is being sent, either TYPEI which is always fixed to be active or TYPEII which is made inactive for a certain period every time divided print data transfer ends is selected. When TYPE II is selected, the inactive time is also set by SEL Interval.

  Next, the number of parallel bits at the time of transferring data to be sent to each LPH block is set according to how many parallels are set by the register parallel.

  In addition, as shown in FIG. 16, the transfer clock is set at the time of transfer by setting the clock duty, the clock cycle, and the number of pulses according to the register setting values Clock Duty, Clock Cycle, and Clock Number, and the data width of the transfer data. Is set by Data Width.

  Regarding the format of data transfer at the time of transfer, first, in the register format, it is selected whether it is binary data or multi-value data, and how many bits are transferred in parallel with this binary data or multi-value data information. By properly combining these, the data transfer specifications of each LPH are matched.

  FIG. 16 shows the case of binary data and para trans [3: 0] = 4, and FIG. 17 shows multi-value data of para trans [3: 0] = 5 and clock number [15: 0]. ] = N.

  Next, the reset signal will be described. As shown in FIGS. 18 and 19, the reset signal is set by setting the register reset signal to High active or Low active by RH / L. The active time is also set by Reset Duty.

  As shown in FIG. 18 and FIG. 19, the data latch signal is set by setting the active time in the register setting DH reset Duty and the number of signals in the DH reset number.

  Furthermore, the setting of the strobe light emission signal of each LPH will be described with reference to FIG. By setting the STB Num, STB Clk Num, STB (1-n) Duty, and STB (1-n) Cycle of the register settings, the number of strobe light emission signals, the number of clocks of the strobe light emission signal, the duty of the strobe light emission signal The cycle is arbitrarily set to cope with the difference in the number of strobe signals and the difference in the strobe signals due to the difference in the LPH specifications.

  Finally, various timings are set in the register as shown in FIG. 20, so that it can be adapted to the specification of the timing of each LPH.

  As described above, in the digital copying apparatus 1 of this embodiment, the three LED heads 26a to 26c, which are the light emitting element array of the optical writing unit 26, are displaced by a predetermined amount in the sub scanning direction orthogonal to the main scanning direction. The LED write control circuit 51 is arranged in a zigzag pattern with a predetermined amount overlapping in the main scanning direction, and the data write pattern, light amount correction / print selection signal, data transfer method, data transfer clock, reset signal, strobe light emission Based on various signals such as a pattern and a latch signal for image data, image data for one line is divided for each LED head 26a to 26c and transferred to each LED head 26a to 26c. Each LED is driven to perform main scanning. These data division patterns, light intensity correction / print selection signals, data transfer methods, data transfer clocks, etc. A plurality of signals such as a reset signal, a strobe light emission pattern, and a latch signal for image data are prepared in advance, and these signals are combined to make the LED heads 26a to 26c binary, multivalued, static light emission, dynamic light. It is operated according to various specifications such as automatic light emission.

  Accordingly, the driving method of the static lighting method and the dynamic lighting method, the type of light emitting element array (LED head) such as binary or multi-value, and the light emitting element array for a wide image forming apparatus that may be used in the future. In the case of using a light-emitting element array or the like that realizes writing for a wider image forming apparatus by connecting a plurality of light-emitting elements, even if there is a difference in specifications among the light-emitting element arrays, it can be widely handled.

  Further, the LED writing control circuit 51 of the digital copying apparatus 1 of the present embodiment can arbitrarily set the number of divisions of image data in the main scanning direction from the outside. Can respond.

  Further, the LED writing control circuit 51 of the digital copying apparatus 1 of the present embodiment extracts and rearranges image data every arbitrary number of data in the main scanning direction, and how many data the rearrangement is performed. Since it can be arbitrarily set from the outside, it can correspond to the data format specifications of various light emitting element arrays.

  Further, the LED writing control circuit 51 of the digital copying apparatus 1 of the present embodiment includes a division number setting function for arbitrarily setting the number of divisions in the main scanning direction of the image data, and the image data in the main scanning direction. It is provided with a sort setting function that can be fetched and rearranged every arbitrary number of data, and arbitrarily set from the outside how many data is to be sorted, and any of these division number setting function and sort setting function Is executed according to the selection, so that it is possible to more appropriately cope with the specifications of the data formats of various light emitting element arrays.

  Further, the LED writing control circuit 51 of the digital copying apparatus 1 of the present embodiment can arbitrarily set whether the light amount correction / print selection signal is set to High active or Low active from the outside. It is possible to cope with the specifications of the LPH data transfer light quantity correction / print selection signal of the element array.

  Further, the LED writing control circuit 51 of the digital copying apparatus 1 of the present embodiment can arbitrarily set the number of times of high / low switching of the light amount correction / print selection signal from the outside, so that the LPH data of various light emitting element arrays can be set. It is possible to cope with the specifications of the transfer light quantity correction / print selection signal, and the light quantity correction can be performed between the lines, density unevenness can be suppressed, and the image quality can be improved.

  Furthermore, since the LED writing control circuit 51 of the digital copying apparatus 1 of the present embodiment can arbitrarily set the number of bits for parallel transfer of image data from the outside, the specification for LPH data transfer of various light emitting element arrays is satisfied. Can respond.

  Further, the LED writing control circuit 51 of the digital copying apparatus 1 of the present embodiment can arbitrarily set the effective width time of each data from the outside, so that it corresponds to the LPH data transfer specification of each light emitting element array. Can do.

  Furthermore, since the LED write control circuit 51 of the digital copying apparatus 1 of the present embodiment can arbitrarily set the cycle and duty of the data transfer clock from the outside, it corresponds to the specifications of the LPH data transfer clock of various light emitting element arrays. can do.

  Further, the LED writing control circuit 51 of the digital copying apparatus 1 of this embodiment can arbitrarily set the number of clocks of the data transfer clock from the outside according to the number of data to be transferred, so that the LPH data of various light emitting element arrays can be set. It can correspond to the specification of the transfer clock.

  Furthermore, since the LED writing control circuit 51 of the digital copying apparatus 1 of the present embodiment can arbitrarily set the reset signal to be high active or low active from the outside, resetting of various light emitting element arrays is possible. It can correspond to the specifications of the signal.

  Further, the LED writing control circuit 51 of the digital copying apparatus 1 according to the present embodiment can arbitrarily set the time for activating the reset signal from the outside, so that it corresponds to the reset signal specifications of various light emitting element arrays. Can do.

  Furthermore, since the LED writing control circuit 51 of the digital copying apparatus 1 of the present embodiment can arbitrarily set the number of strobe light emission signals from the outside, it corresponds to the specifications of the strobe light emission signals of various light emitting element arrays. Can do.

  Further, the LED writing control circuit 51 of the digital copying apparatus 1 of this embodiment can arbitrarily set the pulse period and duty of the strobe light emission signal from the outside for each LED head 26a to 26c. The specification of the strobe light emission signal of the array can be supported.

  Furthermore, since the LED writing control circuit 51 of the digital copying apparatus 1 of the present embodiment can arbitrarily set the number of pulses of the latch signal of the image data from the outside, the specification of the print data latch signal of various light emitting element arrays Can respond.

  Further, the LED write control circuit 51 of the digital copying apparatus 1 of the present embodiment can arbitrarily set the pulse width of the latch signal of the image data from the outside, so that the specification of the print data latch signal of various light emitting element arrays is satisfied. Can respond.

  The digital copying apparatus 1 of the present embodiment includes the optical writing unit 26 having such an LED writing control circuit 51 in the image forming unit 5, so that the light emitting element array of the optical writing unit 26 is used. Even if a certain LED head changes the type of light emitting element array (LED head) such as a driving method of a static lighting method and a dynamic lighting method, binary, multi-value, etc., the specification of the light emitting element array after the change In addition to being able to respond appropriately, a plurality of wide light emitting element arrays can be connected to appropriately support wider writing.

  The invention made by the present inventor has been specifically described based on the preferred embodiments. However, the present invention is not limited to the above, and various modifications can be made without departing from the scope of the invention. Needless to say.

  When optical writing is performed by arranging a plurality of light emitting element arrays such as LED heads in a staggered manner, an optical writing apparatus that appropriately corresponds to light emitting element arrays with various specifications and image formation using this optical writing apparatus It can be applied to the device.

1 is a schematic front view of a digital copying apparatus to which an embodiment of an image writing apparatus and an image forming apparatus of the present invention is applied. FIG. 2 is a block diagram of the main part of the digital copying apparatus in FIG. 1. The top view which shows the arrangement | sequence of the LED head of FIG. FIG. 3 is a circuit block diagram of the LED write control circuit of FIG. 2. The circuit block block diagram of the 1st FPGA control part of FIG. The circuit block block diagram of the 2nd FPGA control part of FIG. FIG. 6 is an operation explanatory diagram of a data format conversion unit of the first FPGA control unit of FIG. 5. Explanatory drawing of the data rearrangement process by the data format conversion part of the 1st FPGA control part of FIG. Explanatory drawing of the order which takes out data by the data rearrangement process of FIG. The figure which shows the specific example of the data rearrangement process of FIG. The timing chart which shows the light quantity correction process by the light quantity correction ROM read-out control part of the 2nd FPGA control part of FIG. Explanatory drawing of the setting of the various signals in the light quantity correction process of FIG. Explanatory drawing of the (gamma) correction process by the (gamma) correction and binarization part of the 2nd FPGA control part of FIG. Explanatory drawing of the binarization process by the (gamma) correction | amendment / binarization part of the 2nd FPGA control part of FIG. FIG. 7 is an explanatory diagram of setting of a SEL signal in data transfer processing of the transfer control unit and the strobe output control unit of FIG. 6. Explanatory drawing of the data transfer process of binary data in the transfer control part and strobe output control part of FIG. Explanatory drawing of the data transfer process of the multi-value data in the transfer control part and strobe output control part of FIG. FIG. 7 is an explanatory diagram of setting of a data latch signal in the transfer control unit and the strobe output control unit of FIG. 6. FIG. 7 is an explanatory diagram of setting of a reset signal, a data hold signal, and a strobe signal in the transfer control unit and the strobe output control unit of FIG. 6. Explanatory drawing of the timing of the data transfer in the transfer control part and strobe output control part of FIG. The top view which shows the arrangement | positioning state of the LED head of the conventional optical writing part.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Digital copying apparatus 2 Main body housing | casing 3 Paper feed part 4 Conveyance part 5 Image formation part 6 Fixing part 7 Paper discharge part 7a, 7b Paper discharge roller 8 Image reading part 10 Manual feed tray 11 Document base 12 Separation charger 13 Conveyance tank 14 Discharge Paper tray 15 Operation unit 21 Transfer paper 22 Paper feed table 23 Registration roller 24 Photoconductor 25 Charging unit 26 Optical writing unit 26a, 26b, 26c LED head 27 Development unit 28 Transfer unit 29 Cleaning unit 31 Roller 32 Adhesion sensor 32 Adhesion sensor 33 White roller 34 Roller 40 Image processing unit 41 Image memory unit 42 System control unit 43 Drive control circuit 51 LED write control circuit 52 Printer drive unit 61 Operation panel 62 Operation control circuit 81 Image amplification circuit 82 A / D conversion circuit 83 Shading Correction circuit 84 Image processing circuit 85 Synchronous system Control circuit 86 Reading control circuit 87 Scanner drive unit 90 Image data input unit 91 First FPGA control unit 92 Second FPGA control unit 93A_1 to 93A_6 A group SRAM
93B_1 to 93B_6 Group B SRAM
93 Image data RAM unit 94 Image data delay unit 94a to 94c FM (field memory)
95 Light quantity correction ROM section 96 Double copy RAM section 97 Download section 98 Reset circuit section 101 Signal selection section 102 Register 103 Data input thinning section 104 Test pattern generation section 105 Selector 106 Double copy control section 107 Data format conversion section 108 SRAM writing Control unit 109 SRAM read control unit 110 Field memory write control unit 111 Block switching control unit 112 Write pulse generation unit 113 Address selector 121 Data input unit 122 Selector 123 Register 124 Format conversion unit 125 Test pattern generation circuit 126 γ correction / 2 Value conversion unit 127 γ correction / joint light amount correction / binarization unit 128 γ correction / binarization unit 129 P sensor 130 transfer control unit 131 strobe output control unit 132 light amount correction OM read control unit 133 the field memory read controller

Claims (17)

  A plurality of light emitting elements arranged in one direction and an image forming means for forming an image of light emitted from the light emitting element array on the photosensitive member; The light emitting element array units are arranged in a zigzag pattern with a predetermined amount of displacement in the sub-scanning direction and a predetermined amount of overlap in the main-scanning direction. Based on various signals such as a reset signal, a strobe light emission pattern, and a latch signal for image data, the image data for one line is divided for each light emitting element array unit and transferred to each light emitting element array unit to emit the light. In the image writing apparatus for driving each light emitting element of the element array unit, the data division pattern, the light amount correction / print selection signal, and the data transfer method A plurality of various signals such as a data transfer clock, a reset signal, a strobe light emission pattern, and an image data latch signal are prepared in advance, and these light emitting element arrays are combined into binary, multi-value, static light emission, An image writing apparatus that operates in accordance with various specifications such as dynamic light emission.   2. The image writing apparatus according to claim 1, wherein the number of divisions in the main scanning direction of the image data can be arbitrarily set from the outside.   The image writing apparatus is characterized in that the image data can be taken out every arbitrary number of data in the main scanning direction and rearranged, and the number of data to be rearranged can be arbitrarily set from the outside. The image writing apparatus according to claim 1.   The image writing apparatus has a division number setting function for arbitrarily setting the number of divisions in the main scanning direction of the image data from the outside, and takes out the image data every arbitrary number of data in the main scanning direction and rearranges the image data And a rearrangement setting function for arbitrarily setting the number of data to be rearranged from the outside, and executing either the division number setting function or the rearrangement setting function according to the selection. The image writing apparatus according to claim 1.   5. The image writing apparatus according to claim 1, wherein the light quantity correction / print selection signal can be arbitrarily set from the outside as to whether the light amount correction / print selection signal is set to High active or Low active. The image writing apparatus according to 1.   5. The image document according to claim 1, wherein the image writing device can arbitrarily set a high / low switching frequency of the light quantity correction / print selection signal from the outside. 6. Device.   7. The image writing apparatus according to claim 1, wherein the image writing apparatus can arbitrarily set the number of bits for parallel transfer of the image data from the outside.   8. The image writing apparatus according to claim 1, wherein the image writing apparatus can arbitrarily set an effective width time of each data from the outside.   9. The image writing apparatus according to claim 1, wherein the image writing apparatus can arbitrarily set the cycle and duty of the data transfer clock from the outside.   10. The image according to claim 1, wherein the image writing device can arbitrarily set the number of clocks of the data transfer clock from the outside in accordance with the number of data to be transferred. Writing device.   11. The image according to claim 1, wherein the image writing device can arbitrarily set whether the reset signal is made high active or low active from the outside. Writing device.   12. The image writing apparatus according to claim 1, wherein the image writing apparatus can arbitrarily set a time for activating the reset signal from the outside.   13. The image writing apparatus according to claim 1, wherein the number of strobe light emission signals can be arbitrarily set from the outside.   14. The image writing apparatus according to claim 1, wherein the strobe light emission signal pulse period and duty can be arbitrarily set from the outside for each light emitting element array. Image writing device.   15. The image writing apparatus according to claim 1, wherein the image writing apparatus can arbitrarily set the number of pulses of the latch signal of the image data from the outside.   16. The image writing apparatus according to claim 1, wherein the image writing apparatus can arbitrarily set a pulse width of a latch signal of the image data from the outside. The image writing unit irradiates the photosensitive member with light to form an electrostatic latent image on the photosensitive member, and finally transfers the developer image obtained by developing the electrostatic latent image with a developer onto a sheet. In the image forming apparatus to be formed, the image writing apparatus according to any one of claims 1 to 16 is used as the image writing unit.

Images