JP2006203019A - Semiconductor device and method for forming the same - Google Patents

Abstract

An object of the present invention is to reduce the occurrence of leakage current resulting from Cu diffusion and suppress overhang.
An insulating barrier film and an interlayer insulating film are sequentially formed on a lower layer wiring formed on a semiconductor substrate (not shown). Next, the interlayer insulating film 103 is removed, and a via 104 reaching the insulating barrier film 102 and a trench 105 reaching the via 104 are formed. Next, after the modified layer 200 is formed on the exposed portion of the interlayer insulating film 103, the modified layer 200 is removed to form rounds 105b, rounds 105a, and rounds 104a. Next, the insulating barrier film 102 on the bottom surface of the via 104 is removed. Next, a barrier metal film 106 is deposited on the via 104 and the trench 105, and resputtering is performed. Next, a Cu film 107 is deposited on the barrier metal film 106, and the Cu film 107 and the barrier metal film 106 are polished to form a via plug 108 and an upper wiring 109.
[Selection] Figure 2

Description

  The present invention relates to a semiconductor device having a wiring formed by a damascene method and a method for forming the same.

  In recent years, along with the high integration of semiconductor integrated circuits and the reduction in chip size, miniaturization and multilayering of wiring have been promoted. As the wiring pitch is narrowed, the RC delay due to the increase in the wiring resistance and inter-wiring capacitance has become impossible to ignore. For this reason, it is necessary to reduce the electric parasitic resistance generated in the wiring when the miniaturization of the semiconductor integrated circuit is advanced. In order to reduce the electrical parasitic resistance of the wiring, it is necessary to reduce the specific resistance of the wiring material or the relative dielectric constant of the interlayer insulating film.

  The wiring of devices with a gate length of 0.13 μm has been changed from aluminum (Al) wiring to copper (Cu) wiring in order to reduce the specific resistance of the wiring material. By adopting Cu wiring, the specific resistance of the wiring was reduced to about 2/3 of the conventional one.

However, in Cu wiring, since Cu atoms diffuse quickly into an insulating film such as a silicon oxide film (SiO ₂ film), Cu atoms enter the transistor and cause breakdown of the transistor. When Cu atoms diffuse between the wirings and an unexpected bridge structure is formed between the wirings, a phenomenon such as deterioration of the dielectric strength between the wirings occurs. It was necessary to provide a barrier film for preventing atomic diffusion. Currently, a conductive barrier film (hereinafter referred to as tungsten nitride (WN), tantalum nitride (TaN), titanium nitride (TiN) or the like is generally formed on the bottom and side surfaces of the Cu wiring to cover the periphery of the wiring Cu film. Used as a barrier metal film).

  Note that when Cu wiring is employed, it is difficult to form the wiring by etching as compared with the Al wiring, and therefore Cu wiring is formed by the damascene method. That is, after a groove having a wiring pattern is formed in the deposited interlayer insulating film, the wall surface of the groove is covered with a barrier metal film, and then a Cu film is embedded in the groove by electrolytic plating, and then CMP (Chemical Mechanical Polishing: The barrier metal film and the Cu film are polished and planarized by a chemical mechanical polishing method to complete the Cu wiring (see, for example, Patent Document 1).

  Hereinafter, a semiconductor device having wiring formed by a conventional damascene method will be described.

FIG. 6 is a cross-sectional view showing a semiconductor device having wiring formed by a conventional damascene method. As shown in FIG. 6, a semiconductor device having a wiring formed by a conventional damascene method includes a lower layer wiring 1 formed on a semiconductor substrate (not shown) and an insulating film 2 formed on the lower layer wiring 1. A via 3 connected to the lower wiring 1 formed in the insulating film 2, a trench 4 connected to the via 3 formed on the insulating film 2, and a barrier formed so as to cover the via 3 and the trench 4. A metal film 5 and a Cu film 6 formed so as to fill the via 3 and the trench 4 from above the barrier metal film 5 are provided. Here, the barrier metal film 5 and the Cu film 6 in the via 3 form a via plug 7, and the barrier metal film 5 and the Cu film 6 in the trench 4 form an upper wiring 8.
JP-A-7-130681

  However, the following problems occur in a semiconductor device having wiring formed by a conventional damascene method. In a semiconductor device having a wiring formed by a conventional damascene method, a barrier metal film or a Cu seed layer overhangs at an upper portion of a via side surface and an upper portion of a trench side surface as the wiring pattern is miniaturized. That is, the barrier metal film is thick at the upper part of the via side surface and the upper part of the trench side surface, and the barrier metal film is thin at the lower part of the via side surface and the lower part of the trench side surface. For this reason, as shown in FIG. 7, it becomes difficult to embed the Cu film 6 by electrolytic plating, and burying defects such as voids occur inside the via 3. In addition, the step coverage (coverability) of the barrier metal film is lowered at the lower portion of the via side surface. Therefore, after depositing the barrier metal film, resputtering is performed in which atoms are knocked out from the surface of the barrier metal film deposited on the bottom surface of the via and re-deposited on the side surface of the via. However, as shown in FIG. 8, not only the barrier metal film 5 on the bottom surface of the via 3 but also the barrier metal film 5 on the bottom surface of the trench 4 is peeled off during resputtering. The barrier metal film 5 is completely removed. As a result, the Cu atoms of the Cu film 6 diffuse from the corners A into the insulating film 2, thereby causing a problem of leakage current and the like.

  The present invention provides a semiconductor device capable of suppressing the diffusion of Cu by improving the step coverage of the barrier metal film, particularly at the corner A at the bottom of the trench, and suppressing the occurrence of voids by suppressing the overhang. An object is to provide a method for forming the same.

  The semiconductor device according to the present invention is a semiconductor device having an insulating film formed on a semiconductor substrate and wiring embedded in a trench formed in the insulating film, and has a round corner at the bottom of the trench.

  Thereby, since the step coverage of the barrier metal film at the corner of the bottom surface of the trench can be improved, Cu diffusion can be suppressed.

  Further, a semiconductor device according to the present invention is formed on a lower layer wiring formed on a semiconductor substrate, an insulating film formed on the lower layer wiring, a via plug embedded in a via formed in the insulating film, and an insulating film. In the semiconductor device having the upper layer wiring buried in the trench, the corner of the bottom of the trench is rounded.

  Thereby, since the step coverage of the barrier metal film at the corner of the bottom surface of the trench can be improved, Cu diffusion can be suppressed.

  In addition, the semiconductor device according to the present invention has a rounded shoulder portion of the via.

  Thereby, the overhang of the upper part of the via side surface can be suppressed, and the generation of voids can be suppressed.

  In the semiconductor device according to the present invention, the insulating film includes an insulating barrier film and an interlayer insulating film formed on the insulating barrier film.

  In the semiconductor device according to the present invention, the interlayer insulating film is a SiOC film.

  Moreover, the curvature of the roundness at the bottom of the trench is k = 7.7 × E7 [1 / m] or less.

  The method of manufacturing a semiconductor device according to the present invention includes a step (a) of forming an insulating film on a semiconductor substrate, a step (b) of forming a trench in the insulating film, and a surface of the insulating film after the step (b). Forming a modified layer in step (m), removing the modified layer (n), after step (n), depositing a barrier metal film to cover the trench (c), and step (C) is followed by a step (d) of depositing a Cu film so as to fill the trench.

  Thereby, the step coverage of the barrier metal film, particularly at the corners of the bottom surface of the trench, can be improved and Cu diffusion can be suppressed. Moreover, generation | occurrence | production of a void can be suppressed by suppressing the overhang of a trench side surface upper part.

  The method for manufacturing a semiconductor device according to the present invention includes a step (a) of forming a lower layer wiring on a semiconductor substrate, a step (b) of forming an insulating film on the lower layer wiring, and forming a via in the insulating film. A step (c), a step (d) for forming a trench connected to a via in the insulating film, a step (m) for forming a modified layer on the surface of the insulating film after the step (d), and a modified layer A step (n) of removing the Cu, a step (e) of depositing a barrier metal film so as to cover the via and the trench after the step (n), and a Cu film so as to embed the via and the trench after the step (e) (F).

  Thereby, the step coverage of the barrier metal film, particularly at the corners of the bottom surface of the trench, can be improved and Cu diffusion can be suppressed. Moreover, generation | occurrence | production of a void can be suppressed by suppressing the overhang of a via side upper part and a trench side upper part.

  In the method for manufacturing a semiconductor device according to the present invention, ion irradiation or plasma irradiation is used in the step (m).

  In the method for manufacturing a semiconductor device according to the present invention, Ar gas is used for ion irradiation.

  In the method for manufacturing a semiconductor device according to the present invention, the plasma irradiation uses a gas that generates atoms or molecules containing any of O, N, and H.

In the method for manufacturing a semiconductor device according to the present invention, the atom or molecule containing any of O, N, or H is O ₂ or NH ₃ .

  In the method for manufacturing a semiconductor device according to the present invention, the step (b) includes a step (b1) of forming an insulating barrier film on the lower wiring and a step of forming an interlayer insulating film on the insulating barrier film ( b2).

  In the method for manufacturing a semiconductor device according to the present invention, the interlayer insulating film is a SiOC film.

  In the method for manufacturing a semiconductor device according to the present invention, the step (n) performs a wet etching process using a chemical solution of diluted hydrofluoric acid or buffered hydrofluoric acid.

  According to the present invention, the step coverage of the barrier metal film, particularly at the corners of the bottom of the trench, can be improved, the diffusion of Cu can be suppressed and the occurrence of leakage current can be reduced, the overhang can be suppressed and the generation of voids can be suppressed. Therefore, the reliability of the embedded wiring by the damascene method can be improved.

(First embodiment)
A semiconductor device according to a first embodiment of the present invention will be described. FIG. 1 is a cross-sectional view showing a semiconductor device according to the first embodiment of the present invention. As shown in FIG. 1, the semiconductor device according to the first embodiment of the present invention includes a lower layer wiring 101 formed on a semiconductor substrate (not shown) and an insulating barrier film formed on the lower layer wiring 101. 102, an interlayer insulating film 103 formed on the insulating barrier film 102, a via 104 having a round 104a at the shoulder and connected to the lower layer wiring 101, and a via 105 having a round 105b at the bottom corner A. A trench 105 to be connected, a barrier metal film 106 formed so as to cover the via 104 and the trench 105, and a Cu film 107 formed so as to fill the via 104 and the trench 105 are included. Here, the barrier metal film 106 and the Cu film 107 in the via 104 form a via plug 108, and the barrier metal film 106 and the Cu film 107 in the trench 105 form an upper wiring 109. In addition, the curvature of the shoulder 104 roundness 104a and the corner 105 roundness 105b of the bottom surface of the trench 105 is equal to or less than k = 7.7 × E7 [1 / m].

  According to the present invention, since the trench 105 has the roundness 105b at the corner A on the bottom surface, the step coverage of the barrier metal film 106 on the bottom surface of the trench 105, particularly at the corner A, can be improved. Thus, a highly reliable semiconductor device in which the barrier metal film 106 is not peeled off can be provided. Further, it is possible to provide a semiconductor device having a favorable embedded wiring in which overhang of the barrier metal film 106 is suppressed.

  In the semiconductor device according to the first embodiment, the dual damascene structure is shown, but a single damascene structure can be used.

(Method for Forming First Semiconductor Device According to First Embodiment)
A method for forming the first semiconductor device according to the first embodiment of the present invention will be described below. FIG. 2A to FIG. 3E are cross-sectional views showing respective steps of the first semiconductor device formation method according to the first embodiment of the present invention.

  First, as shown in FIG. 2A, a lower layer wiring 101 is formed on a semiconductor substrate (not shown) on which elements such as transistors are formed. Next, the insulating barrier film 102 is formed on the lower layer wiring 101 by the CVD method. Here, SiC is used for the insulating barrier film 102. Thereafter, an interlayer insulating film 103 is formed on the insulating barrier film 102 by a CVD method. Here, a carbon-containing silicon oxide film (SiOC film) is used as the interlayer insulating film 103.

  Next, as shown in FIG. 2B, a photomask (not shown) having a via pattern is deposited on the interlayer insulating film 103 by photolithography. Subsequently, dry etching is performed using this photomask to remove the interlayer insulating film 103 and form a via 104 connected to the insulating barrier film 102. Thereafter, the photomask is removed by ashing.

  Next, as shown in FIG. 2C, a photomask (not shown) having a trench pattern is deposited on the interlayer insulating film 103 by photolithography. Subsequently, dry etching is performed using this photomask to remove the interlayer insulating film 103 and form a trench 105 connected to the via 104. Thereafter, the photomask is removed by ashing.

Next, as shown in FIG. 2D, the exposed portion of the interlayer insulating film 103, that is, the upper surface of the interlayer insulating film 103, the side surfaces and the bottom surface of the trench 105, and the side surface of the via 104 are irradiated by ion irradiation. Perform reforming treatment. Here, ion irradiation is controlled by setting RF bias and pressure, and is performed with a depth of about 5 nm. In addition, argon (Ar) gas is used for ion irradiation. At this time, since the bonding force of Si—C is weaker than that of Si—O in the SiOC film, carbon (C) is desorbed from the interlayer insulating film 103 by Ar ion irradiation, and the surface of the interlayer insulating film 103 Then, the SiO _x modified layer 200 is formed.

Next, as shown in FIG. 2E, the upper surface of the interlayer insulating film 103, the side surfaces and the bottom surface of the trench 105, and the side surface of the via 104, in particular, the corner A of the bottom surface of the trench 105, the trenches are formed by wet etching. 105, and the modified layer 200 on the shoulder portion of the via 104 is removed, and the roundness 105b at the corner A on the bottom surface of the trench 105, the roundness 105a on the shoulder portion of the trench 105, and the roundness 104a on the shoulder portion of the via 104 Form. Here, the curvature of the roundness 105b, the roundness 105a, and the roundness 104a is k = 7.7 × E7 [1 / m] or less. In the wet etching, a chemical solution of diluted hydrofluoric acid or buffered hydrofluoric acid is used. At this time, since the SiO _x film generally has a higher etching rate than the SiOC film, only the SiO _x film is selectively removed.

  Next, as shown in FIG. 3A, the insulating barrier film 102 on the bottom surface of the via 104 is removed by dry etching.

  Next, as shown in FIG. 3B, a barrier metal film 106 is deposited so as to cover the via 104 and the trench 105 by sputtering. Here, tantalum (Ta) and tantalum nitride (TaN) are used as the barrier metal film 106. At this time, the barrier metal film 106 is overhanging at the opening of the via 104, and the thickness of the barrier metal film 106 is thick at the upper part of the side surface of the via 104, but is thin at the lower part of the side surface of the via 104. It has become.

  Next, as shown in FIG. 3C, atoms are knocked out from the surface of the barrier metal film 106 on the bottom surface of the via 104 by resputtering, and the barrier metal film 104 on the lower side surface of the via 104 is thinned. Redeposit.

  Next, as shown in FIG. 3D, a Cu film 107 is deposited so as to fill the via 104 and the trench 105 from above the barrier metal film 106 by metal plating.

  Next, as shown in FIG. 3E, the Cu film 107 and the barrier metal film 106 protruding from the trench 105 are polished by CMP to expose the interlayer insulating film 103 in a portion other than the trench 105, thereby forming the trench 105. The via plug 108 and the upper layer wiring 109 are formed while leaving the Cu film 107 and the barrier metal film 106 in the via 104.

  According to the first method for forming a semiconductor device of the first embodiment, since the corner 105 of the bottom surface of the trench 105 has the round 105b, in the step of depositing the barrier metal film 106 shown in FIG. The step coverage of the barrier metal film 106 on the bottom surface 105, particularly at the corner A, can be improved. 3C, the barrier metal film 106 on the bottom surface of the via 104 can be peeled off while the barrier metal film 106 on the bottom surface of the trench 105 can be left. Therefore, Cu diffusion can be suppressed and generation of leakage current can be reduced. Further, according to the first method for forming a semiconductor device according to the first embodiment, the shoulder portion of the via 104 has the round portion 104 a on the shoulder portion of the via 104 and the round portion 105 a on the shoulder portion of the trench 105. In addition, the protrusion of the interlayer insulating film 103 is eliminated from the shoulder portion of the trench 105, and overhang can be suppressed in the deposition process of the barrier metal film 106 shown in FIG. Thereby, in the Cu film 107 embedding step shown in FIG. 3D, the generation of voids can be reduced, and the Cu film 107 can be satisfactorily embedded by electroplating.

Although the dual damascene structure is shown in the first method for forming a semiconductor device according to the first embodiment, a single damascene structure can also be used. In the first method for forming a semiconductor device according to the first embodiment, ion irradiation is used as the modification treatment, but plasma irradiation may be used. In this case, the plasma irradiation is a gas that generates atoms or molecules containing any one of oxygen atoms (O), nitrogen atoms (N), and hydrogen atoms (H) such as oxygen (O ₂ ) and ammonia (NH ₃ ). Is used. By this plasma irradiation, C in SiOC reacts with the atoms or molecules containing any of the above O, N, or H, so that carbon monoxide (CO), carbon dioxide (CO ₂ ), hydrogen cyanide (HCN), or nitriding C can be desorbed as a gas such as carbon (CN).

(Method for Forming Second Semiconductor Device According to First Embodiment)
Next, a method for forming a second semiconductor device according to the first embodiment of the present invention will be described. FIG. 4A to FIG. 5E are cross-sectional views showing the respective steps of the method for forming the second semiconductor device according to the first embodiment of the present invention.

  First, as shown in FIG. 4A, a lower layer wiring 101 is formed on a semiconductor substrate (not shown) on which elements such as transistors are formed. Next, the insulating barrier film 102 is formed on the lower layer wiring 101 by the CVD method. Here, SiC is used for the insulating barrier film 102. Thereafter, an interlayer insulating film 103 is formed on the insulating barrier film 102 by a CVD method. Here, a SiOC film is used as the interlayer insulating film 103.

  Next, as shown in FIG. 4B, a photomask (not shown) having a via pattern is deposited on the interlayer insulating film 103 by photolithography. Subsequently, dry etching is performed using this photomask to remove the interlayer insulating film 103 and form a via 104 connected to the insulating barrier film 102. Thereafter, the photomask is removed by ashing.

  Next, as shown in FIG. 4C, a photomask 300 having a trench pattern is deposited on the interlayer insulating film 103 by photolithography. Subsequently, dry etching is performed using the photomask 300 to remove the interlayer insulating film 103 and form a trench 105 connected to the via 104. Thereafter, the photomask 300 is left.

Next, as shown in FIG. 4D, a modification process is performed on the exposed portions of the interlayer insulating film 103, that is, the side surfaces and the bottom surface of the trench 105 by ion irradiation using the photomask 300 as a mask. Here, ion irradiation is controlled by setting RF bias and pressure, and is performed with a depth of about 5 nm. Moreover, Ar gas is used for ion irradiation. At this time, since the bonding force of Si—C is weaker than the bonding force of Si—O in the SiOC film, C is detached from the interlayer insulating film 103 by Ar ion irradiation, and SiO is deposited on the surface of the interlayer insulating film 103. A modified layer 400 of _X is formed.

Next, as shown in FIG. 4E, by wet etching, the corners A of the bottom surface of the trench 105, the shoulder portions of the trench 105, and the shoulder portions of the via 104 are formed on the side and bottom surfaces of the trench 105. The modified layer 400 is removed, and a round A 105 b at the bottom of the trench 105, a round 105 a at the shoulder of the trench 105, and a round 104 a at the shoulder of the via 104 are formed. Here, the curvature of the round 105b, the round 105a, and the round 104a is k = 7.7 × E7 [1 / m] or less. In the wet etching, a chemical solution of diluted hydrofluoric acid or buffered hydrofluoric acid is used. At this time, since the SiO _x film generally has a higher etching rate than the SiOC film, only the SiO _x film is selectively removed. Further, the photomask 300 is also removed by wet etching.

  Next, as shown in FIG. 5A, the insulating barrier film 102 on the bottom surface of the via 104 is removed by dry etching.

  Next, as shown in FIG. 5B, a barrier metal film 106 is deposited so as to cover the via 104 and the trench 105 by sputtering. Here, Ta and TaN are used as the barrier metal film 106. At this time, the barrier metal film 106 is overhanging at the opening of the via 104, and the thickness of the barrier metal film 106 is thick at the upper part of the side surface of the via 104, but is thin at the lower part of the side surface of the via 104. It has become.

  Next, as shown in FIG. 5C, atoms are knocked out from the surface of the barrier metal film 106 on the bottom surface of the via 104 by resputtering, and the barrier metal film 104 on the lower side surface of the via 104 is thinned. Redeposit. Next, as shown in FIG. 5D, a Cu film 107 is deposited so as to fill the via 104 and the trench 105 from above the barrier metal film 106 by metal plating.

  Next, as shown in FIG. 5E, the Cu film 107 and the barrier metal film 106 that protrude from the trench 105 are polished by CMP, and the interlayer insulating film 103 is exposed to a portion other than the trench 105. The via plug 108 and the upper layer wiring 109 are formed while leaving the Cu film 107 and the barrier metal film 106 in the via 104.

  According to the second method for forming a semiconductor device of the first embodiment, since the corner 105 of the bottom surface of the trench 105 has the round 105b, in the step of depositing the barrier metal film 106 shown in FIG. The step coverage of the barrier metal film 106 on the bottom surface 105, particularly at the corner A, can be improved. 5C, the barrier metal film 106 on the bottom surface of the via 104 can be peeled off while the barrier metal film 106 on the bottom surface of the trench 105 can be left. Therefore, diffusion of Cu can be suppressed and generation of leakage current can be reduced. In addition, according to the second method for forming a semiconductor device according to the first embodiment, the shoulder of the via 104 has the round 104a on the shoulder of the via 104 and the round 105a on the shoulder of the trench 105. In addition, the protrusion of the interlayer insulating film 2 is eliminated at the shoulder portion of the trench 105, and overhang can be suppressed in the deposition process of the barrier metal film 106 shown in FIG. Thereby, in the Cu film 107 embedding step shown in FIG. 5D, the generation of voids can be reduced, and the Cu film 107 can be satisfactorily embedded by electroplating. Furthermore, according to the method for forming the second semiconductor device according to the first embodiment, in the ion irradiation process of the interlayer insulating film 103 shown in FIG. 4D, ion irradiation or plasma is performed with the photomask 300 left. Irradiation is performed, and the modified layer 400 is formed only on the bottom and side surfaces of the trench 105. Therefore, the top surface of the interlayer insulating film 103 is not removed in the wet etching process shown in FIG. The film thickness of the film 103 can be easily controlled. Further, according to the second method for forming a semiconductor device according to the first embodiment, since the photomask 300 is removed together with the modified layer 400 in the wet etching step shown in FIG. It is not necessary to remove the photomask 300 by ashing after the trench formation step shown in c), and the number of steps can be reduced.

Although the dual damascene structure is shown in the second method for forming a semiconductor device according to the first embodiment, a single damascene structure can also be used. In the second method for forming a semiconductor device according to the first embodiment, ion irradiation is used as the modification treatment, but plasma irradiation may be used. In this case, plasma irradiation uses a gas capable of generating atoms or molecules containing any of O, N, and H, such as O ₂ and NH ₃ . By this plasma irradiation, C in SiOC reacts, so that gases such as CO and CO ₂ can be desorbed.

  The present invention can be used for, for example, a semiconductor device having a wiring formed by a damascene method such as a miniaturized and integrated LSI and a method for forming the same.

Sectional drawing which shows the semiconductor device which concerns on the 1st Embodiment of this invention. Sectional drawing which shows each process of the formation method of the 1st semiconductor device which concerns on the 1st Embodiment of this invention. Sectional drawing which shows each process of the formation method of the 1st semiconductor device which concerns on the 1st Embodiment of this invention. Sectional drawing which shows each process of the formation method of the 2nd semiconductor device which concerns on the 1st Embodiment of this invention. Sectional drawing which shows each process of the formation method of the 2nd semiconductor device which concerns on the 1st Embodiment of this invention. Sectional drawing which shows the semiconductor device which has the wiring formed by the conventional damascene method Sectional drawing which shows the subject of the conventional semiconductor device Sectional drawing which shows the subject of the conventional semiconductor device

Explanation of symbols

DESCRIPTION OF SYMBOLS 101 Lower layer wiring 102 Insulating barrier film 103 Interlayer insulating film 104 Via 104a The roundness of the shoulder part of a via 105 Trench 105a The roundness of the shoulder part of a trench 105b The roundness of the corner A of the bottom face of a trench 106 Barrier metal film 107 Cu film 108 Via plug 109 Upper layer Wiring 200 Modified layer 300 Photomask 400 Modified layer A corner

Claims (15)

In a semiconductor device having an insulating film formed on a semiconductor substrate and wiring embedded in a trench formed in the insulating film,
A semiconductor device characterized in that the bottom corner of the trench is rounded. A lower wiring formed on the semiconductor substrate; an insulating film formed on the lower wiring; a via plug embedded in a via formed in the insulating film; and a trench formed in the insulating film. In a semiconductor device having an upper layer wiring,
A semiconductor device characterized in that the bottom corner of the trench is rounded. The semiconductor device according to claim 2,
A semiconductor device, wherein a shoulder portion of the via is rounded. In the semiconductor device as described in any one of Claims 1-3,
The semiconductor device is characterized in that the insulating film includes an insulating barrier film and an interlayer insulating film formed on the insulating barrier film. The semiconductor device according to claim 4,
The semiconductor device according to claim 1, wherein the interlayer insulating film is a SiOC film. In the semiconductor device according to any one of claims 1 to 5,
2. A semiconductor device according to claim 1, wherein a curvature of a rounded corner at the bottom of the trench is 7.7 × E7 [1 / m] or less. Forming an insulating film on the semiconductor substrate (a);
Forming a trench in the insulating film (b);
A step (m) of forming a modified layer on the surface of the insulating film after the step (b);
Removing the modified layer (n);
(C) depositing a barrier metal film so as to cover the trench after the step (n);
And (d) depositing a Cu film so as to fill the trench after the step (c). Forming a lower layer wiring on the semiconductor substrate (a);
Forming an insulating film on the lower wiring (b);
Forming a via in the insulating film (c);
Forming a trench connected to the via in the insulating film (d);
A step (m) of forming a modified layer on the surface of the insulating film after the step (d);
Removing the modified layer (n);
A step (e) of depositing a barrier metal film so as to cover the via and the trench after the step (n);
And (f) depositing a Cu film so as to fill the via and the trench after the step (e). In the formation method of the semiconductor device according to claim 7 or 8,
The method for forming a semiconductor device, wherein the step (m) uses ion irradiation or plasma irradiation. In the formation method of the semiconductor device according to claim 9,
The method for forming a semiconductor device, wherein the ion irradiation uses Ar gas. In the formation method of the semiconductor device according to claim 9,
A method for forming a semiconductor device, wherein the plasma irradiation uses a gas that generates atoms or molecules containing any of O, N, and H. The method of forming a semiconductor device according to claim 11.
The method for forming a semiconductor device, wherein the atom or molecule containing any of O, N, and H is O ₂ or NH ₃ . In the formation method of the semiconductor device according to any one of claims 8 to 12,
The step (b) includes a step (b1) of forming an insulating barrier film on the lower layer wiring,
A method for forming a semiconductor device, comprising a step (b2) of forming an interlayer insulating film on the insulating barrier film. 14. The method of forming a semiconductor device according to claim 13, wherein the interlayer insulating film is a SiOC film. In the formation method of the semiconductor device according to any one of claims 7 to 14,
In the step (n), a wet etching process using a chemical solution of dilute hydrofluoric acid or buffered hydrofluoric acid is performed.

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