JP2006295320A - Multiplied clock signal output circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a multiplied clock signal output circuit capable of stabilizing the frequency of a multiplied clock signal without the need for implementing measures of power supply isolation resulting in a cost increase. <P>SOLUTION: The multiplied clock signal output circuit 1 is provided with a count value averaging circuit 3, which averages results of counts by a plurality of number of times by a counter for counting a period of a reference clock signal PREF within a control period, and a digital control oscillation circuit 2 applies arithmetic processing to averaged data DTAVE to produce the multiplied clock signal. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention generates and outputs a multiplied clock signal obtained by multiplying the frequency of the reference clock signal by arithmetically processing the period data obtained by counting the period of the reference clock signal with a clock signal having a shorter period than the reference clock signal. The present invention relates to a multiplied clock signal output circuit.

In a so-called DPLL circuit that generates and outputs a multiplied clock signal obtained by multiplying the frequency of the reference clock signal by realizing the operation of a PLL (Phase Locked Loop) circuit by digital arithmetic processing, a plurality of periods of the reference clock signal are set to 1 The circuit operation is repeated as a control cycle. In the control period, the period of the reference clock signal is counted only once and used for calculation for generating the multiplied clock signal. An example of the DPLL circuit having such a configuration is disclosed in Patent Document 1.
JP-A-8-265111

  The DPLL circuit also includes a ring oscillator configured by connecting a plurality of logic inverting elements such as inverter gates in a ring shape, and the period of the reference clock signal is determined by a high-speed clock signal output from the ring oscillator. I try to count. However, the gate delay time of the inverter gate has a characteristic that varies according to the change of the power supply voltage. For this reason, when the power supply voltage fluctuates based on the fluctuation of the current consumption according to the operation state of the internal circuit or the circuit connected to the outside, the frequency of the clock signal output from the ring oscillator fluctuates. As a result, there is a problem that the frequency of the multiplied clock signal varies.

In order to solve such a problem, for example, it is conceivable to separate a power source supplied to a DPLL circuit or a ring oscillator inside the DPLL circuit and a power source supplied to other circuits. However, in that case, a plurality of power supply circuits are prepared and a power supply terminal is separately provided. Further, it is necessary to add a capacitor for stabilizing the power supply on the DPLL circuit side, resulting in an increase in cost.
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a multiplied clock signal output circuit that can stabilize the frequency of the multiplied clock signal without taking measures to increase costs such as separating power supplies. Is to provide.

According to the multiplication clock signal output circuit of claim 1, the averaging circuit averages a plurality of count results by the counter that counts the period of the reference clock signal within the control period, and the arithmetic processing circuit performs the averaging The multiplied data is arithmetically processed to generate a multiplied clock signal. Specifically, for example, as described in claim 2, the averaging circuit includes an addition circuit that sequentially adds the periodic data counted by the counter, and a division circuit that divides the addition result in accordance with the number of additions. To do.
That is, even when the frequency of the high-speed clock signal output from the ring oscillator fluctuates due to fluctuations in the power supply voltage, the periodic data is averaged, so that the influence of frequency fluctuations can be eliminated as much as possible. Therefore, the frequency accuracy of the multiplied clock signal can be improved without taking measures such as separating the power sources.

According to the multiplied clock signal output circuit of claim 3, the averaging circuit selects and outputs either one of the period data counted by the counter and the period data previously averaged; An adder circuit for adding the data output from the selector and the period data counted by the counter and a divider circuit for dividing the addition result of the adder circuit into two.
That is, only the first time allows the selector to select the period data on the counter side, so that the average result obtained first is substantially equal to the period data counted first. Thereafter, if the selector selects the cycle data side averaged last time, the cycle data averaged up to the previous time and the cycle data newly counted this time are added, and the addition result is 2 Will be divided. Therefore, averaged period data can be obtained without increasing the counter size or the divisor in the divider circuit.

(First embodiment)
A first embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a functional block diagram showing the configuration of the multiplied clock signal output circuit. The multiplied clock signal output circuit 1 includes a digitally controlled oscillation circuit (DCO, arithmetic processing circuit) 2, a counter / numerical value averaging circuit 3, a data latch circuit 4, and a control circuit 5. The digitally controlled oscillation circuit 2 includes a ring oscillator 6 that sequentially outputs 16 pulse signals (hereinafter referred to as clock signals) R1 to R16 having a predetermined phase difference Tg, and a high level control signal PA from the outside. , The clock signal R1 to R16 generated by the ring oscillator 6 is used to generate an output signal POUT having a period corresponding to the 12-bit frequency control data CD1 to CD12.

  The counter / numerical value averaging circuit 3 counts one cycle of the reference signal PREF using the clock signal RCK that is one of the clock signals R1 to R16 output from the ring oscillator 6, and averages the count value. The 13-bit data DTAVE 1 to 13 is output to the data latch circuit 4. The data latch circuit 4 converts the data DTAVE 1 to 13 into 12-bit frequency control data CD 1 to CD 12 in accordance with a multiplication number switching signal DV 1 given from the outside, and outputs it to the digital control oscillation circuit 2. The control circuit 5 outputs various control signals for controlling the operation timing of the digital control oscillation circuit 2, the counter / numerical value averaging circuit 3, and the data latch circuit 4.

The control circuit 5 is composed of a logic circuit centered on a 3-bit counter that counts the reference signal PREF, and is reset when an external control signal PA is at a low level. If the control signal PA is at a high level, the 3-bit counter counts the reference signal PREF. When the count value (control state) becomes “1” or more, the count enable signal UCE3 is output to the counter / numerical value averaging circuit 3, and when the count value is “4”, the data latch signal is sent to the data latch circuit 4. When UCE2 is output, the data latch signal DLS is output to the digitally controlled oscillation circuit 2 when the count value is "5", and when the count value is "0, 2, 4, 6" The count clear signal CLR is output to the circuit 3. When the operation start signal PSTB is input from the outside, the signal PSTB is latched at the timing when the count clear signal CLR is output, and is output as the control signal PC for starting the oscillation operation to the digitally controlled oscillation circuit 2. The
It should be noted that once the count permission signal UCE3 becomes active, the count permission signal UCE3 continues to be maintained even when the control cycle is switched.

  When the count permission signal UCE3 is continuously output from the control circuit 5, the counter / numerical value averaging circuit 3 is in the control state “1, 3, 5, 7” in which the count clear signal CLR is not output (that is, the reference signal A built-in 13-bit counter 41 (see FIG. 3) counts the clock signal RCK. The obtained count data DT1 to DT13 are averaged every time they are obtained, and averaged data DTAVE1 to DTAVE13 are output.

  In the data latch circuit 4, when the data latch signal DLS is output from the control circuit 5 and the latch timing signal DLC is output from the digital control oscillation circuit 2 in synchronization therewith, DTAVE 1 to 12, which is the lower 12 bits of DTAVE 1 to 13. Alternatively, DTAVE2 to 13 representing a value obtained by dividing the data by 2 is output to the digitally controlled oscillation circuit 2 as frequency control data CD1 to CD12. Thereafter, when the count clear signal CLR is output from the control circuit 5, the counter 41 in the counter / numerical value averaging circuit 3 is cleared.

  The digitally controlled oscillation circuit 2 receives the multiphase clock signals R1 to R16 from the ring oscillator 6 but selects a clock signal corresponding to the 4-bit select data D1 to D4, although the configuration other than the ring oscillator 6 is not shown. The high-order 8 bits (CD5 to CD12) of the frequency control data CD input from the pulse selector and counter / numerical value averaging circuit 3 that are selectively selected and output are preset and the clock signal R13 output from the ring oscillator 6 is preset. It is equipped with a counter that performs down-counting at the rising timing.

For example, as shown in FIG. 2, the ring oscillator 6 includes two 2-input NAND gates 7 and 8 as delay gates and 30 INV (inverter) gates 9 to 38 (however, for 10 to 24 and 26 to 37). Is omitted). In each of these logic inversion circuits, each output terminal is connected to the input terminal of the next stage in a ring shape, one input terminal of the NAND gate 7 is connected to the output terminal of the NAND gate 8, and the other input terminal Is supplied with a mode control signal PA from the outside.
One input terminal of the NAND gate 8 is connected to the output terminal of the INV gate 38, and the other input terminal is connected to the output terminal of the INV gate 25. The multiphase clock signals R1 to R16 are output from the output terminals of the logic inversion circuits connected to the even-numbered stages from the NAND gate 7, respectively.

  In the above configuration, the counter / numerical value averaging circuit 3 performs an averaging process, and the control signals required for the configuration (output of UCE3 and count clear signal CLR instead of the count permission signal UCE). The configuration other than the portion where the control circuit 5 outputs the timing and the like is basically the same as that disclosed in Patent Document 1.

  Next, the configuration of the counter / numerical value averaging circuit 3 will be described with reference to FIG. The counter / numerical value averaging circuit 3 includes a counter 41, an adder circuit 42, a divider circuit 43, and a register 44. The counter 41 counts the number of clock signals RCK output during a period in which the count permission signal UCE3 is active and the count clear signal CLR is inactive, and outputs the counter value DT to the adder circuit 42. . The adder circuit 42 adds the data FB obtained by feeding back the addition result data DTB output to the divider circuit 43 to the input side and the counter value DT. The division circuit 43 divides the addition result data DTB by the value obtained by adding “1” to the number N of additions in the adder 42 and outputs the result to the register 44. The data stored and output in the register 44 becomes the averaged data DTAVE (1-13).

  FIG. 3 also shows a state in which the calculation data in the counter / numerical value averaging circuit 3 changes every calculation cycle. The counter 41 alternately repeats counting and clearing every cycle of the reference signal PREF, so that the calculation cycle is two cycles of the reference signal PREF. As an initial state, when the calculation is started from the feedback data FB and the number N of additions being “0”, if the first counter value DT is “a1”, the addition result data DTB is “a1 + 0” and the output data DTAVE is “a1”. Is.

If the counter value DT in the next calculation cycle is “a2”, the feedback data FB is the previous addition result “a1”, and the current addition result data DTB is “a1 + a2”. Since the dividing circuit 43 is multiplied by “1 / (1 + 1)”, the output data DTAVE becomes “(a1 + a2) / 2”.
Thereafter, similarly, if the counter value DT in the next calculation cycle is “a3”, the feedback data FB is the previous addition result “a1 + a2”, and thus the current addition result data DTB is “a1 + a2 + a3”. Since the dividing circuit 43 is multiplied by “1 / (2 + 1)”, the output data DTAVE becomes “(a1 + a2 + a3) / 3”.

  Next, the operation of this embodiment will be described with reference to FIG. FIG. 4 is a timing chart showing circuit operations centering on the counter / numerical value averaging circuit 3 and the data latch circuit 4. As described above, the counter 41 of the counter / numerical value averaging circuit 3 starts the count operation when the UCE 3 becomes active (j), and the count data DT is a1, a2, a3,. Output as (i). Then, the data DTAVE averaged every two cycles is updated from the counter / numerical value averaging circuit 3 and outputted as a1, (a1 + a2) / 2, (a1 + a2 + a3) / 3,. (G).

  Since the latch signal UCE2 is output to the data latch circuit 4 in the fourth state (b), initially (a1 + a2) / 2 is latched as the data DTAVE, and the 13-bit data corresponds to the multiplication number switching signal DV1. Is converted to 12-bit data CD and output to the digitally controlled oscillator circuit 2 (h). The digitally controlled oscillation circuit 2 outputs a latch signal DLS in the fifth state, and the 12-bit data CD is latched (c) and used for an operation for generating the multiplied clock signal POUT. When the control circuit 5 receives the operation start signal PSTB and activates the control signal PC in the seventh state, the digital control oscillation circuit 2 starts outputting the multiplied clock signal POUT.

As described above, according to the present embodiment, the multiplied clock signal output circuit 1 includes the counter / numerical value averaging circuit 3, and count results of a plurality of times by the counter 41 that counts the period of the reference clock signal PREF are included in the control period. The digitally controlled oscillation circuit 2 performs an arithmetic process on the averaged data DTAVE to generate a multiplied clock signal POUT. Specifically, the counter / numerical value averaging circuit 3 sequentially adds the period data DT counted by the counter 41 by the adder circuit 42, divides the addition result data DTB by the division circuit 43 according to the number of additions, The averaged data DTAVE is output.
That is, even when the frequency of the high-speed clock signal RCK output from the ring oscillator 6 is fluctuated due to fluctuations in the power supply voltage, the periodic data DT is averaged, so that the influence of frequency fluctuations can be eliminated as much as possible. Accordingly, the frequency accuracy of the multiplied clock signal POUT can be improved without taking measures to separate the power supplied to the multiplied clock signal output circuit 1.

(Second embodiment)
FIG. 5 shows a second embodiment of the present invention. The same parts as those of the first embodiment are denoted by the same reference numerals and the description thereof is omitted. Only the different parts will be described below. FIG. 5 is a diagram corresponding to FIG. 3 of the first embodiment, and shows a configuration of a counter / numerical value averaging circuit 45 in place of the counter / numerical value averaging circuit 3. In the counter / numerical value averaging circuit 45, a division circuit 46 is arranged instead of the division circuit 43, and the division circuit 46 always divides the addition result data DTB output from the addition circuit 42 by “2”. It is configured.

  Further, a data selector 47 is added to the counter / numerical value averaging circuit 45. The selector 47 selects either the count data DT of the counter 41 or the feedback data FB that is the division result output from the division circuit 46 and outputs it to the addition circuit 42. Selection switching of the selector 47 is performed by a logic circuit (not shown). The selector 47 selects the count data DT side only when the counter 41 first counts and outputs the period data from the initial state, and thereafter the feedback is performed. The data FB side is continuously selected.

Next, the operation of the second embodiment will be described. As shown in FIG. 5, when the counter / numerical value averaging circuit 45 starts the operation from the state where the feedback data FB is indefinite as the initial state, the selector 47 initially selects the count data DT side. If the counter value DT is “a1”, the addition result data DTB is “a1 + a1”, and the output data DTAVE divided by “2” is “a1”.
Thereafter, the selector 47 continues to select the feedback data FB side. Then, if the counter value DT in the next calculation cycle is “a2”, the feedback data FB is the previous addition result “a1”, so the current addition result data DTB is “a1 + a2” and is divided by “2”. The output data DTAVE thus obtained is “(a1 + a2) / 2 = a2 ′”.

  Thereafter, similarly, if the counter value DT in the next calculation cycle is “a3”, the feedback data FB is the previous division result “a2 ′”, so that the current addition result data DTB is “a2 ′ + a3”. It becomes. The output data DTAVE divided by “2” is “(a2 ′ + a3) / 2 = a3 ′”.

As described above, according to the second embodiment, the counter / numerical value averaging circuit 45 selects either the cycle data DT counted by the counter 41 or the cycle data FB averaged last time. The selector 47 for output, the adder circuit 42 for adding the data output from the selector 47 and the period data counted by the counter 41, and the divider circuit 46 for dividing the addition result of the adder circuit 42 into two. .
Therefore, except for the first calculation cycle, if the selector 47 selects the feedback data FB side, the cycle data FB (= DTAVE) averaged up to the previous time and the cycle data DT newly counted this time are added. Then, the addition result is divided into two, and the averaged period data DTAVE can be obtained without increasing the size of the counter 41 or the divisor in the division circuit 46.

(Third embodiment)
FIG. 6 shows a third embodiment of the present invention. The multiplied clock signal output circuit 48 of the third embodiment is obtained by adding a frequency fine adjustment circuit 49 to the multiplied clock signal output circuit 1 of the first embodiment. Details of the operation of the frequency fine adjustment circuit 49 are also described in Patent Document 1, and only the outline thereof will be described below.
The frequency fine adjustment circuit 49 receives the 12-bit frequency control data CD output from the counter / numerical value averaging circuit 3 and outputs 9-bit frequency control data DD (DD1 to DD9) to the digital control oscillation circuit 2. Then, the digitally controlled oscillation circuit 2 outputs the output signal POUT at a cycle corresponding to the 9-bit frequency control data DD.

  The frequency fine adjustment circuit 49 receives the upper 9 bits CD4 to CD12 of the frequency control data CD, generates data obtained by adding a constant “1” to the data value (“+1” data), and generates the above 9 bits CD4 to CD12 and “ Either “+1” data is selected. Then, the 9-bit data selected and output is latched at the rising timing of the clock signal FDC output in synchronization with the output signal POUT from the digital control oscillation circuit 2, and the latched data is digitally converted as frequency control data DD1 to DD9. Output to the control oscillation circuit 2. The frequency fine adjustment circuit 49 receives the lower 3 bits CD1 to CD3 of the frequency control data CD output from the counter / numerical value averaging circuit 3, and is synchronized with the clock signal FDC and corresponds to the lower 3 bits CD1 to CD3. Select and output “+1” data at a frequency.

  For example, when the frequency control data CD input from the counter / numerical value averaging circuit 3 is “110000000011”, the digitally controlled oscillation circuit 2 outputs the output signal POUT once and twice every two times. Every time, “110000001” obtained by adding the value 1 to the upper 9-bit data “110000000” is input. In other cases, the upper 9-bit data “110000000” is inputted as it is, and the digitally controlled oscillation circuit 2 generates the output signal POUT in a cycle corresponding to the input data.

That is, in the multiplied clock signal output circuit 48, data representing the value after the decimal point when the frequency control data CD output from the counter / numerical value averaging circuit 3 is divided by 8 (2 ⁿ : n = 3) (first value) Data) to the digitally controlled oscillation circuit 2 and the frequency according to the ratio between the value represented by the lower 3 bits of data CD1 to CD3 of the frequency control data CD and 8, that is, the frequency according to the value after the decimal point. Thus, “1” is added to the first data.
Therefore, when the frequency control data CD is not divisible by 8 (the data values of the lower 3 bits CD1 to CD3 are not 0), the data value after the decimal point is changed with a frequency according to the value after the decimal point in the division result. Since the data (second data) added with “1” is output as the frequency control data CD, the average value of the generation cycle of the output signal POUT accurately corresponds to the value obtained by dividing the frequency control data CD by “8”. Can be made.

The present invention is not limited to the embodiments described above or shown in the drawings, and the following modifications are possible.
For example, the averaging circuit may be configured as follows. A shift register is configured by connecting N data registers in series, and the count data is sequentially shifted each time the counter counts the period data. Then, the output data of each data register may be added by an adding circuit, and the addition result may be divided by N.

1 is a functional block diagram showing a configuration of a multiplied clock signal output circuit according to a first embodiment of the present invention. Diagram showing the configuration of the ring oscillator Diagram showing the configuration of the counter and numerical averaging circuit Timing chart showing circuit operation centering on counter / numerical value averaging circuit and data latch circuit FIG. 3 equivalent view showing a second embodiment of the present invention. FIG. 1 equivalent view showing a third embodiment of the present invention.

Explanation of symbols

In the drawings, 1 is a multiplied clock signal output circuit, 2 is a digitally controlled oscillator circuit (arithmetic processing circuit), 3 is a counter / numerical value averaging circuit, 6 is a ring oscillator, 41 is a counter, 42 is an adder circuit, and 43 is a divider circuit. , 45 is a counter / numerical value averaging circuit, 46 is a division circuit, 47 is a data selector, and 48 is a multiplied clock signal output circuit.

Claims (3)

A counter that periodically counts the period of the reference clock signal with a clock signal having a period shorter than the reference clock signal output from the ring oscillator;
An arithmetic processing circuit that generates and outputs a multiplied clock signal obtained by multiplying the frequency of the reference clock signal by performing arithmetic processing on the period data counted by the counter with a plurality of periods of the reference clock signal as one control period; In the multiplication clock signal output circuit provided,
An averaging circuit that averages a plurality of count results by the counter within at least the control period;
The multiplication clock signal output circuit, wherein the arithmetic processing circuit performs arithmetic processing on the period data averaged by the averaging circuit. The averaging circuit is
An addition circuit for sequentially adding the period data counted by the counter;
2. The multiplied clock signal output circuit according to claim 1, comprising a division circuit that divides the addition result of the addition circuit in accordance with the number of additions. The averaging circuit is
A selector that selects and outputs either the cycle data counted by the counter or the cycle data averaged last time;
An addition circuit for adding the data output from the selector and the period data counted by the counter;
2. The multiplied clock signal output circuit according to claim 1, further comprising: a division circuit that divides the addition result of the addition circuit into two.

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