JP2006294799A - Solid state imaging element and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid state imaging element, along with its manufacturing method, capable of assuring transfer charge capacity at an output gate for improved transfer efficiency of the charge, without complication even after addition of a process for forming an element. <P>SOLUTION: A photoelectric converter, a vertical charge transfer, a horizontal charge transfer, and an output which converts signal charges to electric signals for outputting are formed on a semiconductor substrate. In the horizontal charge transfer, a p-type semiconductor layer is formed in the semiconductor substrate, and an n-type semiconductor layer for transferring charges is formed in the shallow region of the p-type semiconductor layer. An impurity added region where a p-type impurity is added is formed at a part on the upper stream side in the direction of charge transfer within an output gate region which is arranged at the end on the output part side of the horizontal charge transfer part. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device and a method for manufacturing the same, and more particularly to a technique for improving transfer efficiency.

FIG. 8 is a cross-sectional view illustrating the configuration of a horizontal transfer unit and an output unit of a conventional solid-state imaging device. In this conventional solid-state imaging device, the horizontal charge transfer unit 1 includes a horizontal transfer register unit 2 and an output gate unit 3. The horizontal transfer register unit 2 includes a plurality of transfer stages 4, 4,..., And transfers signal charges at high speed in the horizontal direction (X direction in the figure) by transfer voltages (drive signals) φH ₁ and φH ₂ . As a result, the signal charge is transferred in the horizontal transfer channel 5.

Each transfer stage 4, 4,... In the horizontal transfer channel 5 includes a set of charge storage electrodes 6a and charge transfer electrodes 6b, and an n ⁻ layer 5a below the charge transfer electrodes 6b. The downstream side of the horizontal transfer channel 5 in the charge transfer direction is connected to the floating diffusion (FD) region 8 of the output unit 7 via the output gate unit 3 ahead of the final transfer stage 4.

  The output gate unit 3 includes an output gate electrode 9 and a horizontal transfer channel 5 below the output gate electrode 9. A voltage VOG is applied to the output gate electrode 9, and signal charges are transferred from the horizontal transfer channel 5 to the FD region 8. The signal charge is transferred to the FD region 8 and subjected to charge-voltage conversion. The converted voltage signal is amplified by the output amplifier 10 and output.

  The signal charge transferred to the FD region 8 is discharged to the reset drain region 12 through the reset gate portion 11 after charge-voltage conversion. At the time of discharge, a constant voltage φRG is applied to the reset gate portion 11 by the reset gate electrode 13.

  The horizontal charge transfer unit 1 and the output unit 7 have a layer structure in which, for example, a p-type well 18 and a buried channel type n-type horizontal transfer channel 5 are formed in this order on the surface of an n-type semiconductor substrate 17, for example. A charge storage electrode 6a and a charge transfer electrode 6b are formed on the horizontal transfer channel 5 via an insulating film (not shown), and the charge storage electrode 6a and the charge transfer electrode 6b are connected in common for each transfer stage 4. The

In the output unit 7, the FD region 8 is formed in an n ⁺ type, the reset gate unit 11 is formed in an n type, and the reset drain region 12 is formed in an n ⁺ type. A reset gate electrode 13 is formed on the reset gate portion 11 via an insulating film (not shown).

In the present specification and drawings, the n-type channel region, in which the effective impurity concentration is decreased by adding p-type impurities, is added to n ⁻ , and the effective impurity concentration is increased by adding n-type impurities. The n-type channel region is expressed as n ⁺ , and the p-type region in which the effective impurity concentration is increased by adding a p-type impurity is expressed as p ⁺ .

Patent Document 1 describes a technique for further improving the charge transfer efficiency of each transfer stage with respect to the solid-state imaging device as described above. In this technique, for example, when a p-type impurity such as boron is introduced into a substrate by an ion implantation method, the side surface portion of the electrode layer serving as a mask is formed in a tapered shape, and the thin portion of the electrode side surface portion is formed. The p-type impurity is easy to penetrate. As a result, a sufficient amount of p-type impurity can be implanted into a region where the p-type impurity is insufficiently implanted below the side surface of the electrode layer, and generation of a potential depression in the region is suppressed. Yes. When the potential depression occurs, the signal charge is trapped in the potential depression, and the transfer electric field in the vicinity of the potential depression becomes weak, so that the charge transfer efficiency decreases. In the technique of Patent Document 1, such a decrease in transfer efficiency is prevented by processing the side surface portion of the electrode layer. The configuration of Patent Document 1 improves the charge transfer efficiency by adding a potential step to the horizontal transfer region.
Japanese Patent Laid-Open No. 9-289309

  By the way, as a method of providing a potential step in the horizontal transfer region of the element, there are a method of performing ion etching by taper etching of an electrode layer as in the above-mentioned Patent Document 1, and a method of performing ion implantation by patterning in a normal photolithography process. . However, these methods have disadvantages that increase the number of steps, take extra processing time, and increase the manufacturing cost of parts. In addition, in the output gate region connected to the horizontal transfer region, there is a problem that the charge transfer efficiency tends to be lowered.

  SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and can improve the charge transfer efficiency while ensuring the transfer charge capacity of the output gate without adding complexity to the process for forming the element. An object of the present invention is to provide an imaging device and a manufacturing method thereof.

The above object of the present invention is achieved by the following configurations.
(1) A photoelectric conversion unit that photoelectrically converts incident light to generate a signal charge, a vertical charge transfer unit that transfers a signal charge generated by the photoelectric conversion unit in a vertical direction, and a transfer from the vertical charge transfer unit A solid-state imaging device formed on a semiconductor substrate includes a horizontal charge transfer unit that transfers a signal charge in a horizontal direction and an output unit that converts the signal charge transferred from the horizontal charge transfer unit into an electric signal and outputs the electric signal. The horizontal charge transfer unit includes a p-type semiconductor layer formed in the semiconductor substrate, and an n-type semiconductor layer for charge transfer formed in a shallow region of the p-type semiconductor layer. In the output gate region disposed at the end portion on the output portion side, an impurity doped region to which a p-type impurity is added is formed in a part of the output gate region on the upstream side in the charge transfer direction. A solid-state imaging device.

  According to this solid-state imaging device, in the output gate region, the impurity-added region to which the p-type impurity is added is formed in part of the output gate region on the upstream side in the charge transfer direction. A potential step occurs. By this step, the signal charge can be reliably transferred from the output gate region to the downstream side in the transfer direction, and the transfer efficiency is improved while ensuring the transfer charge capacity of the output gate.

(2) The solid state according to (1), wherein a boundary of the impurity added region in the output gate region is inclined toward the upstream side in the charge transfer direction with respect to the depth direction of the semiconductor substrate. Image sensor.

  According to this solid-state imaging device, the potential distribution in the output gate region has an inclination toward the charge transfer direction because the boundary of the impurity-added region is inclined with respect to the depth direction of the semiconductor substrate. As a result, the signal charge is transferred more smoothly due to the drift due to the potential gradient.

(3) The solid-state imaging device according to (1) or (2), wherein a boundary of the impurity added region is formed in the output gate region.

  According to this solid-state imaging device, since the impurity-added region is formed in the output gate region, the potential distribution in the output gate region becomes a well-balanced potential gradient, and the signal charge transfer becomes smoother.

(4) A photoelectric conversion unit that photoelectrically converts incident light to generate a signal charge, a vertical charge transfer unit that transfers the signal charge generated by the photoelectric conversion unit in a vertical direction, and a transfer from the vertical charge transfer unit Manufacture of a solid-state imaging device formed on a semiconductor substrate with a horizontal charge transfer unit that transfers the signal charge in the horizontal direction and an output unit that converts the signal charge transferred from the horizontal charge transfer unit into an electrical signal and outputs the electrical signal A step of forming a p-type semiconductor layer in the semiconductor substrate; and an output gate region disposed at an end of the horizontal charge transfer unit on the output unit side, wherein the output gate region Forming a resist pattern having an edge of the opening on the downstream side in the charge transfer direction, and an oblique direction inclined at a predetermined angle from the vertical direction of the semiconductor substrate to the downstream side in the charge transfer direction using the resist as a mask Solid-state imaging comprising the steps of: ion-implanting p-type impurities to form an impurity doped region; and forming an n-type semiconductor layer for charge transfer in a shallow region of the p-type semiconductor layer. Device manufacturing method.

  According to this method for manufacturing a solid-state imaging device, a p-type semiconductor layer is formed, an output gate region of a horizontal charge transfer portion is opened, and a resist pattern having an opening edge on the downstream side in the charge transfer direction of the output gate is formed To do. This resist pattern uses a resist used for forming other parts such as a photoelectric conversion element of a solid-state imaging device. Then, using this resist as a mask, when p-type impurities are ion-implanted from an oblique direction inclined at a predetermined angle from the vertical direction of the semiconductor substrate to the downstream side of the charge transfer direction, the p-type impurities are absorbed by the resist at the opening edge of the resist. The depth of implantation of the p-type impurity varies from the part that hardly reaches the substrate to the part that penetrates the edge of the resist and collides with the substrate, and the part that the p-type impurity collides with the substrate directly from the resist opening. To do. As a result, the boundary of the impurity added region is inclined toward the upstream side in the charge transfer direction with respect to the depth direction of the semiconductor substrate, and the potential distribution in the output gate region has an inclination in the charge transfer direction. Then, an n-type semiconductor layer is formed in a shallow region of the p-type semiconductor layer. Accordingly, the signal charge can be smoothly transferred by the drift due to the potential gradient.

(5) A photoelectric conversion unit that photoelectrically converts incident light to generate a signal charge, a vertical charge transfer unit that transfers the signal charge generated by the photoelectric conversion unit in the vertical direction, and a transfer from the vertical charge transfer unit Manufacture of a solid-state imaging device formed on a semiconductor substrate with a horizontal charge transfer unit that transfers the signal charge in the horizontal direction and an output unit that converts the signal charge transferred from the horizontal charge transfer unit into an electrical signal and outputs the electrical signal A method comprising: forming a p-type semiconductor layer in the semiconductor substrate; and an opening in at least a part of an output gate region disposed at an end of the horizontal charge transfer unit on the output unit side, Forming a resist pattern having an edge of the opening in the output gate region; and an oblique direction inclined at a predetermined angle from the vertical direction of the semiconductor substrate to the upstream side in the charge transfer direction using the resist as a mask And a step of forming an impurity doped region by ion implantation of a p-type impurity, and a step of forming an n-type semiconductor layer for charge transfer in a shallow region of the p-type semiconductor layer. Device manufacturing method.

  According to this method for manufacturing a solid-state imaging device, a p-type semiconductor layer is formed, and at least a part of the output gate region is opened, and a resist pattern having an edge of the opening is formed in the output gate region. This resist pattern uses a resist used for forming other parts such as a photoelectric conversion element of a solid-state imaging device. When this resist is used as a mask and p-type impurities are ion-implanted from an oblique direction inclined at a predetermined angle from the vertical direction of the semiconductor substrate to the upstream side in the charge transfer direction, the p-type impurities are absorbed by the resist at the opening edge of the resist. The depth of implantation of the p-type impurity changes in a range from a portion that hardly reaches the region to a portion that penetrates the edge of the resist and collides with the substrate, and a portion that the p-type impurity collides with the substrate directly from the opening of the resist. As a result, the boundary of the impurity added region is inclined toward the upstream side in the charge transfer direction with respect to the depth direction of the semiconductor substrate, and the potential distribution in the output gate region has an inclination in the charge transfer direction. Then, an n-type semiconductor layer is formed in a shallow region of the p-type semiconductor layer. Accordingly, the signal charge can be smoothly transferred by the drift due to the potential gradient.

  According to the solid-state imaging device and the manufacturing method thereof of the present invention, it is possible to improve the charge transfer efficiency while ensuring the transfer charge capacity of the output gate without adding complexity to the process for forming the device. .

Preferred embodiments of a solid-state imaging device and a method for manufacturing the same according to the present invention will be described below in detail with reference to the drawings.
1 is a schematic plan view of a solid-state imaging device according to the present invention, FIG. 2 is a configuration diagram of a horizontal transfer unit and an output unit of the solid-state imaging device shown in FIG. 1, (a) is an enlarged plan view, and (b) is ( It is a cross-sectional schematic diagram of the AA line shown to a).
A solid-state imaging device 100 shown in FIG. 1 is a CCD image sensor, for example, and is an optical device that converts an optical image formed by an imaging optical system into an electrical signal. The solid-state imaging device 100 includes a photoelectric conversion element, a vertical charge transfer unit 25, a horizontal charge transfer unit 31, and an output unit 37, which will be described later.

  In the solid-state imaging device 100, a large number of photodiodes 23, which are photoelectric conversion elements, are formed on the surface portion of an n-type silicon substrate 21, and signal charges generated in the photodiodes 23 upon receiving light are transmitted in the column direction (Y in FIG. 1). Vertical charge transfer section 25 for transferring in the direction) is formed between a plurality of photodiode rows comprising a plurality of photodiodes 23 arranged in the column direction.

  The vertical charge transfer unit 25 includes a plurality of vertical transfer channels 27 formed on the surface portion of the silicon substrate 21 corresponding to each of the plurality of photodiode columns, and a charge transfer electrode ( And a charge readout region 29 for reading out the charge generated in the photodiode 23 to the vertical transfer channel 27.

  A horizontal charge transfer unit 31 to which a plurality of vertical charge transfer units 25 are connected is configured to include a horizontal transfer register unit 33 and an output gate 35 as in the horizontal charge transfer unit 1 shown in FIG. The signal charge sent from the charge transfer unit 25 is transferred at high speed toward the output gate 35 in the horizontal direction (X direction in the figure). After the charge-voltage conversion, the voltage signal is amplified by the output amplifier 39 of the output unit 37 provided at the downstream end of the horizontal charge transfer unit 31 in the charge transfer direction, and this is output as an output signal.

Next, the configuration of the horizontal charge transfer unit 31 and the output unit 37 of the solid-state imaging device 100 according to the present embodiment will be described in detail with reference to FIG.
The configurations of the horizontal charge transfer unit 31 and the output unit 37 of the solid-state imaging device according to the first embodiment shown in FIGS. 2A and 2B are provided with an impurity-added region S compared to those shown in FIG. The only difference is that the charge transfer efficiency is improved, and the other configuration is the same as that of FIG.

  As shown in FIG. 2A, the horizontal transfer channel 41 gradually increases in width (length in the Y direction) toward the output unit 37 in the final transfer stage 43 and the output gate 35 of the horizontal transfer register unit 33. Have a narrowing structure. This is because the output voltage of the floating diffusion (FD) region 45 is inversely proportional to the capacitance of the FD region 45, so that a large output voltage can be obtained, that is, in plan view. This is because the area is set small. In the illustrated example, both are represented by substantially equal lengths. Actually, however, the output gate electrode 47 provided in the output gate 35 is more than the charge storage electrodes 48a and charge transfer electrodes 48b of the transfer stages 43, 43,. In general, the width in the X direction is set wide. As a result, the charge transfer amount can be earned.

  As shown in FIG. 2B, when the horizontal transfer channel 41 is formed of, for example, an n-type semiconductor, the impurity-added region S is formed by adding a p-type impurity to the horizontal transfer channel 41. For this reason, the impurity doped region S is in a state where the p-type impurity concentration is increased in both the horizontal transfer channel 41 which is an n-type semiconductor layer and the p-well layer 51 therebelow. The boundary at the end of the impurity doped region S is set at an appropriate position within the region of the output gate 35. Therefore, an impurity added region S in which the concentration of the p-type impurity is increased is formed on the upstream side in the charge transfer direction in the region of the output gate 35.

  The signal charges transferred to the FD region 45 are discharged to the reset drain region 55 through the reset gate portion 53 after charge-voltage conversion. At the time of discharge, a constant voltage φRG is applied to the reset gate portion 53 by the reset gate electrode 57.

  Next, the state of charge transfer by the horizontal transfer channel 41 configured as described above will be described with reference to FIG. 3A and 3B are explanatory views of the charge transfer operation of the horizontal transfer channel, where FIG. 3A is an enlarged cross-sectional view of the main part of the horizontal transfer channel, and FIG. 3B is a potential distribution diagram along the charge transfer direction of the horizontal transfer channel. FIG. 5C is a graph showing a state where charges are accumulated in the storage electrode, and FIG. 8C is a graph showing a state where charges accumulated in the charge storage electrode are transferred to the FD region 45 in the same potential distribution diagram.

As shown in FIG. 3A, the impurity-added region S is formed in the region of the output gate 35 (output gate electrode 47) on the upstream side in the charge transfer direction, and as shown in FIG. The potential of the impurity added region S is lowered by Δp ₁ (the waveform of the graph is increased). Then, the potential distribution at the position of the output gate 35 has a lower potential with respect to the width La included in the impurity-added region S in the entire width L of the output gate 35, and the potential on the downstream side in the charge transfer direction is always deeper. A potential step is formed.

  As a result, as shown in FIG. 3C, when a predetermined voltage VOG is applied to the output gate electrode 47, the charge Q accumulated at the position of the first charge accumulation electrode 48a is transferred to the FD region 45. The charge Q smoothly flows to the FD region 45, thereby eliminating the transfer residue of the signal charge, shortening the transfer time, and improving the transfer efficiency.

Next, an example of a manufacturing process of the horizontal charge transfer unit 31 and the output unit 37 will be described below.
FIG. 4 is an explanatory diagram of the manufacturing process of the horizontal charge transfer unit and the output unit of the solid-state imaging device according to the present invention.
Hereinafter, the manufacturing process will be sequentially described with reference to FIG.
First, as shown in FIG. 4B, an SiO ₂ oxide film 61 is formed on the surface of the silicon substrate 21 shown in FIG. The oxide film 61 is formed to a thickness of about 20 nm, for example.

  Next, a p-type impurity, for example, boron B is ion-implanted to form a p-well layer 51 below the oxide film 61 (FIG. 4C). Then, the resist 63 is patterned on the oxide film 61 with the position corresponding to the width direction (X direction) of the output gate electrode as an end boundary (FIG. 4D).

Further, using this resist 63 as a mask, a p-type impurity such as boron B (acceleration energy 60 to 100 keV (preferably 80 keV), dose amount 1 × 10 ¹¹ to 1 × 10 ¹⁵ cm ⁻² (preferably 1.6 × 10). ¹² cm ⁻² ), and an impurity-added region S in which a p-type impurity is added at a high concentration is formed in the p-well layer 51 below the oxide film 61 (FIG. 4E).

Next, the patterned resist 63 is removed (FIG. 4F), the resist (not shown) is patterned again, and n-type impurities such as phosphorus P or arsenic As are ion-implanted using this resist as a mask. (For example, in the case of phosphorus P, the acceleration energy is 80 to 120 keV and the dose is 1.0 × 10 ^{12 to} 3.0 × 10 ¹² cm ⁻² , and in the case of arsenic As, the acceleration energy is 80 to 120 keV and the dose is 1.0 ×. ^{10 12 ~3.0 × 10 12 cm -2} ). As a result, an n-type semiconductor layer to be the horizontal transfer channel 41 is formed (FIG. 4G). Thereafter, the oxide film 61 is removed (FIG. 4H), and an ONO film 65 in which SiO ₂ , SiN, and SiO ₂ are laminated is formed (FIG. 4I).

  Here, the resist 63 is the same as a conventionally used resist, but the pattern is different in the vicinity of the output gate 35. That is, the impurity doped region S is conventionally formed up to the upstream end of the output gate 35, but the boundary of the impurity doped region S of the present embodiment is extended below the output gate 35. The ion implantation for defining the impurity-added region S uses an ion implantation process for other parts or an ion implantation process for adjusting a threshold voltage. Therefore, in the present invention, by forming the impurity-added region S using the resist 63, it is not necessary to perform processing such as resist coating, patterning, and ion implantation in addition to the normal process.

Next, after the charge storage electrode 48a is formed on the ONO film 65 by patterning (FIG. 4 (j)), the resist 67 is further patterned so that the charge storage electrodes 48a are opened (FIG. 4). (K)) Using this resist 67 and the charge storage electrode 48a as a mask, a p-type impurity such as boron B is ion-implanted (FIG. 3L). As a result, a buried n ⁻ region 69 is formed in the horizontal transfer channel 41 between the charge storage electrodes 48a.

Subsequently, the charge transfer electrode 48b is formed above the n ⁻ region 69, and the output gate electrode 47 is formed on the side of the final stage charge storage electrode 48a which is the output portion 37 side. At this time, the reset gate electrode 57 is formed at a position corresponding to the reset gate portion 53 (FIG. 4 (n)).

Next, a resist 71 is formed by patterning on the charge storage electrode 48a, the charge transfer electrode 48b, the output gate electrode 47, and the reset gate electrode 57 (FIG. 4 (o)). Alternatively, arsenic As is ion-implanted using the resist 71 as a mask (for example, acceleration energy 80 to 150 keV, dose amount 5.0 × 10 ^{14 to} 3.0 × 10 ¹⁵ cm ⁻² ), and an n ⁺ layer is formed (FIG. 4 ( p)) The n ⁺ layers become the FD region 45 and the reset drain region 55. Finally, if the resist 71 is removed, the horizontal charge transfer unit 31 and the output unit 37 are fabricated (FIG. 4 (q)). ).

  According to the solid-state imaging device 100 according to the present invention described above, the impurity-added region S is formed and the charge transfer efficiency is improved without adding to the normal element formation process. That is, a window is provided in the resist used in the conventional process, and p-type impurities are ion-implanted into the horizontal transfer register portion 33 from this window, thereby forming the impurity added region S. Thus, the region below the output gate electrode 47 is formed. The potential potential from the middle in the width direction of the horizontal transfer channel 41 is changed. That is, a potential step is formed in which the potential distribution at the position of the output gate electrode 47 is always lower in the impurity-added region S and higher in other regions. This potential step functions to facilitate the transfer of signal charges.

  As described above, in the potential distribution below the output gate 35, the flat portion of the potential is reduced, and the overall potential gradient at the time of charge transfer becomes fine. As a result, the signal charge is transferred at high speed, and the transfer residue is hardly generated. Become.

Next, a second embodiment of the solid-state image sensor according to the present invention will be described.
In the present embodiment, when forming the impurity-added region S according to the process shown in FIG. 4 described above, a p-type impurity, for example, boron B is implanted obliquely with respect to the silicon substrate surface. Then, a potential gradient corresponding to the degree of penetration of the resist is provided at the boundary portion of the impurity added region S by using the edge portion of the patterned resist.

FIG. 5 is an explanatory view showing a state of ion implantation when forming the impurity doped region S, and is a cross-sectional view corresponding to FIG. This differs from the ion implantation of the first embodiment in that p-type impurities are implanted obliquely.
In this embodiment, when p-type impurities such as boron B are ion-implanted, they are implanted from an oblique direction inclined at a predetermined angle φ ₁ toward the downstream side in the charge transfer direction from the substrate vertical direction _LN of the silicon substrate 21. Then, in the vicinity of the edge of the resist 63, a part of the p-type impurity penetrates the edge of the patterned resist 63 and reaches the p well layer 51. As a result, the impurity added region S into which the p-type impurity is implanted exhibits a distribution inclined in the depth direction. That is, in the vicinity of the edge of the resist 63, the concentration of the p-type impurity increases as the distance from the edge increases, and the depth of the impurity-added region S increases. The depth of the impurity added region S is constant from the region where the p-type impurity reaches the p-well layer 51 by grazing the edge of the resist 63.

  6 is an explanatory diagram showing the potential distribution and the state of charge transfer in the case of having the impurity doped region S inclined in the depth direction shown in FIG. 5, and (a) is an enlarged cross-sectional view of the main part of the horizontal transfer channel. (B) is a potential distribution diagram along the charge transfer direction of the horizontal transfer channel and is a graph showing a state in which charges are accumulated in the charge storage electrode. (C) is a potential distribution diagram and FD represents the charges accumulated in the charge storage electrode. It is a graph which shows a mode that it transfers to the area | region 45. FIG.

As shown in FIG. 6A, the impurity-added region S is formed in the output gate 35 region with an inclination in the depth direction, so that the impurity-added region is formed as shown in FIG. 6B. The potential of S is reduced by Δp _{2 at the} maximum. Then, the potential distribution at the position of the output gate 35 continuously changes in the vicinity of the boundary with the impurity added region S in the entire width L of the output gate 35, and the potential on the downstream side in the charge transfer direction is always smooth. Deeply changing steps are formed.

  As a result, as shown in FIG. 6C, when a predetermined voltage VOG is applied to the output gate electrode 47 to transfer the charge Q accumulated at the position of the charge accumulation electrode 48a to the FD region 45, Q flows smoothly into the FD region 45, thereby eliminating the remaining transfer of signal charges, shortening the transfer time, and improving the transfer efficiency. In addition, by smoothly changing the potential distribution at the position of the output gate 35, the accumulated charge leaks due to the collapse of the potential distribution shape due to the narrow channel effect, as compared with the rectangular potential distribution. Can be prevented. As a result, in the present invention, it is possible to improve both the charge transfer efficiency and maintain the necessary and sufficient charge transfer capacity.

Here, a modification of the ion implantation process will be described with reference to FIG. FIG. 7 is an explanatory view showing another state of ion implantation when forming the impurity doped region S, and is a cross-sectional view corresponding to FIG.
The direction of ion implantation in this case is set to φ ₂ in the opposite direction from the inclination φ ₁ from the substrate vertical direction _LN described above. That is, the injection direction is set so as to incline upstream in the charge transfer direction. Then, by patterning the end portion of the resist 63 so that the impurity-added region S is formed at a desired position, as in the case shown in FIG. 5, the charge transfer direction upstream with respect to the depth direction. As a result, an inclined impurity doped region S is formed.
In this case, since the tilt start position of the impurity-added region S in the depth direction almost coincides with the end position of the resist 63, the alignment accuracy can be further improved.

  According to the solid-state imaging device of each embodiment described above, the impurity-added region S is formed in the horizontal transfer channel, and the boundary of the impurity-added region S is located in the output gate 35 region where charge transfer efficiency can be minimized. As a result, a step in the potential distribution is provided in the output gate 35. This step prevents the occurrence of transfer failure and enables high-speed drive of charge transfer.

  Note that the above-described oblique ion implantation is applicable not only to the output gate 35 and the horizontal transfer register unit 33 but also to other parts such as the vertical transfer channel 27.

It is a plane schematic diagram of the solid-state image sensor concerning the present invention. 2A and 2B are configuration diagrams of a horizontal transfer unit and an output unit of the solid-state imaging device illustrated in FIG. 1, in which FIG. 1A is an enlarged plan view, and FIG. 2B is a schematic cross-sectional view taken along line AA illustrated in FIG. It is explanatory drawing of the charge transfer operation | movement of a horizontal transfer channel, Comprising: (a) is a principal part expanded sectional view of a horizontal transfer channel, (b) is a potential distribution diagram along the charge transfer direction of a horizontal transfer channel. A graph showing a state where charges are accumulated, (c) is a graph showing a state where charges accumulated in the charge accumulation electrode are transferred to the FD region 45 in the same potential distribution diagram. It is explanatory drawing of the manufacturing process of the horizontal charge transfer part and output part of the solid-state image sensor which concerns on this invention. It is explanatory drawing which shows the mode of the ion implantation at the time of forming an impurity addition area | region, and is sectional drawing corresponding to FIG.4 (e). 6A and 6B are explanatory diagrams showing a potential distribution and a state of charge transfer in the case where the impurity added region S inclined in the depth direction shown in FIG. 5 is included, and FIG. Is a graph showing a state in which charges are accumulated in the charge storage electrode in the potential distribution diagram along the charge transfer direction of the horizontal transfer channel, and (c) is a graph showing the charge accumulated in the charge storage electrode in the potential distribution diagram in the FD region 45. It is a graph which shows a mode that it transfers. It is explanatory drawing which shows the mode of other ion implantation at the time of forming the impurity addition area | region S, and is sectional drawing corresponding to FIG.4 (e). It is sectional drawing showing the structure of the horizontal transfer part and output part of the conventional solid-state image sensor.

Explanation of symbols

DESCRIPTION OF SYMBOLS 21 Silicon substrate 23 Photodiode 25 Vertical charge transfer part 27 Vertical transfer channel 29 Charge read-out area 31 Horizontal charge transfer part 33 Horizontal transfer register part 35 Output gate 37 Output part 39 Output amplifier 41 Horizontal transfer channel 43 Transfer stage 45 Floating diffusion area 47 output gate electrode 48a charge storage electrode 48b charge transfer electrode 51 p-well layer 53 reset gate portion 55 reset drain region 57 reset gate electrode 61 SiO ₂ oxide film 63 resist 65 ONO film 67 resist 69 n ^- region 71 resist 100 solid-state imaging device S impurity added region

Claims (5)

A photoelectric conversion unit that photoelectrically converts incident light to generate signal charges, a vertical charge transfer unit that transfers signal charges generated by the photoelectric conversion unit in the vertical direction, and a signal charge that is transferred from the vertical charge transfer unit A solid-state imaging device formed on a semiconductor substrate, a horizontal charge transfer unit that horizontally transfers a signal charge, and an output unit that converts a signal charge transferred from the horizontal charge transfer unit into an electrical signal and outputs the electrical signal,
The horizontal charge transfer unit includes a p-type semiconductor layer formed in the semiconductor substrate, and an n-type semiconductor layer for charge transfer formed in a shallow region of the p-type semiconductor layer.
In the output gate region disposed at the end of the horizontal charge transfer unit on the output unit side, an impurity added region to which a p-type impurity is added is formed in a part of the output gate region on the upstream side in the charge transfer direction. A solid-state imaging device.   2. The solid-state imaging device according to claim 1, wherein a boundary of the impurity added region in the output gate region is inclined toward an upstream side in a charge transfer direction with respect to a depth direction of the semiconductor substrate.   The solid-state imaging device according to claim 1, wherein a boundary of the impurity added region is formed in the output gate region. A photoelectric conversion unit that photoelectrically converts incident light to generate signal charges, a vertical charge transfer unit that transfers signal charges generated by the photoelectric conversion unit in the vertical direction, and a signal charge that is transferred from the vertical charge transfer unit A solid-state image sensor manufacturing method in which a horizontal charge transfer unit that horizontally transfers a signal charge and an output unit that converts a signal charge transferred from the horizontal charge transfer unit into an electrical signal and outputs the electric signal are formed on a semiconductor substrate. And
Forming a p-type semiconductor layer in the semiconductor substrate;
Forming a resist pattern having an opening in an output gate region disposed at an end of the horizontal charge transfer unit on the output unit side, and having an edge of the opening on the downstream side in the charge transfer direction of the output gate region; When,
Using the resist as a mask, forming a doped region by ion-implanting p-type impurities from an oblique direction inclined at a predetermined angle from the vertical direction of the semiconductor substrate to the downstream side in the charge transfer direction;
Forming an n-type semiconductor layer for charge transfer in a shallow region of the p-type semiconductor layer;
The manufacturing method of the solid-state image sensor characterized by including. A photoelectric conversion unit that photoelectrically converts incident light to generate signal charges, a vertical charge transfer unit that transfers signal charges generated by the photoelectric conversion unit in the vertical direction, and a signal charge that is transferred from the vertical charge transfer unit A solid-state image sensor manufacturing method in which a horizontal charge transfer unit that horizontally transfers a signal charge and an output unit that converts a signal charge transferred from the horizontal charge transfer unit into an electrical signal and outputs the electric signal are formed on a semiconductor substrate. And
Forming a p-type semiconductor layer in the semiconductor substrate;
Forming a resist pattern having an opening in at least a part of an output gate region disposed at an end of the horizontal charge transfer unit on the output unit side, and having an edge of the opening in the output gate region; ,
Using the resist as a mask, p-type impurities are ion-implanted from an oblique direction inclined at a predetermined angle from the vertical direction of the semiconductor substrate to the upstream side of the charge transfer direction, thereby forming an impurity-added region;
Forming an n-type semiconductor layer for charge transfer in a shallow region of the p-type semiconductor layer;
The manufacturing method of the solid-state image sensor characterized by including.

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