JP2006294758A - Semiconductor device having trench capacitor and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a structure capable of improving a withstand voltage between capacitors and suppressing a leakage current in a trench capacitor part used in a withstand voltage DRAM cell, and a manufacturing method thereof.
A plate electrode formed on the surface of a semiconductor substrate in a trench portion formed in a semiconductor substrate, a capacitor insulating film and an upper electrode formed in the trench portion, and a pad formed on the semiconductor substrate adjacent to the trench portion. In the trench capacitor portion including the silicon oxide film, the side wall portion of the pad silicon oxide film is covered with a nitride film, thereby improving the breakdown voltage between the capacitors and suppressing the leakage current.
[Selection] Figure 10

Description

  The present invention relates to a semiconductor device having a trench capacitor used for a dynamic random access memory cell and a method for manufacturing the same.

  In recent years, along with the high integration of semiconductor integrated circuits, the miniaturization of minimum processing dimensions and the miniaturization of the memory cell area of, for example, a dynamic random access memory (DRAM) are rapidly progressing. Accordingly, the capacitor area in DRAM cells has become very small. As the memory cell area decreases, the capacitor capacity (storage capacity Cs) also decreases. However, the capacitor capacity requires a certain value or more in terms of sense sensitivity, soft error, circuit noise, and the like. As a method for solving this, it has been proposed to form a capacitor three-dimensionally to obtain a capacitor capacity by increasing the capacitor surface area with a small cell area as much as possible. As one of them, a deep hole is formed as a trench portion in a semiconductor substrate. A trench capacitor method is being studied in which a capacitor is formed on the side surface of the hole.

  However, as the memory cell is miniaturized and the interval between the trench capacitors is narrowed, there is a problem that a leak current is generated between adjacent capacitors or between a transistor and a capacitor constituting the memory cell. On the other hand, for example, a device has been devised in the manufacturing process such as impurity introduction so as to prevent parasitic leakage current (see, for example, Patent Document 1).

  However, since there are other causes of leakage current, further measures are required. For example, a pad oxide film is formed on a semiconductor substrate for insulation between capacitors. As described below in relation to other processes for forming a trench capacitor, a phenomenon in which a part of the pad oxide film is etched and insulation between trench capacitors becomes insufficient is becoming noticeable with miniaturization. Yes.

In the trench capacitor forming step, for example, after forming a pad oxide film, a trench portion is formed in the semiconductor substrate. Thereafter, impurities are diffused into the semiconductor substrate in the trench portion to form a plate electrode, and a capacitor insulating film such as a silicon oxide film is formed on the surface of the semiconductor substrate in the trench portion. Thereafter, for example, a silicon film and a silicon oxide film are repeatedly generated and peeled for forming an electrode portion. In this repeated process, a part of the pad oxide film described above is etched.
Japanese Patent Laid-Open No. 11-168190 (7th page, FIG. 2)

  SUMMARY OF THE INVENTION An object of the present invention is to provide a structure capable of improving the breakdown voltage between capacitors and suppressing a leakage current in a trench capacitor used in a DRAM cell, and a method for manufacturing the same.

  According to a first aspect of the present invention, there is provided a semiconductor substrate, a trench portion formed in the semiconductor substrate, a plate electrode formed on a surface of the semiconductor substrate in the trench portion, and a capacitor insulating film formed in the trench portion. And a trench capacitor including an upper electrode and a pad silicon oxide film formed on a semiconductor substrate adjacent to the trench portion, wherein the side wall portion of the pad silicon oxide film is covered with a nitride film. It is characterized by being.

  According to a second aspect of the present invention, as a method of manufacturing a semiconductor device having a trench capacitor, a step of forming a pad oxide film on a semiconductor substrate, a step of patterning the pad oxide film, and the patterned pad Forming a trench portion in the semiconductor substrate sandwiched between the surface regions of the semiconductor substrate under an oxide film, forming a plate electrode on the surface and side regions of the semiconductor substrate in the trench portion, and the plate Forming a capacitor insulating film on the surface and side surfaces of the semiconductor substrate in the trench portion in which the electrode is formed; forming a buried electrode film in the trench portion so as to cover the capacitor insulating film; and the capacitor Removing the insulating film and the buried electrode film to a predetermined depth and exposing the side wall of the pad oxide film; A step of nitriding the side walls of the serial pad oxide film, characterized in that it comprises a step of forming a further upper electrode on the buried electrode film.

  According to a third aspect of the present invention, as a method of manufacturing a semiconductor device having a trench capacitor, a step of forming a pad oxide film on a semiconductor substrate, a step of patterning the pad oxide film, and the step exposed by patterning Nitriding a sidewall of the pad oxide film; forming a trench portion in the semiconductor substrate sandwiched between surface regions of the semiconductor substrate under the patterned pad oxide film; and the semiconductor substrate in the trench portion Forming a plate electrode on the surface and side regions of the substrate, forming a capacitor insulating film on the surface and side surface of the semiconductor substrate in the trench where the plate electrode is formed, and covering the capacitor insulating film, Forming a buried electrode film in the trench, and further forming an upper electrode on the buried electrode film Characterized in that it comprises a.

  According to the present invention, by forming a relatively dense nitride film on the side wall of the pad oxide film in the trench capacitor, a structure capable of improving the breakdown voltage between the capacitors and suppressing the leakage current can be obtained.

  Embodiments of the present invention will be described below with reference to the drawings.

  1 to 10 show a method of manufacturing a semiconductor device having a trench capacitor according to the first embodiment of the present invention in the order of steps. FIG. 10 shows a trench capacitor portion in a semiconductor device having a trench capacitor according to the first embodiment of the present invention. In this embodiment, a semiconductor device including a DRAM cell having a trench capacitor is configured.

  As shown in FIG. 1, for example, a P-type silicon substrate 10 is prepared as a semiconductor substrate. Next, the N-type impurity layer 11 is embedded in the silicon substrate 10 using, for example, an ion implantation method and a subsequent heat treatment. Further, a pad oxide film 12 made of a silicon oxide film is formed on the surface of the silicon substrate 10 by a thermal oxidation method, for example, with a thickness of about 8 nm. Subsequently, a silicon nitride film 13 is formed on the upper surface of the pad oxide film 12 to a thickness of about 22 nm by, for example, a CVD method. Further, for example, an organic metal is used as a source gas of the CVD method, and a mask silicon oxide film 14 is formed on the upper surface of the silicon nitride film 13 with a thickness of about 200 nm, for example.

  Next, using a photolithography method and a dry etching method, a mask pattern for opening the trench is formed as shown in FIG. For example, the mask silicon oxide film 14 is etched into a predetermined shape by anisotropic etching by RIE, and the silicon nitride film 13 and the pad oxide film 12 are further etched to expose a part of the upper surface of the silicon substrate 10.

  Next, as shown in FIG. 3, the silicon substrate 10 is etched by anisotropic dry etching using the mask silicon oxide film 14 as a mask. Thereby, for example, a trench portion 15 having a depth of about 8 to 9 μm is formed.

  Next, as shown in FIG. 4, a silicon oxide film containing a conductivity type impurity opposite to that of the silicon substrate 10, for example, an arsenic-added silicon oxide film 16 is formed to a thickness of about 30 nm by, eg, CVD, and a resist film 17 is further formed. Application is performed using a spin coat method so as to be embedded in the trench portion 15.

  Next, the arsenic-doped silicon oxide film 16 exposed after removing the resist film 17 to a predetermined depth is removed using, for example, a hydrofluoric acid-based or ammonium fluoride-based aqueous solution. Further, the resist film 16 is removed by, for example, an oxygen ashing method. Further, as shown in FIG. 5, a protective film 18 made of, for example, a silicon oxide film that is an insulating film is formed by the CVD method including the entire opening portion of the trench part, and the trench part 15 including the arsenic-added silicon oxide film 16 is formed. Is coated with a thickness of about 20 to 25 nm. Subsequently, heat treatment is performed at, for example, 900 ° C., and arsenic is diffused from the arsenic-added silicon oxide film 16 into the silicon substrate 10 so as to bury the plate electrode 19.

  Next, the protective film 18 is removed by etching with, for example, a hydrofluoric acid-based or ammonium fluoride-based aqueous solution. Subsequently, the arsenic-added silicon oxide film 16 is removed by etching with, for example, a hydrofluoric acid-based or ammonium fluoride-based aqueous solution, thereby completing the plate electrode forming step.

  Next, as shown in FIG. 6, as a capacitor insulating film 20, a composite film of a silicon nitride film and a silicon oxide film is formed on the entire surface of the silicon substrate 10 including the inner wall of the trench portion 15 by a CVD method, for example, to a thickness of about 5 nm. Form. The capacitor insulating film 20 may be a high dielectric film having a relative dielectric constant of 8 or more, such as a tantalum oxide film, a hafnium oxide film, a titanium oxide film, or the like. Further, a first conductive film 21 made of a polycrystalline silicon film doped with a conductivity type impurity is formed as an embedded electrode film in the trench portion 15 by, for example, a CVD method.

  Next, as shown in FIG. 7, the first conductive film 21 embedded in the trench portion 15 is removed by etching to a predetermined depth, for example, by the RIE method. Subsequently, the exposed capacitor insulating film 20 is removed. Furthermore, the semiconductor substrate 10 is heated to 400 ° C. to 600 ° C., and the side wall of the pad oxide film 12 is nitrided by using a radical nitridation method to form a first nitride film 22 of about 1 to 2 nm. At this time, the exposed side wall of the silicon substrate 10 and the surface of the first conductive film 21 are also nitrided, and a second nitride film 23 and a third nitride film 23a are also formed.

  Although the first nitride film 2 is very thin, its density is fine, so that it has excellent etching resistance. Therefore, the first nitride film 22 formed on the side wall of the pad oxide film 12 prevents biting etching of the pad oxide film 12 in the lateral direction in the etching process of the silicon oxide film, which will be further performed thereafter. To do. In the conventional process, after the biting in the lateral direction generated in the pad oxide film 12, in the conductive film forming process, the conductive film enters the biting portion, and a short circuit due to the conductive film entering from both side walls of the pad oxide film 12 or A phenomenon of leakage current was observed.

  However, as shown in the present embodiment, the side walls of the pad oxide film 12 are protected by nitriding the side walls of the pad oxide film 12 using the radical nitridation method to form the first nitride film 22, thereby Prevent biting etching in the direction.

  Next, as shown in FIG. 8, a silicon oxide film 24 is formed by CVD. Thereafter, anisotropic etching is performed by RIE so that the silicon oxide film 24 remains on the side wall portion of the silicon substrate 10, and the third nitride film 23 a and the silicon oxide film 24 on the first conductive film 21 are removed. . Subsequently, a second conductive film made of a polycrystalline silicon film to which a conductivity type impurity is added is formed on the entire surface of the silicon substrate 10 by, for example, a CVD method so as to be embedded in the upper portion of the trench portion.

  Subsequently, as shown in FIG. 9, the second conductive film 25 is etched back, and the second conductive film 25 is embedded in the upper portion of the trench portion. Subsequently, after the silicon oxide film 24 remaining on the side wall is etched by wet etching or CDE, a polysilicon film made of a polycrystalline silicon film to which a conductivity type impurity is added as shown in FIG. 3 is formed, and an etch back is performed again to form an upper electrode. Thereby, the capacitor forming step is completed.

  Furthermore, a semiconductor device (not shown) having a trench capacitor is completed through a transistor formation step and a multilayer wiring formation step.

  As shown in the present embodiment, the side wall of the pad oxide film 12 is protected by nitriding the side wall of the pad oxide film 12 using a radical nitridation method to form the nitride film 22, and the lateral direction of the pad oxide film 12 by the subsequent etching. Prevents bite etching. Thereby, a semiconductor device including a DRAM memory cell having element characteristics corresponding to miniaturization can be manufactured.

  Also in a semiconductor device having a trench capacitor, it is possible to improve the breakdown voltage between the upper electrodes of the trench part and to prevent the occurrence of leakage current.

  11 to 20 show a method of manufacturing a semiconductor device having a trench capacitor according to the second embodiment of the present invention. FIG. 20 shows a trench capacitor portion in a semiconductor device having a trench capacitor according to the second embodiment of the present invention. This embodiment is basically the same as the first embodiment in that a semiconductor device including a DRAM cell having a trench capacitor is configured. The difference from the first embodiment is that the step of forming the first nitride film in the manufacturing method is provided in a relatively previous stage. In addition, the same code | symbol was attached | subjected to the part same as the 1st Example, and the description was also simplified.

  As shown in FIG. 11, for example, a P-type silicon substrate 10 is prepared as a semiconductor substrate. Next, the N-type impurity layer 11 is embedded in the silicon substrate 10 using, for example, an ion implantation method and a subsequent heat treatment. Further, a pad oxide film 12 made of a silicon oxide film is formed on the surface of the silicon substrate 10 by a thermal oxidation method, for example, with a thickness of about 8 nm. Subsequently, a silicon nitride film 13 is formed on the upper surface of the pad oxide film 12 to a thickness of about 22 nm by, for example, a CVD method. Further, a mask silicon oxide film 14 is formed on the upper surface of the silicon nitride film 13, for example, to a thickness of about 200 nm.

  Next, using photolithography and dry etching, a mask pattern for opening the trench is formed as shown in FIG. The mask silicon oxide film 14 is etched into a predetermined shape by anisotropic etching, and the silicon nitride film 13 and the pad oxide film 12 are further etched to expose a part of the upper surface of the silicon substrate 10.

  Further, the semiconductor substrate 10 is heated to 400 ° C. to 600 ° C., and the sidewalls of the pad oxide film 12 are nitrided by using a plasma nitriding method to form a first nitride film 27 of about 1 to 2 nm. At this time, the surface of the mask silicon oxide film 14 and the exposed surface of the silicon substrate 10 are also nitrided, and a fourth nitride film 28 and a fifth nitride film 29 are formed. The formation of the first nitride film 27 may be performed after the formation of a trench portion described later.

  Although the first nitride film 27 is very thin, its density is fine, so that it has excellent etching resistance. Therefore, the first nitride film 27 formed on the side wall of the pad oxide film 12 prevents biting etching of the pad oxide film 12 in the lateral direction in the etching process of the silicon oxide film, which will be further performed thereafter. To do. In the conventional process, after the biting in the lateral direction generated in the pad oxide film 12, in the conductive film forming process, the conductive film enters the biting portion, and a short circuit due to the conductive film entering from both side walls of the pad oxide film 12 or A phenomenon of leakage current was observed.

  However, as shown in the present embodiment, the side walls of the pad oxide film 12 are protected by nitriding the side walls of the pad oxide film 12 using the plasma nitriding method, and the side walls of the pad oxide film 12 are protected. Prevent biting etching in the direction.

  Next, as shown in FIG. 13, the silicon substrate 10 is etched by anisotropic dry etching using the mask silicon oxide film 14 as a mask. Thereby, for example, a trench portion 15 having a depth of about 8 to 9 μm is formed.

  Next, as shown in FIG. 14, a silicon oxide film containing a conductivity type impurity opposite to the silicon substrate 10, for example, an arsenic-added silicon oxide film 16 is formed to a thickness of about 30 nm by, eg, CVD, and a resist film 17 is further formed. Application is performed using a spin coat method so as to be embedded in the trench portion 15.

  Next, the arsenic-doped silicon oxide film 16 exposed after removing the resist film 17 to a predetermined depth is removed using, for example, a hydrofluoric acid-based or ammonium fluoride-based aqueous solution. Further, as shown in FIG. 15, the resist film 16 is removed by, for example, an oxygen ashing method. Further, a protective film 18 made of, for example, a silicon oxide film, which is an insulating film, is formed by the CVD method including the entire opening of the trench part, and the inner wall surface of the trench part 15 including the arsenic-added silicon oxide film 16 has a thickness of 20 Cover about 25 nm. Subsequently, heat treatment is performed at, for example, 900 ° C., and arsenic is diffused from the arsenic-added silicon oxide film 16 into the silicon substrate 10 so as to bury the plate electrode 19.

  Next, the protective film 18 is removed by etching with, for example, a hydrofluoric acid-based or ammonium fluoride-based aqueous solution. Subsequently, the arsenic-added silicon oxide film 16 is removed by etching with, for example, a hydrofluoric acid-based or ammonium fluoride-based aqueous solution, thereby completing the plate electrode forming step.

  Next, as shown in FIG. 16, a composite film of a silicon nitride film and a silicon oxide film is formed as a capacitor insulating film 20 on the entire surface of the silicon substrate 10 including the inner wall of the trench portion 15 by a CVD method, for example, with a thickness of about 5 nm. Form. The capacitor insulating film 20 may be a high dielectric film having a relative dielectric constant of 8 or more, such as a tantalum oxide film, a hafnium oxide film, a titanium oxide film, or the like. Further, a first conductive film 21 made of a polycrystalline silicon film doped with a conductivity type impurity is formed as an embedded electrode film in the trench portion 15 by, for example, a CVD method.

  Next, as shown in FIG. 17, the first conductive film 21 embedded in the trench portion 15 is removed by etching to a predetermined depth, for example, by the RIE method. Subsequently, the exposed capacitor insulating film 20 is removed.

  Next, as shown in FIG. 18, a silicon oxide film 24 is formed by CVD. Thereafter, anisotropic etching is performed by the RIE method so that the silicon oxide film 24 remains on the side wall portion of the silicon substrate 10. Subsequently, a second conductive film 25 made of a polycrystalline silicon film to which a conductive impurity is added is formed on the entire surface of the silicon substrate 10 by, for example, a CVD method so as to be embedded in the upper portion of the trench portion.

  Subsequently, as shown in FIG. 19, the second conductive film 25 is etched back, and the second conductive film 25 is embedded in the upper portion of the trench portion. Subsequently, after the silicon oxide film 24 remaining on the side wall is etched by a wet etching method, a third conductive film made of a polycrystalline silicon film to which a conductivity type impurity is added is further formed by, eg, CVD, as shown in FIG. An upper electrode is formed by forming the film 26 and performing etch back again. Thereby, the capacitor forming step is completed.

  Furthermore, a semiconductor device (not shown) having a trench capacitor is completed through a transistor formation step and a multilayer wiring formation step.

  As shown in the present embodiment, the side wall of the pad oxide film 12 is protected by nitriding the side wall of the pad oxide film 12 by using a plasma nitriding method and forming the nitride film 27, and the lateral direction of the pad oxide film 12 is etched by the subsequent etching. Prevents bite etching. Thereby, a semiconductor device including a DRAM memory cell having element characteristics corresponding to miniaturization can be manufactured.

  Also in a semiconductor device having a trench capacitor, it is possible to improve the breakdown voltage between the upper electrodes of the trench part and to prevent the occurrence of leakage current.

  Further, since this embodiment is performed at a relatively early stage of the entire process, the effect of protecting the side wall of the pad oxide film 12 is great.

  Note that the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit of the present invention.

  For example, in addition to radical nitriding and plasma nitriding, the first nitride film may be ion-assisted nitriding or electron beam excited plasma as long as it can form a relatively dense thin film.

  Further, the trench capacitor forming process has various modifications other than those shown as examples, and the step of forming the first nitride film may be selected accordingly.

  As the buried electrode film, in addition to the impurity-doped polycrystalline silicon film, an impurity-doped amorphous silicon film, a metal film such as tungsten, titanium, nickel, cobalt, molybdenum, and tantalum, or a silicide film thereof, For example, a tungsten silicide film, a titanium silicide film, or the like may be used. However, when a metal film or a silicide film is used, the heat treatment conditions and the like need to be lowered, for example, corresponding to the metal film and the silicide film. In addition, it is necessary to pay attention to the chemical solution at the time of etching and select one that shows appropriate conditions.

The schematic diagram of the cross section which shows 1st Embodiment of the manufacturing method of the semiconductor device by this invention in process order. The schematic diagram of the cross section which shows 1st Embodiment of the manufacturing method of the semiconductor device by this invention in process order. The schematic diagram of the cross section which shows 1st Embodiment of the manufacturing method of the semiconductor device by this invention in process order. The schematic diagram of the cross section which shows 1st Embodiment of the manufacturing method of the semiconductor device by this invention in process order. The schematic diagram of the cross section which shows 1st Embodiment of the manufacturing method of the semiconductor device by this invention in process order. The schematic diagram of the cross section which shows 1st Embodiment of the manufacturing method of the semiconductor device by this invention in process order. The schematic diagram of the cross section which shows 1st Embodiment of the manufacturing method of the semiconductor device by this invention in process order. The schematic diagram of the cross section which shows 1st Embodiment of the manufacturing method of the semiconductor device by this invention in process order. The schematic diagram of the cross section which shows 1st Embodiment of the manufacturing method of the semiconductor device by this invention in process order. The schematic diagram of the cross section which shows 1st Embodiment of the manufacturing method of the semiconductor device by this invention in process order. The schematic diagram of the cross section which shows 2nd Embodiment of the manufacturing method of the semiconductor device by this invention in process order. The schematic diagram of the cross section which shows 2nd Embodiment of the manufacturing method of the semiconductor device by this invention in process order. The schematic diagram of the cross section which shows 2nd Embodiment of the manufacturing method of the semiconductor device by this invention in process order. The schematic diagram of the cross section which shows 2nd Embodiment of the manufacturing method of the semiconductor device by this invention in process order. The schematic diagram of the cross section which shows 2nd Embodiment of the manufacturing method of the semiconductor device by this invention in process order. The schematic diagram of the cross section which shows 2nd Embodiment of the manufacturing method of the semiconductor device by this invention in process order. The schematic diagram of the cross section which shows 2nd Embodiment of the manufacturing method of the semiconductor device by this invention in process order. The schematic diagram of the cross section which shows 2nd Embodiment of the manufacturing method of the semiconductor device by this invention in process order. The schematic diagram of the cross section which shows 2nd Embodiment of the manufacturing method of the semiconductor device by this invention in process order. The schematic diagram of the cross section which shows 2nd Embodiment of the manufacturing method of the semiconductor device by this invention in process order.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Silicon substrate 11 N-type impurity layer 12 Pad oxide film 13 Silicon nitride film 14 Silicon oxide film for mask 15 Trench part 16 Arsenic doped silicon oxide film 17 Resist film 18 Protective film 19 Plate electrode 20 Capacitor insulating film 21 First conductive film 22, 27 First nitride film 23 Second nitride film 23a, 29 Third nitride film 24 Silicon oxide film 25 Second conductive film 26 Third conductive film 28 Fourth nitride film 29 Fifth nitride film 30 trench capacitor

Claims (5)

A semiconductor substrate;
A trench formed in the semiconductor substrate;
A plate electrode formed on the surface of the semiconductor substrate in the trench portion;
A capacitor insulating film and an upper electrode formed in the trench,
A semiconductor device having a trench capacitor including a pad silicon oxide film formed on a semiconductor substrate adjacent to the trench portion,
A semiconductor device having a trench capacitor, wherein a side wall portion of the pad silicon oxide film is covered with a nitride film. Forming a pad oxide film on the semiconductor substrate;
Patterning the pad oxide film;
Forming a trench portion in the semiconductor substrate sandwiched between the surface regions of the semiconductor substrate under the patterned pad oxide film;
Forming plate electrodes on the surface and side regions of the semiconductor substrate in the trench portion;
Forming a capacitor insulating film on the surface and side surfaces of the semiconductor substrate in the trench portion where the plate electrode is formed;
Forming a buried electrode film in the trench so as to cover the capacitor insulating film;
Removing the capacitor insulating film and the buried electrode film to a predetermined depth, exposing a side wall of the pad oxide film;
Nitriding sidewalls of the exposed pad oxide film;
Forming a top electrode on the buried electrode film, and a method for manufacturing a semiconductor device having a trench capacitor.   3. The method of manufacturing a semiconductor device having a trench capacitor according to claim 2, wherein either a radical nitriding method or a plasma nitriding method is used as a method of nitriding the side wall of the pad oxide film. Forming a pad oxide film on the semiconductor substrate;
Patterning the pad oxide film;
Nitriding sidewalls of the pad oxide film exposed by patterning;
Forming a trench portion in the semiconductor substrate sandwiched between the surface regions of the semiconductor substrate under the patterned pad oxide film;
Forming plate electrodes on the surface and side regions of the semiconductor substrate in the trench portion;
Forming a capacitor insulating film on the surface and side surfaces of the semiconductor substrate in the trench portion where the plate electrode is formed;
Forming a buried electrode film in the trench so as to cover the capacitor insulating film;
And a step of forming an upper electrode on the buried electrode film. A method of manufacturing a semiconductor device having a trench capacitor.   5. The method of manufacturing a semiconductor device having a trench capacitor according to claim 4, wherein either a radical nitriding method or a plasma nitriding method is used as a method of nitriding the side wall of the pad oxide film.

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