JP2006279371A - Power-on reset circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reliably reset an internal circuit even when a rise time of a power supply voltage is long or when there are variations in transistor manufacturing.
A power-on reset circuit 1 includes a P-channel MOS transistor 2, N-channel MOS transistors 3a to 3d connected to the drain of the P-channel MOS transistor 2, and an input section connected to the drain and N-channel of the P-channel MOS transistor. The inverter circuit 4 connected to the connection point of the gates of the MOS transistors 3a to 3d, the N-channel MOS transistor 5 connected to the ground side terminal of the inverter circuit 4, and the voltage of the power source from the threshold of the P-channel MOS transistor 2 A bias circuit 9 is used to turn on the N-channel MOS transistor 5 when it becomes larger than a predetermined value.
[Selection] Figure 1

Description

  The present invention relates to a power-on reset circuit for generating a reset signal for initializing an internal circuit when a power supply is turned on in a semiconductor integrated circuit.

Conventionally, various power-on reset circuits have been provided (see, for example, Patent Document 1 and Patent Document 2).
FIG. 3 is a circuit diagram of a power-on reset circuit disclosed in Patent Document 1. In FIG. A power-on reset circuit 100 shown in FIG. 3 includes a resistor 101 having one end connected to the power source of the power supply voltage Vcc, a capacitor 102 having one electrode connected to the other end of the register 101, and the other electrode grounded, An inverter circuit 103 whose input is connected to a connection point (node N100) between the register 101 and the capacitor 102, and a P-channel MOS transistor 104 whose source is connected to the node N100, whose drain is grounded, and whose gate is connected to the power supply. It is comprised by. The register 101 and the capacitor 102 constitute a CR circuit.

  When the power supply is turned on, the increase in the input potential of the inverter circuit 103 (the potential of the node N100) is higher than the increase (rise) of the power supply voltage Vcc of the power supply in accordance with a time constant determined by the resistance value of the register 101 and the capacitance value of the capacitor 102. Late. When the potential of the node N100 rises as the capacitor 102 is charged and exceeds the threshold value of the inverter circuit 103, the output of the inverter circuit 103 is inverted (changed from "High" level to "Low" level), A reset signal with a pulse width as the delay time is output.

  When the power is turned off, the P-channel MOS transistor 104 is turned on, and the charge charged in the capacitor 102 is quickly discharged.

  FIG. 4 is a circuit diagram of a power-on reset circuit disclosed in Patent Document 2. The power-on reset circuit 200 shown in FIG. 4 includes a P-channel MOS transistor 201, a register 202, a P-channel MOS transistor 203, a capacitor 204, and inverter circuits 205, 206, and 207. Inverter circuits 205, 206, and 207 are configured by P-channel MOS transistors 205a, 206a, and 207a and N-channel MOS transistors 205b, 206b, and 207b.

When the power supply is turned on and the power supply voltage Vcc reaches the threshold value of the P channel MOS transistor 203, the capacitor 204 is charged, the output of the inverter circuit 205 is inverted (from "High" level to "Low" level), and the inverter circuit 206 Is inverted (from “Low” level to “High” level), the output of the inverter circuit 207 is inverted (from “High” level to “Low” level), and a reset signal having a predetermined pulse width Is output.
Japanese Utility Model Publication No. 7-16432 Japanese translation of PCT publication No. 2002-516507

  In the power-on reset circuit 100 of Patent Document 1, when the rise time of the power supply voltage Vcc is longer than the time constant of the CR circuit constituted by the register 101 and the capacitor 102, no reset pulse is output. For this reason, it is necessary to make the time constant value of the CR circuit larger than the rise time of the power supply voltage Vcc. When the rise time of the power supply voltage Vcc is long, the CR circuit needs to be constituted by a large-sized resistor element or capacitor element. There is.

  Further, in the power-on reset circuit 200 of Patent Document 2, the threshold value Vthn of the N-channel MOS transistor provided in the subsequent stage of the power-on reset circuit 200 is larger than the threshold value Vthp of the P-channel MOS transistor 203 due to variations in transistor manufacturing. If this happens, the N-channel MOS transistor cannot be turned on and the internal circuit cannot be reset.

  Therefore, an object of the present invention is to provide a power-on reset circuit capable of reliably resetting an internal circuit even when a rise time of a power supply voltage is long or when there are variations in transistor manufacturing.

  A power-on reset circuit according to the present invention includes a P-channel MOS transistor having a source connected to a power supply and a gate grounded, a capacitive element connected to a drain of the P-channel MOS transistor, and an input section having the P-channel MOS transistor An inverter circuit having a power source side terminal connected to the power source, a switching element connected to a ground side terminal of the inverter circuit, and a voltage of the power source being the P And a control circuit that turns on the switching element when the voltage of the power source at which the channel MOS transistor is turned on is greater than a predetermined value.

  In the power-on reset circuit, the switching element is an N-channel MOS transistor having a drain connected to the ground-side terminal of the inverter circuit and a source grounded, and the control circuit is configured such that the voltage of the power source is the P When the voltage of the power supply at which the channel MOS transistor is turned on becomes larger than a predetermined value, a voltage higher than the threshold value of the N channel MOS transistor is supplied to the gate of the N channel MOS transistor.

  According to the present invention, since the switching element is turned off for a certain time after the P-channel MOS transistor is turned on, the output of the inverter circuit is maintained at the “High” level for a certain time, and the rise time of the power supply voltage is long. Even in such a case, a reset signal equal to or higher than the threshold value Vthn of the N-channel MOS transistor can be surely output, and the internal circuit can be surely reset even if there are variations in transistor manufacturing.

  Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.

  First, the circuit configuration of the power-on reset circuit 1 in the embodiment of the present invention will be described with reference to FIG. FIG. 1 is a circuit diagram of a power-on reset circuit according to the present embodiment. The P channel MOS transistor is referred to as a Pch transistor, and the N channel MOS transistor is referred to as an Nch transistor.

  The power-on reset circuit 1 shown in FIG. 1 includes a Pch transistor 2 whose source is connected to the power supply of the power supply voltage Vcc and whose gate is grounded and whose threshold is Vthp. The power-on reset circuit 1 includes Nch transistors 3 a to 3 d in which the source and drain are grounded and the gate is connected to the drain of the Pch transistor 2. The Pch transistor 2 functions as a resistance element, and the Nch transistors 3a to 3d function as capacitive elements. The Pch transistor 2 and the Nch transistors 3a to 3d constitute a CR circuit.

  The power-on reset circuit 1 includes an inverter circuit 4 whose input is connected to a connection point (node RCOUT) between the drain of the Pch transistor 2 and the gates of the Nch transistors 3a to 3d. The inverter circuit 4 includes the Pch transistor 4a. And an Nch transistor 4b. The gate of the Pch transistor 4 a and the gate of the Nch transistor 4 b are connected, and the connection point is the input part of the inverter circuit 4. The drain of the Pch transistor 4 a and the drain of the Nch transistor 4 b are connected, and the connection point (node XRCOUT) is the output part of the inverter circuit 4. The source of the Pch transistor 4a (the power supply side terminal of the inverter circuit 4) is connected to the power supply, and the source of the Nch transistor 4b (the ground side terminal of the inverter circuit 4) is connected to the drain of the Nch transistor 5 described later.

The power-on reset circuit 1 includes an Nch transistor 5 whose drain is connected to the source of the Nch transistor 4b of the inverter circuit 4 (the ground side terminal of the inverter circuit 4) and whose threshold is Vthn.
The power-on reset circuit 1 includes an inverter circuit 6 whose input section is connected to the output section of the inverter circuit 4, and inverter circuits 7 and 8 whose respective input sections are connected to the output section of the inverter circuit 6. The outputs of the circuits 7 and 8 are the output (node ACL) of the power-on reset circuit 1.

The power-on reset circuit 1 includes a bias circuit (control circuit) 9 configured by Pch transistors 9a and 9b and Nch transistors 9c and 9d for controlling on / off of the Nch transistor 5. The threshold value of the Pch transistor 9a is Vthp, and its gate and its drain are connected (diode connection). Nch transistor 9c has a threshold value of Vthn, its gate and its drain are connected (diode connection), and this connection point (node RG) is connected to the gate of Nch transistor 5. The power supply is connected to the source of the Pch transistor 9a, the drain of the Pch transistor 9a is connected to the source of the Pch transistor 9b, the drain of the Pch transistor 9b is connected to the drain of the Nch transistor 9c, and the source of the Nch transistor 9c is the Nch transistor 9d. And the source of the Nch transistor 9d is grounded. The gate of the Pch transistor 9b is grounded, and the outputs of the inverter circuits 7 and 8 are connected to the gate of the Nch transistor 9d. It is assumed that the voltage drop can be ignored in Pch transistor 9b and Nch transistor 9d.
In this bias circuit 9, when the power supply voltage Vcc becomes equal to or higher than the sum (Vthp + Vthn) of the threshold value Vthp of the Pch transistor 9a and the threshold value Vthn of the Nch transistor 9c, the Pch transistor 9a and the Nch transistor 9c are turned on, and the potential of the node RG The threshold voltage Vthn of the Nch transistor 5 is exceeded, and the Nch transistor 5 is turned on.

The power-on reset circuit 1 includes a Pch transistor 10 whose source is connected to a power source, the outputs of the inverter circuits 7 and 8 are connected to the gate of the Pch transistor 10, and the drain is connected to the node RCOUT.
The power-on reset circuit 1 includes a Pch transistor 11 having a source connected to the node RCOUT, a gate connected to a power supply, and a drain grounded.

  Next, the circuit operation of the power-on reset circuit 1 whose circuit configuration is shown in FIG. 1 will be described with reference to FIG. 2 is a waveform diagram showing the circuit operation of the power-on reset circuit 1 of FIG. 1. (a) is the power supply voltage Vcc, (b) is the potential of the node RCOUT, (c) is the potential of the node RG, (d) Represents the potential of the node XRCOUT, and (e) represents the potential of the node ACL. However, this is a case where the rise time of the power supply voltage Vcc is longer than the time constant of the CR circuit constituted by the Pch transistor 2 and the Nch transistors 3a to 3d.

  In the time T1 until the power supply is turned on and the power supply voltage Vcc rises and reaches the threshold value Vthp of the Pch transistor 2, the Pch transistor 2 remains off and the potential of the node RCOUT remains 0 (V). The potential of node RG is less than threshold value Vthn of Nch transistor 5. At this time, since the Pch transistor 4a of the inverter circuit 4 is turned on when the power supply voltage Vcc reaches the threshold value Vthp of the Pch transistor 4, the potential of the node XRCOUT rises with the rise of the power supply voltage Vcc, and the potential of the node XRCOUT becomes When the threshold value of the circuit 6 is exceeded, the outputs of the inverter circuits 7 and 8 (the potential of the node ACL) change from the “Low” level to the “High” level.

When the power supply voltage Vcc reaches the threshold value Vthp of the Pch transistor 2 (time T2 in FIG. 2), the Pch transistor 2 is turned on, and then the potential of the node RCOUT immediately becomes the power supply voltage Vcc, and the Pch transistor 4a is turned off. Since the potential of the node RG is less than the threshold Vthn of the Nch transistor 5 and the Nch transistor 5 remains off, the node XRCOUT does not go to the “Low” level and maintains a potential equal to or higher than the threshold of the inverter circuit 6. Maintain the “High” level.
At time T3 before the power supply voltage Vcc reaches (Vthp + Vthn), the potential of the node RG is less than the threshold value Vthn of the Nch transistor 5, and the Nch transistor 5 remains off. Therefore, the node XRCOUT does not become the “Low” level. The potential equal to or higher than the threshold value of the inverter circuit 6 is maintained, and the node ACL also maintains the “High” level.

Further, when the power supply voltage Vcc rises and reaches (Vthp + Vthn) (time T4 in FIG. 2), the node RG becomes equal to or higher than Vthn, the Nch transistor 5 is turned on, and the Nch transistor 4b is also turned on. The node ACL becomes “Low” level, and the node ACL also becomes “Low” level.
With the above operation, a reset signal equal to or higher than the threshold value Vthn of the N-channel MOS transistor provided at the subsequent stage of the node ACL is output from the power-on reset circuit 1.

When the node ACL becomes the “Low” level, the Nch transistor 9d of the bias circuit 9 is turned off, and no current flows from the power supply side to the ground side in the bias circuit 9.
Further, when the node ACL becomes the “Low” level, the Pch transistor 10 is turned on, whereby the Pch transistor 2 is turned off and the current through the Pch transistor 2 does not flow.
Thereby, after the output (reset signal) of the power-on reset circuit 1 becomes “Low” level, unnecessary current does not flow in the power-on reset circuit 1 and unnecessary power is not consumed.

When the power supply is turned off, the Pch transistor 11 is turned on, a discharge path for the charges charged in the Nch transistors 3a to 3d is formed, and the charges charged in the Nch transistors 3a to 3d are quickly discharged.
Thus, it is possible to prevent the Nch transistors 3a to 3d from being charged when the power is turned on next time, and the reset signal is reliably output from the power-on reset circuit 1.

  According to the power-on reset circuit 1 of the embodiment described above, the Nch transistor 5 remains off until the power supply voltage Vcc reaches (Vthp + Vthn) even if the power supply voltage Vcc reaches the threshold value Vthp of the P-channel transistor 2. Even if the rise time of the power supply voltage becomes long, a reset signal equal to or higher than the threshold value Vthn of the N-channel MOS transistor can be output, and the internal circuit can be reset even if there are variations in transistor manufacturing.

  The preferred embodiments of the present invention have been described above. However, the present invention is not limited to the above-described embodiments, and various design changes can be made as long as they are described in the claims.

The circuit diagram of the power-on reset circuit in embodiment of this invention. FIG. 2 is a waveform diagram showing an operation of the power-on reset circuit of FIG. 1. The circuit diagram of the conventional power-on reset circuit. The circuit diagram of the conventional power-on reset circuit.

Explanation of symbols

1 Power-on reset circuit 2 P-channel MOS transistor (Pch transistor)
3a to 3d N-channel MOS transistor (Nch transistor)
4 Inverter circuit 5 N channel MOS transistor (Nch transistor)
9 Bias circuit 9a P-channel MOS transistor (Pch transistor)
9c N-channel MOS transistor (Nch transistor)

Claims (2)

A P-channel MOS transistor having a source connected to a power source and a gate grounded;
A capacitive element connected to the drain of the P-channel MOS transistor;
An inverter circuit in which an input unit is connected to a connection point between the drain of the P-channel MOS transistor and the capacitive element, and a power supply side terminal is connected to the power supply;
A switching element connected to the ground side terminal of the inverter circuit;
A power-on reset circuit comprising: a control circuit that turns on the switching element when the voltage of the power source becomes greater than a predetermined value by the voltage of the power source that turns on the P-channel MOS transistor. The switching element is an N-channel MOS transistor having a drain connected to the ground-side terminal of the inverter circuit and a source grounded.
The control circuit supplies a voltage equal to or higher than a threshold value of the N-channel MOS transistor to the gate of the N-channel MOS transistor when the voltage of the power source becomes larger than a predetermined value by the voltage of the power source that turns on the P-channel MOS transistor. The power-on reset circuit according to claim 1.

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