JP2006269665A - Thin film transistor circuit and manufacturing method thereof - Google Patents

Abstract

The present invention provides a CMOS thin film transistor circuit having a high degree of integration per unit area and a method for manufacturing the same.
The present invention relates to a first semiconductor layer (4) disposed on a substrate (2), and a first gate insulating layer (5) on the first semiconductor layer (4). A gate electrode (6) disposed; and a second semiconductor layer (8) disposed on the gate electrode (6) via a second gate insulating layer (7), wherein the second semiconductor layer A stacked thin film transistor circuit configured such that a source region (8s) and a drain region (8d) of (8) overlap with a source region (4s) and a drain region (8d) of the first semiconductor layer (4); In particular, when used in a flat display device, the area can be reduced by 70% or less compared to the conventional case.
[Selection] Figure 2A

Description

  The present invention relates to a stacked thin film transistor circuit, and more particularly to a thin film CMOS circuit formed on a light transmissive substrate and a method for manufacturing the same.

  A flat display device typified by a liquid crystal display device is characterized by being lightweight, thin, and low power consumption. Utilizing this feature, flat display devices are used in various fields.

However, in recent years, such surface display devices are required to have higher definition, thinner thickness, and higher functionality, and various researches and developments have been made to cope with them. In order to achieve such high definition, it is necessary to miniaturize the connection pitch with the external drive circuit as the display pixels become finer. A technique of achieving a fine connection pitch by forming a part of an external drive circuit integrally on a substrate using a semiconductor thin film such as polycrystalline silicon (p-Si) has been put into practical use.
In addition, in order to achieve high functionality, attempts have been made to incorporate a signal processing function circuit into the display cell itself.

  However, when a circuit is integrated on a substrate, there is a problem that it is difficult to reduce the size of the peripheral area with respect to the display area, that is, a so-called frame area.

FIG. 1A is an overall schematic diagram using general design rules of a conventional polycrystalline silicon CMOS or inverter integrated circuit structure. FIG. 1B is a cross-sectional view taken along line aa ′ in FIG. 1A. In this conventional example, an undercoat 3 is formed on a glass substrate 2, an a-Si layer is deposited thereon, and this layer is irradiated with laser light to form a polycrystalline silicon layer 4. Next, the gate electrode 6 is formed through the insulating layer 5, and the n-ch TFT9 region and the p-ch TFT10 region are ion-implanted with different dopants (for example, P (phosphorus) and B (boron)). -ch TFT 9 and p-ch TFT 10 are formed, in which 4s denotes a source, 4c denotes a channel, and 4d denotes a drain region, and after forming the insulating layer 7, contact holes 8 are formed into the source 4s, the drain 4d, and the drain 4d, respectively. As shown in the figure, the connection wiring 8 ′ is formed so as to fill the contact hole 8. As a result, the power supply (V _DD ) wiring, the GND (V _SS ) wiring, the input ( As shown in Fig. 1A, the CMOS circuit fabricated as described above has an occupation area of 68µm x 60µm and has an n-ch TFT. Channel length is 10 μm, channel width is 20 μm, channel length of p-ch TFT is 8 μm, channel width is 40 μm The

  In such a conventional CMOS or inverter structure, a p-ch TFT and an n-ch TFT are two-dimensionally arranged in parallel, and a gate electrode is formed on each.

  The present invention has been made in view of such a demand for narrowing the TFT CMOS circuit. By creating two TFT circuits stacked in the vertical direction using the gate electrode in common, the present invention has been made. A highly integrated multi-layer thin film transistor circuit and a method for manufacturing the same are provided. Another object of the present invention is to provide a laminated thin film transistor circuit and a manufacturing method that can be suitably used for a flat display device such as a liquid crystal display and can achieve a narrowing of the forehead around the periphery of the display, It occupies less than 70% of the existing area. In one embodiment of the present invention, an occupation area of 48 μm × 60 μm was achieved as shown in FIG. 2A. Furthermore, the present application is also preferably used for high definition and high functionality of the display cell.

The present invention includes a first semiconductor layer disposed on a substrate, a gate electrode disposed on the first semiconductor layer via a first gate insulating layer, and a second gate on the gate electrode. A second semiconductor layer disposed via an insulating layer;
The first and second semiconductor layers each include a source region and a drain region across a channel region formed above and below the gate electrode,
A stacked thin film transistor circuit, wherein the source region and the drain region of the second semiconductor layer overlap with the source region and the drain region of the first semiconductor layer.

The present invention is a method of manufacturing a laminated thin film transistor circuit,
(1) forming a first semiconductor layer on a substrate;
(2) forming a gate electrode on the first semiconductor layer via a first gate insulating layer;
(3) First ion implantation is performed using the gate electrode as a mask to form a source, drain, and channel region in the first semiconductor layer;
(4) forming a second semiconductor layer on the gate electrode and the first semiconductor layer via a second gate insulating layer;
(5) A photoresist mask is formed on the second semiconductor layer in a region corresponding to the gate electrode, and second ion implantation is performed using the photoresist mask, so that the source and drain of the second semiconductor layer are formed. The manufacturing method is characterized in that the region overlaps with the source and drain regions of the first semiconductor layer.

By using the laminated thin film transistor circuit of the present invention, for example, the inverter circuit area can be reduced to 70% or less than the conventional one. Furthermore, the area occupied by a common gate electrode semiconductor circuit typified by an inverter circuit, for example, a “NAND circuit” or a “NOR” circuit can be reduced. Furthermore, by forming the laminated thin film transistor circuit of the present invention in an integrated and integrated type, for example, the “frame” of the TFT liquid crystal display can be narrowed.
In addition, the functional circuit can be integrated into the cell without increasing the area of the display cell region.

An embodiment of a thin film transistor CMOS circuit (inverter) composed of an n-ch TFT and a p-ch TFT of the present invention will be described with reference to the drawings.
It should be noted that the present invention is not limited to the following examples, and it is obvious that various modifications and changes can be made within the scope defined by the claims.

  FIG. 2A is an overall schematic diagram of the CMOS configuration of the stacked thin film transistor of the present invention. 2B and 2C are cross-sectional views taken along lines bb ′ and c- in FIG. 2A, respectively. FIG. 2D shows a circuit diagram configuration of the laminated thin film transistor circuit of the present invention.

  As shown in FIG. 2B, a 200 nm thick SiOx undercoat insulating layer 3 is deposited on a glass substrate 2 by a plasma chemical vapor deposition (P-CVD) method. Here, the substrate may be a transparent substrate, that is, a substrate that transmits desired light from the back surface of the substrate, and a glass substrate is preferably used, but a quartz substrate, a resin substrate, or the like can also be used. 3A to 3F show plan views of the CMOS structure formed in each manufacturing process.

  Next, a first amorphous silicon (a-Si: H) layer having a thickness of 50 nm is deposited on the undercoat layer 3 by a P-CVD method, and this a-Si: H layer is formed into a line-shaped excimer laser beam. A first polycrystal Si layer for forming an n-channel TFT is formed by a so-called excimer laser annealing (ELA) process using GaN. The average crystal grain size is 0.2 to 0.4 μm. Next, a first polycrystalline silicon island layer 4 is formed by performing a photo-etching process (PEP). The polycrystalline silicon island layer 4 formed in this step corresponds to the range indicated by the thick frame in FIG. 3A.

  Next, a first SiOx gate insulating layer 5 having a thickness of 150 nm is deposited thereon by a P-CVD method.

  A gate material (molybdenum silicide: MoSix) having a thickness of 200 nm is deposited on the gate insulating layer 5 by sputtering, and a gate electrode 6 is formed by PEP. The gate electrode 6 formed in this step corresponds to a region indicated by a thick frame in FIG. 3B.

Next, the first phosphorus ion implantation (4 ^{× 10 15} P ⁺ / cm ^{2 at} 150 keV) for forming the source and drain of the n-channel TFT is performed using the gate electrode as a mask. At this time, the source region and the drain region are self-aligned with the gate electrode 6. As a result, the source region 4s, the drain region 4d, and the channel region 4c are formed in the first polycrystalline silicon island layer 4. Note that the photoresist produced by PEP for forming the gate electrode may be removed before or after the ion implantation. Here, the n-channel TFT in this example shows Vth; +0.8 V, μn; 120 cm ² / Vsec.

  Next, a second SiOx gate insulating layer 7 having a thickness of 200 nm is deposited by P-CVD so as to cover the first SiOx gate insulating layer 5 and the gate electrode 6.

Next, a second a-Si: H layer having a thickness of 70 nm is deposited by a P-CVD method, and this is subjected to ELA treatment to form a second polycrystalline Si layer. The average crystal grain size is 0.2 to 0.4 μm. Next, a second polycrystalline silicon island layer 8 for forming a p-channel TFT is formed by PEP. In this second polycrystalline silicon island layer 8, the partial region 13 of the polycrystalline silicon island layer 8 corresponding to the contact hole forming region 14a reaching the first n-ch TFT drain region is removed in advance. The second polycrystalline silicon island layer 8 formed in this step and the removed region 13 correspond to the region indicated by the thick frame in FIG. 3C.
The first and second polycrystalline silicon island layers may be formed as quasi-single crystalline silicon island layers having an average crystal grain size exceeding 10 μm depending on laser annealing conditions.

  Next, a photoresist mask is formed. This mask includes a p-channel gate region 14b, a contact hole formation region 14a including at least the removed region 13, and a contact hole formation region 10c to the source region 4s of the underlying n-ch TFT. It is formed by PEP on the region 14c that substantially extends from the containing region to the end of the second polycrystalline silicon region. The pattern exposure of the photoresist used as a mask used at this time is performed from the upper front of the apparatus. The photoresist mask corresponds to a region indicated by a thick frame in FIG. 3D. However, as for the gate pattern, it is desirable to leave a mask about 1 μm on the left and right sides with respect to the channel length of the gate electrode in FIG. 3B.

Next, a second boron ion implantation for forming the source and drain of the p-channel is performed on the second polycrystalline silicon island layer 8 (2 × 10 ¹⁵ B ⁺ / cm ² at 10 keV).

The source region 8s, the drain region 8d, and the channel region 8c of the p-ch TFT thus formed are configured to overlap the source and drain regions of the n-ch TFT through the gate electrode. The p-channel TFT in this example shows Vth; −1.0 V, μp; cm ² / Vsec.

  Following the ion implantation, the photoresist mask is removed, and a 350 nm SiNx passivation layer 9 is deposited by P-CVD.

Next, heat treatment is performed at 500 ° C. for 1 hour in an N ₂ atmosphere to activate the implanted P and B, and recover the crystallinity. As a result, the source region and drain region of each TFT are changed to the low resistance N ⁺ layer and P ⁺ layer.

  Next, contact holes 10a-e are formed by wet etching on the source, drain, and gate electrodes of the n-ch TFT and p-ch TFT by PEP. Reference numeral 10a denotes a contact hole formed to connect the drain region 4d of the lower n-ch TFT to the OUT line. 10b is a contact hole made to connect the source region 8s of the upper p-ch TFT to the Vdd line, but does not reach the source region 4s of the lower n-ch TFT, and the source region 8s The lower n-ch TFT is electrically insulated from the source region 4s and the gate insulating layers 5 and 7. 10c is a contact hole made to connect the source region 4s of the lower n-ch TFT to the GND line. The source region 4s is composed of the source region 8s of the upper p-ch TFT and the gate insulating layers 5 and 7 Is electrically insulated. Reference numeral 10d shown in FIG. 2A denotes a contact hole prepared for connecting the gate electrode to the IN line. Reference numeral 10e denotes a contact hole formed to connect the drain region 8d of the upper p-ch TFT to the OUT line. 10a and 10e are integrally formed, whereby the drain region 8d of the upper p-ch TFT and the drain region of the lower n-ch TFT are electrically connected. The contact hole 10a-e formed in this step corresponds to a region indicated by a thick frame in FIG. 3E.

  Next, a 40 nm thick Mo layer 11 and then a 300 nm thick Al layer 12 are deposited by sputtering, and Al / Mo electrodes and electrode lines are formed by PEP. The Al / Mo electrodes and electrode lines formed in this step correspond to the areas indicated by the thick frames in FIG. 3F.

  Further, passivation formation of the SiNx film and electrode portion opening processing are performed.

  The present invention may further include the following aspects. In this embodiment, a resist film mask pattern aligned with the gate region is formed during the second B ion implantation, and the ion implantation is performed in a self-aligned manner, thereby manufacturing a stacked thin film transistor circuit. (Other steps are the same as in the previous embodiment.) Thereby, the upper channel TFT and the lower channel TFT are completely self-aligned with one gate electrode.

  In this embodiment, in order to form a resist layer mask pattern that is self-aligned with the gate region during the second B ion implantation, the gate electrode is used as a mask from the back side of the glass substrate after the second polycrystalline silicon island layer 8 is formed. A positive resist pattern is formed by resist exposure. Therefore, it is necessary to set the total thickness of the first and second polycrystalline silicon island layers within a range in which the ultraviolet rays for resist exposure can pass through the first and second polycrystalline silicon island layers from the glass substrate. There is. Therefore, in this embodiment, the total thickness of the first and second polycrystalline silicon island layers is 100 nm or less, preferably 70 nm, and the thickness of the second polycrystalline silicon island layer is 70 nm or less, preferably 40 nm. It set so that it might become. The acceleration voltage for B ion implantation is 6 keV, which is 10 keV or less, so that the peak of B ion implantation into the second polysilicon island layer is slightly above the center of the polysilicon layer thickness. Set. The ion implantation peak at an ion acceleration voltage of 6 keV is about 18 nm from the surface. On the other hand, in the case of this embodiment, since the resist masks 14a and 14c shown in FIG. 3D cannot be formed, the gate insulating film is exposed in each contact hole portion. However, the total thickness of the first and second SiOx gate insulating layers 5 and 7 is about 350 nm. On the other hand, the implantation peak of B ions at the acceleration voltage is about 16 nm, and the maximum reachable distance is 150 nm or less. As a result, it is possible to prevent B ions from being implanted into the polycrystalline silicon island layer constituting the source and drain regions of the first n-ch TFT. Therefore, in the previous embodiment, the masks 14a and 14c as shown in FIG. 3D were prepared so that ions in the second ion implantation were not implanted into the polycrystalline silicon island layer 4, but in this embodiment, It is not necessary to form a photoresist mask other than the resist pattern that matches the gate electrode. In this embodiment, the thickness of the first and second polycrystalline silicon island layers can be further increased. In this case, although the amount of ultraviolet rays for resist exposure is further attenuated, the problem of attenuation can be avoided by a method of increasing the intensity of ultraviolet rays or a longer exposure.

  In this embodiment, the second ion implantation for forming the source and drain of the p-ch TFT is performed using the positive resist pattern produced by backside exposure as a mask under the above conditions. As a result, source / drain regions self-aligned with the gate electrode are formed. The source region 8s, the drain region 8d, and the channel region 8c of the p-ch TFT thus formed are configured to overlap the source and drain regions of the n-ch TFT through the gate electrode.

  In the above embodiment, the first TFT is an n-ch type and the second TFT is a p-ch type, and the details thereof are described. However, the respective types may be a p-cn type and an n-ch type. A major change in the process in that case is a change in ion implantation conditions. Specifically, in the first ion implantation, boron ions are implanted at 70 keV. The second ion implantation is to implant phosphorus ions at 27 keV.

  The stacked thin film transistor circuit of the present invention has a structure in which one gate electrode is provided between vertically stacked n-channel TFTs and p-channel TFTs, and the gate electrodes are shared by both TFTs. As a result, the degree of integration per unit area can be reduced to 70% or less, and the area occupied by semiconductor circuits composed of inverter circuits, for example, "NAND circuits" and "NOR" circuits can be reduced. The “picture frame” of the TFT LCD can be narrowed.

  The narrowing effect of the present invention greatly depends on the TFT design rules. Fig. 1A calculated the narrowing effect shown in Fig. 2A in accordance with the general design rules currently applied to TFT LCD panel production. The narrowing effect varies depending on the minimum design dimensions, TFT dimensions, and wiring dimensions and design. In the optimal condition, it can be halved (50%) compared to the conventional example of FIG. 1A.

The multilayer thin film transistor circuit manufactured as described above can be applied to, for example, the following flat display device.
FIG. 4A is a schematic cross-sectional view of a TFT liquid crystal display device which is a typical flat display device. As shown in the figure, a liquid crystal is filled between the substrates 100 and 200. FIG. 4B is a plan view of the flat display device. As shown in the figure, the display unit 400 is composed of active drive liquid crystal cells in a two-dimensional matrix arrangement, and a drive circuit 600 is arranged in a frame region 500 around the display unit 400 on the substrate 100 or 200. The laminated thin film transistor circuit of the present invention is applied to the display unit 400 and / or the drive circuit 600 of such a flat display device. As a result, higher functionality and narrowing of the flat display device can be achieved. The same applies to the case of an organic EL or the like other than the liquid crystal cell.

It is a top view showing a CMOS structure in which conventional p-channel transistors and n-channel transistors are arranged in parallel. FIG. 1B is a cross-sectional view taken along line aa ′ of FIG. 1A. 1 is a schematic view of a laminated thin film transistor circuit of the present invention. FIG. 2B is a cross-sectional view taken along the line bb ′ of FIG. 2A. FIG. 2B is a cross-sectional view taken along the c-line in FIG. 2A. 1 shows a CMOS circuit configuration of a stacked thin film transistor circuit of the present invention. FIG. 5 is a plan view showing a region processed in a corresponding process in the stacked thin film transistor circuit of the present invention. In the thin-film transistor circuit of this invention, it is a top view which shows the area | region processed in a corresponding process. In the thin-film transistor circuit of this invention, it is a top view which shows the area | region processed in a corresponding process. In the thin-film transistor circuit of this invention, it is a top view which shows the area | region processed in a corresponding process. In the thin-film transistor circuit of this invention, it is a top view which shows the area | region processed in a corresponding process. In the thin-film transistor circuit of this invention, it is a top view which shows the area | region processed in a corresponding process. FIG. 2 is a schematic cross-sectional view of a TFT liquid crystal display device that is a typical flat display device. FIG. 4B is a plan view of the flat display device of FIG. 4A.

Explanation of symbols

2 Board
4 First semiconductor layer
6 Gate electrode
8 Second semiconductor layer
10a-10e contact hole

Claims (16)

A first semiconductor layer disposed on the substrate; a gate electrode disposed on the first semiconductor layer via a first gate insulating layer; and a second gate insulating layer disposed on the gate electrode. A second semiconductor layer arranged
The first and second semiconductor layers each include a source region and a drain region across a channel region formed above and below the gate electrode,
A stacked thin film transistor circuit, wherein the source region and the drain region of the second semiconductor layer overlap with the source region and the drain region of the first semiconductor layer. The stacked thin film transistor circuit according to claim 1, wherein the first and second semiconductor layers are made of a polycrystalline silicon layer or a single crystal silicon layer. The n-ch TFT source, drain and channel regions are formed in the first semiconductor layer, and the p-ch TFT source, drain and channel regions are formed in the second semiconductor layer. Item 2. A laminated thin film transistor circuit according to Item 1. The p-ch TFT source, drain and channel regions are formed in the first semiconductor layer, and the n-ch TFT source, drain and channel regions are formed in the second semiconductor layer. Item 2. A laminated thin film transistor circuit according to Item 1. (1) a first contact hole (10a) that reaches the source region or drain region of the first semiconductor layer through the source region or drain region of the second semiconductor layer;
(2) a second contact hole (10e) reaching the source region or drain region of the second semiconductor layer;
(3) a third contact hole (10b) reaching the source region or drain region of the second semiconductor layer;
(4) The fourth contact hole (10c) reaching the source region or the drain region of the first semiconductor layer, and (5) the contact hole (10d) reaching the gate electrode. The laminated thin film transistor circuit described. The drain region of the first semiconductor layer is electrically connected to the drain region of the second semiconductor layer through the first and second contact holes, and the source region of the first semiconductor layer is The stacked thin film transistor circuit according to claim 1, wherein the stacked thin film transistor circuit is electrically insulated from a source region of the second semiconductor layer via an insulating layer. The source region of the first semiconductor layer is electrically connected to the source region of the second semiconductor layer through the first and second contact holes, and the drain region of the first semiconductor layer is The stacked thin film transistor circuit according to claim 1, wherein the stacked thin film transistor circuit is electrically insulated from a drain region of the second semiconductor layer through an insulating layer. A method of manufacturing a laminated thin film transistor circuit,
(1) forming a first semiconductor layer on a substrate;
(2) forming a gate electrode on the first semiconductor layer via a first gate insulating layer;
(3) First ion implantation is performed using the gate electrode as a mask to form a source, drain, and channel region in the first semiconductor layer;
(4) forming a second semiconductor layer on the gate electrode and the first semiconductor layer via a second gate insulating layer;
(5) A photoresist mask is formed on the second semiconductor layer in a region corresponding to the gate electrode, and second ion implantation is performed using the photoresist mask, so that the source and drain of the second semiconductor layer are formed. A manufacturing method comprising forming a region so as to overlap a source region and a drain region of the first semiconductor layer. 9. The manufacturing method according to claim 8, wherein, in the step (5), a photoresist mask is formed by performing pattern exposure on the resist layer deposited on the second semiconductor layer from above the front of the circuit. Method. 9. The manufacturing method according to claim 8, wherein, in the step (5), a photoresist mask is formed in alignment with the gate electrode by performing resist exposure from the back side of the substrate using the gate electrode as a mask. . 11. The manufacturing method according to claim 10, wherein a total thickness of the first semiconductor layer and the second semiconductor layer is 100 nm or less, and a thickness of the second semiconductor layer is 70 nm or less. . In the manufacturing method of Claim 8,
(1) forming a first contact hole (10a) that penetrates the source region or drain region of the second semiconductor layer and reaches the source region or drain region of the first semiconductor layer;
(2) forming a second contact hole (10e) reaching the source region or drain region of the second semiconductor layer;
(3) forming a third contact hole (10b) reaching the source region or drain region of the second semiconductor layer;
(4) forming a fourth contact hole (10c) reaching the source region or drain region of the first semiconductor layer;
(5) The manufacturing method further comprising a step of forming a fifth contact hole (10d) reaching the gate electrode. A plane including a display unit (400) in which display cells are arranged in a matrix between two substrates, a frame region (500) around the display unit, and a drive circuit (600) formed in the frame region A display device,
The flat display device includes the stacked thin film transistor circuit according to claim 1. The flat panel display according to claim 13, wherein the stacked transistor circuit according to claim 1 is included in the drive circuit (600). 14. The flat panel display according to claim 13, wherein the stacked transistor circuit according to claim 1 is included in the display section (400). The flat display device according to claim 13, wherein the display cell is made of a liquid crystal or an organic EL material.

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