JP2006261283A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

A semiconductor device having a tensile strain or a compressive strain mainly only in a channel direction and a method for manufacturing the same.
Gate electrodes 22n and 22p are formed on a semiconductor substrate 1 with a gate insulating film 21 therebetween. Semiconductor layers 4 and 5 made of a material having a lattice spacing different from that of the semiconductor substrate 1 are embedded in the semiconductor substrate 1 so as to sandwich a channel formation region under the gate electrodes 22n and 22p. Source / drain layers 26n and 26p are formed on the semiconductor substrate 1 and the semiconductor layers 4 and 5 on both sides of the gate electrodes 22n and 22p.
[Selection] Figure 11

Description

  The present invention relates to a semiconductor device and a method for manufacturing the same, and includes, for example, an nMOS transistor (hereinafter referred to as nMOS) having tensile strain in the channel direction or a pMOS transistor (hereinafter referred to as pMOS) having compressive strain in the channel direction. The present invention relates to a semiconductor device and a manufacturing method thereof.

  Conventionally, it is known that the mobility of carriers (electrons or holes) in a Si layer is improved by forming a transistor using a Si layer having compressive strain or tensile strain. A Si layer having such a strain is referred to as a strained Si layer.

  In an nMOS, carrier mobility is improved by using a Si layer having tensile strain and increasing the lattice spacing of the Si layer. On the other hand, in the pMOS, the carrier mobility is improved by using a Si layer having a compressive strain and narrowing the lattice spacing of the Si layer. In order to further improve the mobility, rather than increasing the lattice spacing of the Si layer in the 360 degree direction, the lattice spacing of the Si layer is narrowed only in the channel direction in pMOS, and the lattice spacing of the Si layer is expanded only in the channel direction in nMOS. Is desirable.

  Conventionally, after etching the Si substrate using the gate electrode or the side wall of the gate electrode as a mask, a SiGe layer is selectively epitaxially grown at the source / drain positions to utilize the compressive strain from SiGe having a larger lattice spacing than Si. Thus, a technique for forming a pMOS transistor is disclosed (see Non-Patent Document 1). In Non-Patent Document 1, an Si layer having tensile strain is formed by forming a liner film made of a silicon nitride film on the nMOS side.

However, in the technique described in Non-Patent Document 1, since the Si layer having tensile strain is formed by the liner film on the nMOS side, the lattice spacing of the Si layer cannot be increased only in the channel direction.
T. Ghai et al., “A 90nm High Volume Manufacturing Logic Technology Featuring Novel 45nm Gate Length Strained Silicon CMOS Transistors”, IEDM Tech Dig., Pp.978-980, (2003)

  Although it is conceivable to use a SiC layer for nMOS, the SiC layer is not realized at present because it is difficult to perform selective epitaxial growth unlike the SiGe layer.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor device manufacturing method capable of manufacturing a semiconductor device having tensile strain or compressive strain mainly only in the channel direction. .

  Another object of the present invention is to provide a semiconductor device suitable for achieving high performance by having tensile strain or compressive strain only in the channel direction.

  In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention includes a step of forming an element isolation insulating film for partitioning an active region on a semiconductor substrate, and a region serving as a channel between the semiconductor substrate in the active region. Forming a groove, filling the groove with a semiconductor layer having a lattice spacing different from that of the semiconductor substrate by epitaxial growth, and forming the semiconductor layer formed on the semiconductor substrate other than the groove in the groove filling step. Removing the semiconductor substrate until the semiconductor substrate is exposed, and forming a gate electrode on the semiconductor substrate sandwiched between the semiconductor layers embedded in the trench through a gate insulating film.

  In the method of manufacturing a semiconductor device according to the present invention, a groove is formed in a semiconductor substrate before the gate electrode is formed, and the groove is filled with a semiconductor layer by epitaxial growth. Since the semiconductor substrate other than the groove is flat, the semiconductor layer formed on the semiconductor substrate other than the groove is removed until the semiconductor substrate is exposed, so that the semiconductor layer remains in the groove. The region of the semiconductor substrate that becomes the channel is sandwiched between the semiconductor layers having a lattice spacing different from that of the semiconductor substrate, so that the region of the semiconductor substrate sandwiched between the semiconductor layers is subjected to compressive stress or tensile stress along the channel direction. Take it. Thereby, a substrate structure having compressive strain or tensile strain in the channel direction is formed. After forming the substrate structure, a gate electrode is formed through a gate insulating film.

  In order to achieve the above object, a semiconductor device of the present invention includes a semiconductor substrate, a gate electrode formed on the semiconductor substrate via a gate insulating film, and a channel formation region under the gate electrode. The semiconductor substrate is formed by being embedded in a semiconductor substrate, and has a semiconductor layer having a lattice spacing different from that of the semiconductor substrate, and the semiconductor substrate on both sides of the gate electrode and source / drain layers stacked on the semiconductor layer.

  In the semiconductor device of the present invention described above, the channel formation region of the semiconductor substrate is sandwiched between the semiconductor layers having a lattice spacing different from that of the semiconductor substrate, so that the channel formation region sandwiched between the semiconductor layers extends along the channel direction. Compressive stress or tensile stress. Thereby, the semiconductor substrate has a compressive strain or a tensile strain along the channel direction. In this substrate structure, in the present invention, the source / drain layers are stacked on the semiconductor substrate and the semiconductor layer on both sides of the gate electrode. As a result, the source / drain layer can obtain uniform electrical characteristics (resistance, etc.) on both sides of the gate electrode without being affected by the underlying semiconductor layer.

According to the method for manufacturing a semiconductor device of the present invention, a semiconductor device having a tensile strain or a compressive strain mainly in only the channel direction can be manufactured.
According to the semiconductor device of the present invention, a semiconductor device having a tensile strain or a compressive strain only in the channel direction and achieving high performance can be realized.

  Embodiments of a semiconductor device according to the present invention will be described below with reference to the drawings.

(First embodiment)
FIG. 1 is a cross-sectional view of the semiconductor device according to the first embodiment. The semiconductor device according to the present embodiment is a CMOS transistor including an nMOS transistor (hereinafter referred to as nMOS) and a pMOS transistor (hereinafter referred to as pMOS). The nMOS region corresponds to the first region of the present invention, and the pMOS region corresponds to the second region of the present invention.

  For example, an element isolation insulating film 2 made of, for example, STI (Shallow Trench Isolation) is formed on a semiconductor substrate 1 made of Si, which partitions an nMOS region and a pMOS region as active regions.

  A p-type well 3p is formed in the semiconductor substrate 1 in the nMOS region, and an n-type well 3n is formed in the semiconductor substrate 1 in the pMOS region. On the surface layer of the p-type well 3p and the n-type well 3n, channels are formed in the left-right direction in the drawing.

  Two SiC layers (semiconductor layer, first semiconductor layer) 4 are embedded in the semiconductor substrate 1 in the nMOS region so as to sandwich the channel formation region. Similarly, two SiGe layers (semiconductor layer, second semiconductor layer) 5 are embedded in the semiconductor substrate 1 in the pMOS region so as to sandwich the channel formation region.

  The SiC layer 4 formed in the nMOS region has a lattice spacing shorter than that of Si constituting the semiconductor substrate 1. For this reason, tensile stress is applied to the Si layer (p-type well 3p) sandwiched between the SiC layers 4. As a result, the p-type well 3p becomes a Si layer having tensile strain with an increased lattice spacing.

  The SiGe layer 5 formed in the pMOS region has a longer lattice spacing than Si constituting the semiconductor substrate 1. For this reason, compressive stress is applied to the Si layer (n-type well 3n) sandwiched between the SiGe layers 5. For this reason, the n-type well 3n becomes a Si layer having a compressive strain in which the lattice spacing is narrowed.

  A gate electrode 12 n is formed on the semiconductor substrate 1 in the nMOS region with a gate insulating film 11 interposed therebetween. A gate electrode 12p is formed on the semiconductor substrate 1 in the pMOS region with a gate insulating film 11 therebetween. The gate insulating film 11 is made of, for example, silicon oxide. The gate electrodes 12n and 12p are made of polysilicon, for example. Note that a dual gate structure in which the gate electrode 12n is polysilicon containing n-type impurities and the gate electrode 12p is polysilicon containing p-type impurities may be employed.

  A sidewall insulating film 14 made of silicon oxide or silicon nitride is formed on the sidewalls of the gate electrodes 12n and 12p.

  An n-type extension region 15n is formed in the p-type well 3p on both sides of the gate electrode 12n in the nMOS region and immediately below the sidewall insulating film 14. N-type source / drain regions 16n deeper than the n-type extension region 15n are formed in the p-type well 3p and the SiC layer 4 on both sides of the gate electrode 12n and outside the n-type extension region 15n.

  A p-type extension region 15p is formed in the n-type well 3n on both sides of the gate electrode 12p in the pMOS region and immediately below the sidewall insulating film 14. A p-type source / drain region 16p deeper than the p-type extension region 15p is formed in the n-type well 3n and the SiGe layer 5 on both sides of the gate electrode 12p and outside the p-type extension region 15p.

  A silicide layer 17 is formed in the gate electrodes 12n, 12p, the n-type source / drain region 16n, and the p-type source / drain region 16p. The silicide layer 17 is made of, for example, NiSi or CoSi.

  An interlayer insulating film 30 made of, for example, a silicon oxide film is formed so as to cover the nMOS transistor and the pMOS transistor.

  A wiring layer 31 is formed on the interlayer insulating film 30. The wiring layer 31 is electrically connected to the gate electrodes 12n and 12p, the n-type source / drain region 16n, and the p-type source / drain region 16p.

  In the semiconductor device according to the present embodiment, in the nMOS region, two SiC layers 4 having a lattice interval shorter than that of Si are formed so as to sandwich the Si layer (p-type well 3p) under the gate electrode 12n. Yes. The SiC layer 4 applies tensile stress from both sides of the Si layer, and the Si layer under the gate electrode 12n has tensile strain in the channel direction. For this reason, the mobility of the electron used as a carrier of nMOS can be improved.

  In the pMOS, two SiGe layers 5 having a lattice interval longer than that of Si are formed so as to sandwich the Si layer (n-type well 3n) under the gate electrode 12p. The SiGe layer 5 applies compressive stress from both sides of the Si layer, and the Si layer under the gate electrode 12p has compressive strain in the channel direction. For this reason, the mobility of holes serving as carriers of the pMOS can be improved.

  Since the mobility of each carrier of nMOS and pMOS can be improved, a high-performance CMOS transistor is realized.

  Next, a method for manufacturing the semiconductor device according to the present embodiment will be described with reference to FIGS.

  As shown in FIG. 2A, an element isolation insulating film 2 that partitions an nMOS region and a pMOS region is formed on a semiconductor substrate 1 made of, for example, Si by STI technology. The element isolation insulating film 2 is mainly made of a silicon oxide film.

  Next, as shown in FIG. 2B, a p-type impurity (for example, boron) is ion-implanted into the semiconductor substrate 1 in the nMOS region to form a p-type well 3p, and the n-type impurity is formed in the semiconductor substrate 1 in the pMOS region. The n-type well 3n is formed by ion implantation (for example, arsenic or phosphorus). By repeating ion implantation with the nMOS region or the pMOS region masked with a resist, the p-type well 3p and the n-type well 3n are formed.

  Next, as shown in FIG. 3A, the entire surface of the pMOS region is covered, and the nMOS region is wider than the region where the gate electrode is formed, centering on the region where the gate electrode is formed (region serving as a channel). A mask layer 41 covering the region is formed. The mask layer 41 may be a resist mask or a hard mask.

  Next, as shown in FIG. 3B, the semiconductor substrate 1 exposed from the mask layer 41 is etched. Thus, two grooves (first grooves) 1n sandwiching the semiconductor substrate 1 in the nMOS region are formed. Thereafter, the mask layer 41 is removed.

Next, as shown in FIG. 4A, the SiC layer 4 is epitaxially grown on the entire surface of the semiconductor substrate 1. Thereby, SiC layer 4 filling trench 1n is formed on semiconductor substrate 1. In the epitaxial growth, for example, SiH ₄ / C ₃ H ₈ / H ₂ is supplied as gas at ₃ sccm / ₂ sccm / 8 slm, and the temperature is set to 800 ° C.

  Next, as shown in FIG. 4B, the SiC layer 4 formed on the semiconductor substrate 1 other than the trench 1n is removed, and the semiconductor substrate 1 is exposed. This step is performed, for example, by polishing the SiC layer 4 by CMP (Chemical Mechanical Polishing) using the element isolation insulating film 2 as a stopper until the semiconductor substrate 1 is exposed. At this time, in order to completely remove the SiC layer 4 on the semiconductor substrate 1, the surface layer portion of the semiconductor substrate 1 may be polished. As a result, the SiC layer 4 remains in the two trenches 1n in the nMOS region.

  Next, as shown in FIG. 5A, the entire surface of the nMOS region is covered, and the pMOS region is wider than the region where the gate electrode is formed, centering on the region where the gate electrode is formed (region serving as a channel). A mask layer 42 covering the region is formed. The mask layer 42 may be a resist mask or a hard mask.

  Next, as shown in FIG. 5B, the semiconductor substrate 1 exposed from the mask layer 42 is etched. Thus, two grooves (second grooves) 1p sandwiching the semiconductor substrate 1 in the pMOS region are formed. Thereafter, the mask layer 42 is removed.

Next, as shown in FIG. 6A, the SiGe layer 5 is epitaxially grown on the entire surface of the semiconductor substrate 1. Thereby, the SiGe layer 5 filling the trench 1p is formed on the semiconductor substrate 1. In the epitaxial growth, for example, Si ₂ H ₆ / GeH ₄ is flowed at ₂ sccm / 3 sccm as a gas, and the temperature is set to 575 ° C.

  Next, as shown in FIG. 6B, the SiGe layer 5 formed on the semiconductor substrate 1 other than the trench 1p is removed, and the semiconductor substrate 1 is exposed. This process is performed, for example, by polishing the SiGe layer 5 by CMP using the element isolation insulating film 2 as a stopper until the semiconductor substrate 1 is exposed. At this time, the surface layer portion of the semiconductor substrate 1 may be polished in order to completely remove the SiGe layer 5 on the semiconductor substrate 1. As a result, the SiGe layer 5 remains in the two trenches 1p in the pMOS region.

  As described above, a substrate structure having tensile strain in the channel direction due to tensile stress from the SiC layer 4 in the nMOS region and compressive strain in the channel direction due to compressive stress from the SiGe layer 5 in the pMOS region. It is formed. Note that the SiGe layer 5 may be formed in the pMOS region first, and then the SiC layer 4 may be formed in the nMOS region.

  Next, as shown in FIG. 7A, gate electrodes 12n and 12p are formed on the p-type well 3p in the nMOS region and the n-type well 3n in the pMOS region via the gate insulating film 11, respectively. The gate insulating film 11 is a silicon oxide film formed by, for example, a thermal oxidation method. The gate electrodes 12n and 12p are formed, for example, by depositing a polysilicon film and then patterning it with a lithography technique and an etching technique. Note that phosphorus or arsenic may be ion-implanted as an n-type impurity into the gate electrode 12n, and boron may be ion-implanted as a p-type impurity into the gate electrode 12p.

  In the previous step, the SiC layer 4 and the SiGe layer 5 are formed so as to sandwich a region wider than the region where the gate electrodes 12n and 12p are formed in consideration of the positional deviation of the gate electrodes 12n and 12p. Therefore, the gate electrodes 12n and 12p can be reliably formed on the Si layer (p-type well 3p and n-type well 3n).

  Next, as shown in FIG. 7B, an n-type extension region 15n is formed in the p-type well 3p and the SiC layer 4 in the nMOS region, and a p-type extension region is formed in the n-type well 3n and the SiGe layer 5 in the pMOS region. 15p is formed. In this process, for example, phosphorus or arsenic is ion-implanted as an n-type impurity in a state where the pMOS region is covered with a resist or the like, and n-type is applied to the p-type well 3p and the SiC layer 4 on both sides of the gate electrode 12n in the nMOS region. An extension region 15n is formed. After removing the resist or the like, boron is ion-implanted as a p-type impurity while the nMOS region is again masked with the resist or the like, and p-type is applied to the n-type well 3n and the SiGe layer 5 on both sides of the gate electrode 12p in the pMOS region. An extension region 15p is formed.

  Next, as shown in FIG. 8A, a sidewall insulating film 14 is formed on the side walls of the gate electrodes 12n and 12p. A silicon oxide film or a silicon nitride film is deposited on the semiconductor substrate 1 so as to cover the gate electrodes 12n and 12p, for example, by CVD, and then etched back by anisotropic etching, whereby the sidewall insulating film 14 Is formed.

  Next, as shown in FIG. 8B, n-type source / drain regions 16n are formed in the p-type well 3p and the SiC layer 4 in the nMOS region, and p-type are formed in the n-type well 3n and the SiGe layer 5 in the pMOS region. Source / drain regions 16p are formed. In this step, for example, phosphorus or arsenic is ion-implanted as an n-type impurity in a state where the pMOS region is covered with a resist or the like, and the p-type well 3p and the SiC layer 4 on both sides of the sidewall insulating film 14 in the nMOS region are implanted. An n-type source / drain region 16n is formed. After removing the resist and the like, boron is ion-implanted as a p-type impurity in a state where the nMOS region is masked by the resist and the like, and p is applied to the n-type well 3n and the SiGe layer 5 on both sides of the sidewall insulating film 14 in the pMOS region. A type source / drain region 16p is formed.

  Next, as shown in FIG. 9A, silicide layers 17 are formed in the gate electrodes 12n and 12p, the n-type source / drain region 16n, and the p-type source / drain region 16p. In this step, after depositing a metal film such as Ni or Co covering the gate electrodes 12n and 12p, the n-type source / drain region 16n and the p-type source / drain region 16p, the silicide layer 17 is formed by heat treatment, Thereafter, unnecessary metal film is removed.

  Next, as shown in FIG. 9B, a silicon oxide film is deposited by, for example, a CVD method to form an interlayer insulating film 30 that covers the entire surface of the nMOS region and the pMOS region.

  Next, as shown in FIG. 10, contact holes 30a reaching the gate electrodes 12n, 12p, the n-type source / drain region 16n, and the p-type source / drain region 16p are formed in the interlayer insulating film 30. The contact hole 30a is formed by etching the interlayer insulating film 30 using a resist.

  Next, a wiring layer 31 is formed on the interlayer insulating film 30 so as to fill the contact hole 30a (see FIG. 1). If necessary, a semiconductor device is completed through a multilayer wiring formation process.

  In the above embodiment, before forming the gate electrodes 12n and 12p, the trench 1n is formed in the semiconductor substrate 1 in the nMOS region, and the SiC layer 4 is epitaxially grown on the entire surface of the semiconductor substrate 1 so as to fill the trench 1n. Since the semiconductor substrate 1 other than the trench 1n is flat, the Si layer (p-type well 3p) in the nMOS region is polished by polishing the SiC layer 4 on the semiconductor substrate 1 other than the trench 1n using the element isolation insulating film 2 as a stopper. Can be formed.

  Similarly, before forming the gate electrodes 12n and 12p, the trench 1p is formed in the semiconductor substrate 1 in the pMOS region, and the SiGe layer 5 is epitaxially grown on the entire surface of the semiconductor substrate 1 so as to fill the trench 1p. Since the semiconductor substrate 1 other than the trench 1p is flat, the Si layer (n-type well 3n) in the pMOS region is polished by polishing the SiGe layer 5 on the semiconductor substrate 1 other than the trench 1p using the element isolation insulating film 2 as a stopper. Can be formed.

  As described above, a substrate structure having tensile strain in the channel direction due to tensile stress from the SiC layer 4 in the nMOS region and compressive strain in the channel direction due to compressive stress from the SiGe layer 5 in the pMOS region. It is formed.

  In particular, the SiC layer 4 is difficult to selectively grow epitaxially and grows epitaxially on the entire surface of the semiconductor substrate 1. By using the above method, the SiC layer 4 sandwiching the semiconductor substrate 1 in the channel region can be formed. .

  In the present embodiment, the SiC layer 4 and the SiGe layer 5 are formed so as to sandwich a region wider than the region where the gate electrode is formed. Therefore, even when the gate electrodes 12n and 12p are displaced, the gate electrodes 12n and 12p can be formed in the Si layer sandwiched between the SiC layer 4 or the SiGe layer 5. Since the channel under the gate electrodes 12n and 12p is formed only in the Si layer (p-type well 3p or n-type well 3n), carrier mobility can be improved.

  As described above, a semiconductor device including a CMOS transistor having a tensile strain or a compressive strain mainly in the channel direction can be manufactured.

(Second Embodiment)
FIG. 11 is a cross-sectional view of the semiconductor device according to the second embodiment. In the present embodiment, a semiconductor device having a so-called lifted extension (Raised Extension) structure and a lifted source / drain (Raised Source / Drain) structure will be described. In addition, the same code | symbol is attached | subjected to the component similar to 1st Embodiment, and the description is abbreviate | omitted.

  Similar to the first embodiment, the SiC layer 4 is formed in the nMOS region, and the SiGe layer 5 is formed in the pMOS region. As a result, the nMOS region has a tensile strain in the channel direction due to tensile stress from the SiC layer 4, and the pMOS region has a substrate structure that has compressive strain in the channel direction due to compressive stress from the SiGe layer 5.

  A gate electrode 22n is formed on the semiconductor substrate 1 in the nMOS region with a gate insulating film 21 interposed therebetween. A gate electrode 22p is formed on the semiconductor substrate 1 in the pMOS region via a gate insulating film 21. The gate insulating film 11 is made of, for example, silicon oxide. The gate electrodes 22n and 22p are made of polysilicon, for example. The gate electrode 22n may be a dual gate structure made of polysilicon containing n-type impurities, and the gate electrode 22p may be made of polysilicon containing p-type impurities. An insulating film 23 made of, for example, silicon oxide is formed on the side walls of the gate electrodes 22n and 22p.

  On both sides of the gate electrode 22n in the nMOS region, an n-type extension layer 25n is formed on the p-type well 3p and the SiC layer 4. A sidewall insulating film 24 is formed on the n-type extension layer 25n to cover the sidewall of the gate electrode 22n. An n-type source / drain layer 26 n is formed on the n-type extension layer 25 n exposed from the sidewall insulating film 24. Thus, in the nMOS region, the n-type extension layer 25n and the n-type source / drain layer 26n lifted from the main surface of the semiconductor substrate 1 are formed.

  A p-type extension layer 25p is formed on the n-type well 3n and the SiGe layer 5 on both sides of the gate electrode 22p in the pMOS region. A sidewall insulating film 24 is formed on the p-type extension layer 25p to cover the sidewall of the gate electrode 22p. A p-type source / drain layer 26 p is formed on the p-type extension layer 25 p exposed from the sidewall insulating film 24. Thus, in the pMOS region, the p-type extension layer 25p and the p-type source / drain layer 26p lifted from the main surface of the semiconductor substrate 1 are formed.

  A silicide layer 17 is formed on the gate electrodes 22n, 22p, the n-type source / drain layer 26n, and the p-type source / drain layer 26p. The silicide layer 17 is made of, for example, NiSi or CoSi.

  An interlayer insulating film 30 made of, for example, a silicon oxide film is formed so as to cover the nMOS transistor and the pMOS transistor.

  A wiring layer 31 is formed on the interlayer insulating film 30. The wiring layer 31 is electrically connected to the gate electrodes 22n, 22p, the n-type source / drain layer 26n, and the p-type source / drain layer 26p.

  In the semiconductor device according to the present embodiment, in the nMOS region, two SiC layers 4 having a lattice interval shorter than that of Si are formed so as to sandwich the Si layer (p-type well 3p) under the gate electrode 22n2. Yes. A tensile stress is applied from both sides of the Si layer by the SiC layer 4, and the Si layer under the gate electrode 22n has a tensile strain in the channel direction. For this reason, the mobility of the electron used as a carrier of nMOS can be improved.

  In the pMOS, two SiGe layers 5 having a lattice interval longer than that of Si are formed so as to sandwich the Si layer (n-type well 3n) under the gate electrode 22p. The SiGe layer 5 applies compressive stress from both sides of the Si layer, and the Si layer under the gate electrode 22p has compressive strain in the channel direction. For this reason, the mobility of holes serving as carriers of the pMOS can be improved.

  Since the mobility of each carrier of nMOS and pMOS can be improved, a high-performance CMOS transistor is realized.

  Next, a method for manufacturing the semiconductor device according to the present embodiment will be described with reference to FIGS.

  First, similarly to the first embodiment, the steps shown in FIGS. As a result, a substrate structure having tensile strain in the channel direction due to tensile stress from the SiC layer 4 in the nMOS region and compressive strain in the channel direction due to compressive stress from the SiGe layer 5 is formed in the pMOS region. . Note that the SiGe layer 5 may be formed in the pMOS region first, and then the SiC layer 4 may be formed in the nMOS region.

  Next, as shown in FIG. 12A, gate electrodes 22n and 22p are formed on the p-type well 3p in the nMOS region and the n-type well 3n in the pMOS region via the gate insulating film 21, respectively. The gate insulating film 21 is a silicon oxide film formed by, for example, a thermal oxidation method. The gate electrodes 22n and 22p are formed, for example, by depositing a polysilicon film, forming a mask layer 28 having a pattern corresponding to the gate electrode by lithography and etching techniques, and then etching the polysilicon film. The mask layer 28 is made of, for example, silicon oxide, and the mask layer 28 is left in this embodiment. The gate electrode 22n may be ion-implanted with phosphorus or arsenic as an n-type impurity, and the gate electrode 22p may be ion-implanted with boron as a p-type impurity.

  In the previous step, the SiC layer 4 and the SiGe layer 5 are formed so as to sandwich a region wider than the region where the gate electrodes 22n and 22p are formed in consideration of the positional shift of the gate electrodes 22n and 22p. Therefore, the gate electrodes 22n and 22p can be reliably formed on the Si layer (p-type well 3p and n-type well 3n).

  Next, as shown in FIG. 12B, an insulating film 23 made of, for example, silicon oxide is formed on the side walls of the gate electrodes 22n and 22p. For example, a silicon oxide film is deposited on the semiconductor substrate 1 so as to cover the gate electrodes 22n and 22p by a CVD method, and then etched back by anisotropic etching, thereby forming sidewalls of the gate electrodes 22n and 22p. An insulating film 23 is formed.

  Next, as shown in FIG. 13A, an n-type extension layer 25n is formed on the semiconductor substrate 1 in the nMOS region, and a p-type extension layer 25p is formed on the semiconductor substrate 1 in the pMOS region.

In this step, for example, a Si layer is selectively epitaxially grown on the semiconductor substrate 1 on both sides of the gate electrodes 22n and 22p. In this process, since the gate electrodes 22n and 22p are covered with the insulating film 23 and the mask layer 28, the Si layer is not epitaxially grown on the gate electrodes 22n and 22p, but is selectively formed on both sides of the gate electrodes 22n and 22p. The Si layer is epitaxially grown. In the epitaxial growth, for example, Si ₂ H ₆ is flowed at 4 sccm as a gas, and the temperature is set to 600 ° C. Subsequently, n-type impurities are ion-implanted into the Si layer in the nMOS region, and p-type impurities are ion-implanted into the Si layer in the pMOS region. Thereby, the n-type extension layer 25n and the p-type extension layer 25p are formed.

  Next, as shown in FIG. 13B, sidewall insulating films 24 made of, for example, silicon nitride are formed on the sidewalls of the gate electrodes 22n and 22p with the insulating film 23 interposed therebetween. For example, a silicon nitride film is deposited on the semiconductor substrate 1 so as to cover the gate electrodes 22n and 22p by CVD, and then etched back by anisotropic etching, so that the sidewalls of the gate electrodes 22n and 22p are formed. A sidewall insulating film 24 is formed.

  Next, as shown in FIG. 14A, an n-type source / drain layer 26n is formed on the n-type extension layer 25n in the nMOS region, and a p-type source / drain layer is formed on the p-type extension layer 25p in the pMOS region. 26p is formed.

In this step, a Si layer is selectively epitaxially grown on the n-type source / drain layer 26n and the p-type source / drain layer 26p exposed from the sidewall insulating film 24 on both sides of the gate electrodes 22n and 22p. In the epitaxial growth, for example, Si ₂ H ₆ is flowed at 4 sccm as a gas, and the temperature is set to 600 ° C. Subsequently, n-type impurities are ion-implanted into the Si layer in the nMOS region, and p-type impurities are ion-implanted into the Si layer in the pMOS region. Thereby, the n-type source / drain layer 26n and the p-type source / drain layer 26p are formed. Thereafter, RTA (Rapid Thermal Annealing) is performed to activate the impurities implanted into the extension layer and the source / drain layers.

  Next, as shown in FIG. 14B, silicide layers 27 are formed on the gate electrodes 22n, 22p, the n-type source / drain layer 26n, and the p-type source / drain layer 26p. In this process, after depositing a metal film such as Ni or Co covering the gate electrodes 22n, 22p, the n-type source / drain layer 26n and the p-type source / drain layer 26p, the silicide layer 27 is formed by heat treatment, Thereafter, unnecessary metal film is removed.

  Next, as shown in FIG. 15, for example, a silicon oxide film is deposited by the CVD method to form an interlayer insulating film 30 that covers the entire surface of the nMOS region and the pMOS region.

  Next, as shown in FIG. 16, contact holes 30 a reaching the gate electrodes 22 n and 22 p, the n-type source / drain layer 26 n and the p-type source / drain layer 26 p are formed in the interlayer insulating film 30. The contact hole 30a is formed by etching the interlayer insulating film 30 using a resist.

  Next, a wiring layer 31 is formed on the interlayer insulating film 30 so as to fill the contact hole 30a (see FIG. 11). If necessary, a semiconductor device is completed through a multilayer wiring formation process.

  Also in the semiconductor device manufacturing method according to the present embodiment, the nMOS region has tensile strain in the channel direction due to tensile stress from the SiC layer 4 and the pMOS region has A substrate structure having a compressive strain in the channel direction is formed by the compressive stress from the SiGe layer 5.

  In the present embodiment, the SiC layer 4 and the SiGe layer 5 are formed so as to sandwich a region wider than the region where the gate electrode is formed. Therefore, even when the gate electrodes 22n and 22p are displaced, the gate electrodes 22n and 22p can be formed on the Si layer sandwiched between the SiC layer 4 or the SiGe layer 5. Since the channel under the gate electrodes 22n and 22p is formed only in the Si layer (p-type well 3p or n-type well 3n), carrier mobility can be improved.

  Furthermore, in the first embodiment, the source / drain regions 16n and 16p are formed in the SiC layer 4 and the SiGe layer 5, whereas in this embodiment, the source / drain layer 26n is formed on the SiC layer 4 and the SiGe layer 5. , 26p are formed. The effect by this is demonstrated.

  When the extension regions 15n and 15p and the source / drain regions 16n and 16p are also formed in the SiC layer 4 and the SiGe layer 5, the Si layer (wells 3p and 3n) and the SiC layer 4 and the SiGe layer 5 Since the impurity diffusion coefficients are different, the impurity profile may be shifted. When the gate electrodes 12n and 12p are shifted to the left and right, the impurity profiles of the extension regions 15n and 15p and the source / drain regions 16n and 16p are not symmetrical. For this reason, there is a possibility of affecting the transistor characteristics.

  In contrast, in this embodiment, the extension layers 25n and 25p and the source / drain layers 26n and 26p are formed on the SiC layer 4 and the SiGe layer 5, respectively. For this reason, there are no problems such as deviation of the impurity profile and asymmetry described above, and stable transistor characteristics can be obtained. However, also in this case, the gate electrodes 22n and 22p need to be formed on the Si layer (wells 3p and 3n), but there is no problem with this point as described above.

  As described above, a semiconductor device including a CMOS transistor having a tensile strain or a compressive strain mainly in the channel direction can be manufactured.

The present invention is not limited to the description of the above embodiment.
For example, the extension layers 25n and 25p and the source / drain layers 26n and 26p may be formed by selectively epitaxially growing an Si layer containing impurities in addition to forming the Si layer by selective epitaxial growth and then ion implantation. May be. In this case, the nMOS region and the pMOS region may be selectively epitaxially grown separately.
In addition, various modifications can be made without departing from the scope of the present invention.

1 is a cross-sectional view of a semiconductor device according to a first embodiment. It is process sectional drawing in manufacture of the semiconductor device which concerns on 1st Embodiment. It is process sectional drawing in manufacture of the semiconductor device which concerns on 1st Embodiment. It is process sectional drawing in manufacture of the semiconductor device which concerns on 1st Embodiment. It is process sectional drawing in manufacture of the semiconductor device which concerns on 1st Embodiment. It is process sectional drawing in manufacture of the semiconductor device which concerns on 1st Embodiment. It is process sectional drawing in manufacture of the semiconductor device which concerns on 1st Embodiment. It is process sectional drawing in manufacture of the semiconductor device which concerns on 1st Embodiment. It is process sectional drawing in manufacture of the semiconductor device which concerns on 1st Embodiment. It is process sectional drawing in manufacture of the semiconductor device which concerns on 1st Embodiment. It is sectional drawing of the semiconductor device which concerns on 2nd Embodiment. It is process sectional drawing in manufacture of the semiconductor device which concerns on 2nd Embodiment. It is process sectional drawing in manufacture of the semiconductor device which concerns on 2nd Embodiment. It is process sectional drawing in manufacture of the semiconductor device which concerns on 2nd Embodiment. It is process sectional drawing in manufacture of the semiconductor device which concerns on 2nd Embodiment. It is process sectional drawing in manufacture of the semiconductor device which concerns on 2nd Embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 1n ... groove | channel, 1p ... groove | channel, 2 ... Element isolation insulating film, 3n ... n-type well, 3p ... p-type well, 4 ... SiC layer, 5 ... SiGe layer, 11 ... Gate insulating film, 12n ... Gate electrode, 12p ... gate electrode, 14 ... sidewall insulating film, 15n ... n-type extension region, 15p ... p-type extension region, 16n ... n-type source / drain region, 16p ... p-type source / drain region, 17 ... silicide Layer, 21 ... gate insulating film, 22n ... gate electrode, 22p ... gate electrode, 23 ... insulating film, 24 ... side wall insulating film, 25n ... n-type extension layer, 25p ... p-type extension layer, 26n ... n-type source Drain layer, 26p ... p-type source / drain layer, 27 ... silicide layer, 28 ... mask layer, 30 ... interlayer insulating film, 30a ... contact Hall, 31 ... wiring layer, 41 ... mask layer, 42 ... mask layer

Claims (6)

Forming an element isolation insulating film for partitioning an active region on a semiconductor substrate;
Forming a groove sandwiching a region to be a channel in the semiconductor substrate in the active region;
A step of filling the trench with a semiconductor layer having a lattice spacing different from that of the semiconductor substrate by epitaxial growth;
Removing the semiconductor layer formed on the semiconductor substrate other than the groove in the groove embedding step until the semiconductor substrate is exposed;
Forming a gate electrode through a gate insulating film on the semiconductor substrate sandwiched between the semiconductor layers embedded in the trench. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of forming a source / drain region by introducing an impurity into the semiconductor substrate and the semiconductor layer on both sides of the gate electrode after the step of forming the gate electrode. Method. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of forming a source / drain layer by epitaxial growth on the semiconductor substrate and the semiconductor layer on both sides of the gate electrode after the step of forming the gate electrode. The method for manufacturing a semiconductor device according to claim 1, wherein in the step of forming the groove, the groove is formed so as to sandwich a region wider than a region where the gate electrode is formed. A method of manufacturing a semiconductor device, wherein a first transistor and a second transistor having different carriers are formed in a first region and a second region of a semiconductor substrate,
Forming an element isolation insulating film that partitions the first region and the second region of the semiconductor substrate as active regions;
Forming a first groove sandwiching a region to be a channel in the semiconductor substrate in the first region;
Filling the first trench with a first semiconductor layer having a lattice spacing different from that of the semiconductor substrate by epitaxial growth;
Removing the first semiconductor layer formed on the semiconductor substrate other than the first groove in the first groove embedding step until the semiconductor substrate is exposed;
Forming a second groove sandwiching a region to be a channel in the semiconductor substrate in the second region;
Filling the second groove with a second semiconductor layer having a lattice spacing different from that of the semiconductor substrate by epitaxial growth;
Removing the second semiconductor layer formed on the semiconductor substrate other than the second groove in the second groove embedding step until the semiconductor substrate is exposed;
Forming a gate electrode in each of the first region and the second region of the semiconductor substrate with a gate insulating film interposed therebetween. A semiconductor substrate;
A gate electrode formed on the semiconductor substrate via a gate insulating film;
Embedded in the semiconductor substrate so as to sandwich a channel formation region under the gate electrode, and a semiconductor layer of a material having a lattice spacing different from that of the semiconductor substrate;
A semiconductor device comprising: the semiconductor substrate on both sides of the gate electrode; and a source / drain layer stacked on the semiconductor layer.

Images