JP2006254039A - System decoder - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a system decoder capable of achieving reduction in cost by performing data processing in a TS (transport stream) packet unit. <P>SOLUTION: A TS-IF part 5 synchronizes TSs and writes data in a memory 1 of 188-byte ×2. Then, a scrambling part 6 decodes scrambled data and writes the result in a memory 2 of 188-byte ×2. A DEMUX part 7 uses a PID value and additional information (α part) to filter a TS packet. Packet data that hit the filtering are decoded as data of a section type or PES (packetized elementary stream) system format on the basis of a data type and the result is written in a memory 3 of 188-byte ×2. After that, data extracted, separated and written in the memory 3 are written and temporarily stored in an external storage device (SDRAM) 4. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a configuration of a system decoder applied to DTV-S or the like.

  An MPEG packet processing apparatus for processing a stream compressed by the MPEG method, a TS (Transport Stream) analysis unit of the stream, a PES (Packetized Elementary Stream) decoder for decoding the output of the TS analysis unit, and the PES decoder Patent Document 1 below discloses an MPEG packet processing apparatus characterized in that a storage means is provided in this part and a PES decoder is unified.

JP 2003-259366 A

  In the conventional MPEG packet processing apparatus disclosed in the above patent document, a dedicated storage means is provided for decoding the PES. Here, it is known that the data unit of PES is generally larger than that of TS packets. Therefore, if the storage means for PES decoding is mounted on an LSI, the manufacturing cost increases. On the other hand, when it goes out of the LSI, a dedicated access for the PES decoder is required. In this case, the bus band for external access often has no margin, which causes a bus failure. Further, since processing in TS packet units (188 byte units) cannot be performed, there is a problem that the memory capacity to be mounted on the LSI becomes large, such as temporarily storing memory capacity in PES units, leading to an increase in LSI cost. .

  The present invention has been made to solve such a problem, and an object of the present invention is to obtain a system decoder that can realize cost reduction by performing data processing in units of TS packets.

  A system decoder according to a first aspect of the present invention is connected to a synchronization acquisition unit that synchronously acquires TS (Transport Stream) data and a subsequent stage of the synchronization acquisition unit, and each memory has a storage capacity corresponding to a data unit of TS data. And a first storage unit including a memory set that alternately performs a write operation and a read operation of TS data input from the synchronization acquisition unit, and is connected to a subsequent stage of the first storage unit, A descrambling unit that performs descrambling processing on the TS data read from the storage unit, and a subsequent stage of the descrambling unit, each memory having a storage capacity corresponding to a data unit of TS data, and A second storage unit including a memory set that alternately performs a write operation and a read operation of TS data input from the scramble unit and a subsequent stage of the second storage unit are connected. Connected to an extraction / separation unit that extracts and separates necessary TS data from a plurality of TS data read from the second storage unit, and a subsequent stage of the extraction / separation unit, and each memory is a TS data A third storage unit having a storage capacity equivalent to a unit and including a memory set that alternately performs a write operation and a read operation of TS data input from the extraction / separation unit; and a subsequent stage of the third storage unit And a writing unit for writing TS data read from the third storage unit to an external memory. The system decoder has a four-stage pipeline structure in units of TS packets.

  A system decoder according to a second aspect of the present invention is connected to a synchronization acquisition unit that synchronously acquires TS (Transport Stream) data and a subsequent stage of the synchronization acquisition unit, and each memory has a storage capacity corresponding to a data unit of TS data. And a first storage unit including a memory set that alternately performs a write operation and a read operation of TS data input from the synchronization acquisition unit, and is connected to a subsequent stage of the first storage unit, An extraction / separation unit for extracting and separating necessary TS data from a plurality of TS data read from the storage unit, and a subsequent stage of the extraction / separation unit, each memory having a storage capacity corresponding to a data unit of TS data Including a memory set that alternately performs a write operation and a read operation of TS data input from the extraction / separation unit, and is connected to a subsequent stage of the second storage unit, A system decoder having a three-stage pipeline structure in units of TS packets, including a writing unit that writes TS data read from the second storage unit to an external memory.

  A system decoder according to a third aspect of the present invention is connected to a synchronization acquisition unit that synchronously acquires TS (Transport Stream) data and a subsequent stage of the synchronization acquisition unit, and each memory has a storage capacity corresponding to a data unit of TS data. And a first storage unit including a memory set that alternately performs a write operation and a read operation of TS data input from the synchronization acquisition unit, and is connected to a subsequent stage of the first storage unit, An extraction / separation unit that extracts and separates necessary TS data from a plurality of TS data read from the storage unit, and is connected to a subsequent stage of the extraction / separation unit, and the TS data input from the extraction / separation unit is stored in an external memory. A system decoder having a two-stage pipeline structure in units of TS packets, including a writing unit for writing.

  According to the system decoders of the first to third aspects, the cost can be reduced by performing data processing in units of TS packets.

  First, an outline of the present invention will be described.

  The system decoder according to the present invention is characterized by performing stream separation, extraction of designated data, and writing to an external memory in units of TS (Transport Stream) packets. A function to determine that the data is PES data and delete the header part of the PES is also installed, but only about 12 bytes of memory for temporarily storing the PES header part is installed for the number of PES filters. It has a configuration.

  By performing demultiplex processing (hereinafter referred to as “Demux processing”) in units of TS packets, the required work memory is only 188 bytes. From this 188-byte data, only the data designated for extraction / separation is written to the external memory. At this time, a process of converting data in PES units into data in ES (elementary stream) units is also performed. As a result, there is no need to accumulate data in units of PES, and the memory for temporarily storing data in units of PES and access to this memory can be deleted.

(1) System Decoder According to the First Invention FIG. 1 is a block diagram schematically showing the configuration of the system decoder 100a according to the first invention. Referring to FIG. 1, TS-IF unit 5 synchronizes TS and writes data to 188 bytes × 2 memories 1. Next, the descrambling unit 6 decodes (descrambles) the scrambled data, and writes the result into the memory 2 of 188 bytes. Next, the DEMUX unit 7 filters TS packets using the PID value and additional information (α portion). The packet data that hits this filter is decoded as data in the Section or PES format depending on the data type, and the result is written to the memory 3 of 188 bytes × 2. Here, in the case of PES data, decoding from PES to ES is also performed. Thereafter, the data extracted and separated and written to the memory 3 is written to the external storage device (SDRAM) 4 and temporarily held.

  FIG. 2 is a timing chart showing pipeline processing of the system decoder 100a. Referring to FIG. 2, system decoder 100a is characterized by performing a four-stage pipeline operation in units of TS packets. Details will be described in the first embodiment described later. The first stage is an IF stage for synchronizing streaming data of MPEG2-TS, the second stage is an S stage for descrambling, and the third stage is a Demux. The D stage that performs processing, and the fourth stage is the W stage that performs writing to the SDRAM 4.

  Here, the TS packet unit is a data unit of MPEG2-TS and is 188 bytes. The system decoder 100a synchronizes the 188-byte packet data, and the pipeline process is advanced each time the data is taken into the 188-byte two-plane memories 1 to 3.

  Since the pipeline operation is in units of TS packets, the pipeline operation varies depending on the input rate of data input to the system decoder 100a. In other words, the change in the time interval until all 188 bytes of data are received is directly reflected in the pipeline operation.

(2) System Decoder According to Second Invention FIG. 3 is a block diagram schematically showing the configuration of the system decoder 100b according to the second invention, and FIG. 4 is a timing showing pipeline processing of the system decoder 100b. It is a chart. For applications that do not require scrambling, the S stage can be deleted to provide a three-stage pipeline configuration. In this case, one set of the 188-byte two-plane memory 2 can be omitted. As shown in FIGS. 3 and 4, the pipeline is composed of three stages. The first stage is an IF stage that synchronizes MPEG2-TS streaming data, the second stage is a D stage that performs Demux processing, and the third stage is a W stage that performs writing to the SDRAM 4.

  By separating the D stage and the W stage, the number of clocks (required time) required for the Demux processing at the D stage and the required time required for writing to the SDRAM 4 at the W stage are separated. Yes. Since each stage has a period of 1 TS packet, a period of at least about 40 μsec is required. When the processing clock frequency of the system decoder 100b is 100 MHz, at least about 2000 clocks can be assigned to the Demux processing. In the Demux process according to the second invention, the multi-section process requires the most processing cycle, and the Demux process is completed in about 1000 clocks at the maximum, but there is still sufficient margin. Since the W stage is provided, the waiting time tolerance for the processing system including the external bus contention waiting time used in the write transaction to the SDRAM 4 is improved.

  Although FIG. 3 shows the case where only the system decoder 100b accesses the SDRAM 4, there are actually many other blocks that access the SDRAM 4, so the bus bandwidth accessible by the system decoder 100b is as follows. It will be very limited. The W stage is provided only for the writing period to the SDRAM 4 so that the write transaction to the SDRAM 4 does not fail even in this limited bus band.

(3) System Decoder According to Third Invention FIG. 5 is a block diagram schematically showing the configuration of the system decoder 100e according to the third invention, and FIG. 6 is a timing showing pipeline processing of the system decoder 100e. It is a chart. If only the system decoder 100e has access to the SDRAM 4, or if it is known that the write transaction issued from the system decoder 100e is processed with the highest priority, the W stage is also unnecessary. In this case, the data extracted and separated at the D stage can be directly written into the SDRAM 4 within the period of the D stage. On the other hand, since the number of clocks of about 1500 clocks is required for the Demux process, at least the IF stage and the D stage must be provided separately. Accordingly, the pipeline configuration in the system decoder 100e according to the third aspect of the invention is two stages as shown in FIG. The first stage is an IF stage for synchronizing MPEG2-TS streaming data, and the second stage is a D stage for performing Demux processing and writing to the SDRAM 4.

(4) Time stamp invalidation processing at the time of discontinuous PCR reception Normally, the system decoder is equipped with a clock for managing the decoding time. This clock is a clock whose time is updated based on time data called PCR (Program Clock Reference) embedded in MPEG2-TS. Time information called a time stamp (PTS / DTS) is added to the video ES and audio ES sent in MPEG2-TS, and if the time stamp value matches the clock of the system decoder, the video ES The audio ES is output from the system decoder.

  Here, this time stamp value corresponds to each frame data unit stored in the SDRAM 4. When a plurality of clocks (STC: System Time Clock) are handled at the same time, they are managed as a plurality of time stamps (time stamps corresponding and classified for each PCR_PID) on the time axis.

  When discontinuous PCR is received in this state, first, it is confirmed which PID-compatible PCR is discontinuous. Thereafter, the valid bit of the time stamp value of the video and audio corresponding to the discontinuous PCR among the stored video and audio time stamp values is cleared to 0.

  The AV synchronous ES output unit compares the time stamp value corresponding to the ES data to be output from the system decoder with the corresponding STC. At this time, if the valid bit of the time stamp value is set (value is 1), the ES output control is performed by comparing the STC with the time stamp value when performing ES output. On the other hand, if the valid bit of the time stamp value is cleared (value is 0), the ES output is performed without comparing the STC with the time stamp value when performing ES output.

  This time stamp value clear process avoids a situation where ES output from the system decoder stops (stops for several minutes) even after receiving discontinuous PCR (when the time is rewound for several minutes, etc.). .

Embodiment 1 FIG.
(1) Basic Configuration of System Decoder 100a FIG. 7 is a block diagram showing the configuration of the first half processing unit of the system decoder 100a according to Embodiment 1 of the present invention. As shown in FIG. 7, the first half processing unit of the system decoder 100a receives the MPEG2-TS input and synchronizes with the TS-IF unit 5 that synchronizes 188 bytes, and receives the output of the TS-IF unit 5 and decrypts the cipher. A descrambling unit 6, a DEMUX unit 7 that receives the output of the descrambling unit 6 and performs Demux processing, and a Media I / F unit 8 that writes data output from the DEMUX unit 7 to the SDRAM 4 are configured. The Media I / F unit 8 includes a writing unit 8a and a MediaBus I / F unit 8b.

  First, a pipeline configuration in units of TS packets in the system decoder 100a will be described, and then an architecture that enables Demux processing including the PES decoder will be described.

(2) Pipeline configuration of system decoder 100a As a pipeline operation in units of TS packets of the system decoder 100a, a two-sided memory 1 of 188 bytes on one side is arranged at the rear stage of the TS-IF unit 5 to configure an IF stage. ing.

  In the IF stage, the following processing is performed.

  MPEG2-TS data (TSDATA) sent together with the input clock (TSCLK) is captured by TSCLK. At this time, the data valid (TSVALID) sent simultaneously with TSDATA is referred to, and the data is taken in only when it is valid data. In addition, the capture unit can be selected in units of 1 byte or 1 bit.

  The “47” code which is the head data of the MPEG2-TS packet is searched, and it is confirmed that the “47” code exists every 188 bytes.

  In order to speed up the synchronization acquisition candidate processing, a plurality of counters that operate independently are mounted to handle a plurality of synchronization acquisition candidates. When the synchronization acquisition of any one of the synchronization acquisition candidates is established, the other synchronization acquisition candidates are canceled.

  When synchronization acquisition is established, data of the MPEG2-TS packet starts to be stored in the 188-byte memory 1 in order from the first “47” code.

  The 188-byte memory 1 has two surfaces, and the surface on which writing on all the surfaces has been completed is switched to a reading surface from the subsequent pipeline stage.

  A two-sided memory 2 of 188 bytes on one side is also arranged at the subsequent stage of the descramble unit 6 to constitute an S stage.

  In the S stage, the following processing is performed.

  The MPEG2-TS data is sequentially read from the side where writing has been completed in the two-sided memory 1 of 188 bytes provided after the IF stage.

  It is determined whether the packet is an MPEG2-TS packet having a descrambling designation PID.

  In the case of an MPEG2-TS packet having a PID for descrambling designation, a descrambling process is performed on the payload of the MPEG2-TS packet.

  By performing descrambling over a plurality of clocks in units of 1 byte, descrambling of 188 bytes of data is performed.

  The descrambled data starts to be stored in the 188-byte memory 2 from the first byte of MPEG2-TS.

  The 188-byte memory 2 has two surfaces, and the surface on which writing on all the surfaces has been completed is switched to a reading surface from the subsequent pipeline stage.

  In the case of MPEG2-TS data that is not subject to descrambling processing, the descrambling processing is not performed and the data is written into the 188-byte memory 2. For example, header information of a TS packet or an MPEG2-TS packet not specified by PID is written to the 188-byte memory 2 without performing the descrambling process.

  The data not subject to descrambling processing has the same latency as the data subject to descrambling processing. In other words, the time required for the MPEG2-TS data to pass through the descrambling unit 6 is the same required time regardless of whether or not the descrambling process is performed.

  Further, a single-sided 188-byte two-sided memory 3a to 3c is also provided at the subsequent stage of the DEMUX unit 7 to constitute a D-stage.

  In the D stage, the following processing is performed.

  The scrambled MPEG2-TS data is sequentially read from the 188-byte two-sided memory 2 provided at the subsequent stage of the descrambling stage from the side where the writing has been completed.

  Among the read MPEG2-TS packet data, the TS header portion and, if present, the control data of the adaptation area are sequentially set in the TS analysis register 7a1.

  This read address is used to identify which one of the 188 bytes of the MPEG2-TS packet is being read.

  The base of MPEG2-TS analysis and extraction / separation at the D stage refers to the read address from the 188-byte two-sided memory 2 and the value of the TS analysis register 7a1, and the data structure of the MPEG2-TS packet Analysis proceeds.

  At the stage where the read address from the two-plane memory 2 has advanced to the end of reading the PID, it is determined whether or not the PID has been designated for extraction and separation.

  In this PID determination, if it is a section system, a PES system, or a PES system, it is determined whether it is an independent PES system, an audio system, or a video system.

  The transport scramble control, adaptation field control, and continuity counter value are set in the TS analysis register 7a1.

  The continuity counter value and the adaptation field control value are checked to determine whether the packet is an MPEG2-TS packet having a payload to be discarded, whether there is an adaptation area, and whether there is a payload.

  Next, if there is an adaptation field, the data in the adaptation area is continuously set in the TS analysis register 7a1.

  The beginning of the adaptation area is the adaptation length, and this length is checked. If the value is not 0, the adaptation length value is set in the adaptation length counter, and down-counting is started. When the adaptation length is 0, it is determined that the next byte is a pointer field in the case of section data, and the first byte of the PES in the case of PES data.

  If the adaptation length is not 0, the next byte includes a PCR flag (identifier indicating whether the packet is an MPEG2-TS packet including PCR) or a discontinuity indicating whether the included PCR is a discontinuous PCR. The tee indicator is set in the TS analysis register 7a1.

  If the PCR flag indicates that there is a PCR, the PCR is extracted. At this time, whether or not to load the PCR value to the STC which is the clock of the system decoder 100a is controlled by the load control register value of the PCR.

  If the discontinuity indicator is set, it is determined that the PCR included in the MPEG2-TS packet is a discontinuous PCR. The load control of the discontinuous PCR to the STC is controlled by the PCR load control register value.

  The loading of the discontinuous PCR into the STC also means that the relationship with the time stamp values of the video ES and audio ES already stored in the SDRAM 4 becomes discontinuous, so that the AV frame data already stored is stored. The valid bit of the time stamp corresponding to (video ES / audio ES) is invalidated. Here, the Valid bit is used for identifying whether the time stamp value is valid or invalid. When it is valid, it is used as a time stamp value used for comparison with the STC when processing is performed to wait until the frame data is output from the system decoder 100a. If it is invalid, the process for waiting until the time to be output is not performed.

  When the adaptation field ends, the process branches depending on whether the PID filtering result is a section system or a PES system.

  When the unit start indicator of the TS header is set, it is determined that there is a 1-byte pointer field in front of the payload because the section head includes section start data. In the case of the PES system, it is determined that PES data is stored from the beginning of the payload.

  In the case of a section system, a section header part is set in the section analysis register 7a2.

  The first byte of the section is a table ID. Section filtering is performed after the section headers are aligned, but the MPEG2-TS packet may end with a table ID. In this case, filtering by PID and table ID is performed and it is confirmed whether or not the continuation flag is set. Sets a continuation flag for storing whether or not a section straddling has been received.

  Here, the continuation flag is provided in pairs for all the filters.

  The continuation flag is cleared when the unit start indicator in the TS header portion stored in the MPEG2-TS packet that hits the filter for which the continuation flag is set is 1. The section continued in the MPEG2-TS packet ends, and it is determined that a new section is stored, and the continuation flag is cleared.

  Here, when the MPEG2-TS packet ends in the middle of the section header portion, the next MPEG2-TS packet data is not necessarily the subsequent packet data, so the section analysis register 7a2 is a section filter as a register set. Installed for a few minutes.

  In the case of the PES system, the PES header portion is set in the PES analysis register 7a3.

  The head of the PES header is a fixed code “000001” of the packet start code prefix. The 8th byte from the beginning of the PES header is a PTSDTS flag (an identifier indicating whether or not a time stamp that is PTS or DTS is included). If the time stamp is included, extraction is scheduled to be performed.

  When the next byte is the PES header length and the value of the PES header length is not 0, a value is set in the PES header length down counter, and down counting is performed.

  At the time when the PES header length down-count is completed, the first byte of the ES data exists.

  In the extraction of ES data, the ES extraction is realized by performing the deletion process of the PES header part.

  When the MPEG2-TS packet ends in the middle of the PES header part, it is determined from the PES header length down counter value and the continuation flag which byte of the PES header part should be resumed. .

  Here, when the MPEG2-TS packet ends in the middle of the PES header part, the next MPEG2-TS packet data is not necessarily the subsequent packet data, so the PES header analysis register 7a3 is a register set. There are as many PES filters as PID setting.

  Whether the section system or the PES system is used, the 188-byte read address from the memory 2 indicates which byte of the MPEG2-TS packet is being processed, recognizes the end of the MPEG2-TS, and sets the continuation flag. Is determined.

  Thereafter, the writing from the Media I / F unit 8 to the SDRAM 4 becomes the SDRAM writing stage (W stage).

  In the W stage, the following processing is performed.

  Of the two-sided memories 3a to 3c of 188 bytes provided at the subsequent stage of the D stage, the data on the surface where writing has been completed is written into the SDRAM 4.

  The writing unit is a data unit extracted and separated from 188 bytes of the MPEG2-TS packet for all sections, PES, and ES. Here, some sections have 13 bytes, and the maximum number of write destinations (write destination areas in the SDRAM 4) in the W stage is 14. In the case of the PES system, the maximum number of write destinations (write destination areas in the SDRAM 4) in the W stage is one. This is because in the case of the PES system, a plurality of PES packets are not stored in one MPEG2-TS packet.

  If the writing to the SDRAM 4 is not completed within the period of the W stage, the bus error interrupt is generated because the 188-byte two-plane memories 3a to 3c fail.

  Pipeline operations in units of TS packets (in units of 188 bytes) are divided by the two-plane memories 1, 2, 3a to 3c existing in these stages. The above is the first half processing unit of the system decoder 100a. The four-stage pipeline operation of the first half processing unit of the system decoder 100a is as shown in FIG.

(3) Second Half Processing Unit of System Decoder 100a FIG. 8 is a block diagram showing the basic configuration of the second half processing unit of the system decoder 100a. In the latter half processing unit of the system decoder 100a, the data written in the SDRAM 4 is read out and output from the system decoder 100a with AV synchronization. Here, the processing after reading from the SDRAM 4 operates independently of the pipeline operation in units of TS packets.

(4) Demux Processing (4-1) Configuration of DEMUX Unit 7 Demux processing including mainly ES extraction processing from the PES decoder will be described below. Here, the operation of the D stage of the DEMUX unit 7 will be described. The D stage includes a PID filter operation unit 7b, a TS analysis unit 7a, a Section analysis unit 7a2, a PES analysis unit 7a3, and SRAM units 3a to 3c for temporarily storing separation results. FIG. 9 is a timing chart showing the operations of the D stage and the W stage.

(4-2) Processing of DEMUX Unit 7 TS packet data for one packet (from the 0th byte to the 187th byte) is read from the two-plane memory 2 connected to the subsequent stage of the descrambling unit 6. This read address identifies the number of data from the beginning of the TS packet. The TS packet is stored in a register 7a1 provided in the TS analysis unit 7a according to the read address value. The TS data to be stored in the TS analysis unit 7a holds data in the TS header part, a part of data corresponding to adaptation, and a pointer field in the case of a section.

  Here, when the information up to the PID is written in the register 7a1 of the TS analysis unit 7a, the classification of TS packet types (section, video, audio, or independent PES) is performed. Based on this result, it is possible to identify the section system or the PES system (video, audio, independent PES). Using this result, it is determined whether to use the register 7a2 of the section analysis unit or the register 7a3 of the PES analysis unit.

  In the case of the PES system, only the necessary portion (13 bytes from the beginning of the PES and including the PES header length) of the information corresponding to the PES header is stored in the register 7a3 of the PES analysis unit. Here, depending on the size of the adaptation, the PES header may be larger than the TS packet unit (188 bytes). Therefore, registers 7a3 corresponding to the number of filters for performing PES decoding are mounted, and each register 7a3 has a PES header write pointer that can grasp the written position. When straddling TS packets, this PES header write pointer is stopped. Here, when the down counter value of the PES header length does not end by the end of the TS packet, the TS packet is straddled by the PES header portion. On the other hand, when the PES header length down counter is completed before the TS packet is completed, the TS packet is straddled after the PES header part. At the end of the PES header length down counter, the PES header write pointer is cleared. In the case of continuous reception restart, the PES header information extraction can be restarted by referring to the filter hit determination by PID and the PES header write pointer managed for each PID. Since PES can be filtered only by PID, no continuation flag is required.

  In the case of a section system, only the necessary portion (for 6 bytes from the beginning of the section, depending on the section length) of the information corresponding to the section header is stored in the register 7a2 of the section analysis section. Here, depending on the size of the adaptation, the TS packet may end before the data corresponding to the section header section is stored in the register 7a2 of the section analysis section. For this reason, each section analysis unit has a section header write pointer and a continuation flag for each filter number so that the section analysis unit can grasp how much the section header has been written. By referring to the section header write pointer value and the continuation flag, the section header information extraction can be resumed even if the data of the subsequent section is received for a while after straddling the TS packet. .

  Next, processing when the TS packet unit is exceeded will be described.

  In the case of the section system, the determination as to whether the received section data is data that can be contained in the TS packet or not can be made as follows: The determination is made based on the determination and (b) whether or not the section length down-count is completed at the end of the TS packet (at the 188th byte) based on the section length information existing in the section header section. If it is determined that it is not contained in the TS packet, the continuation flag of the number hitting the filter is set and the section length down counter value is cleared.

  In addition, when the value of unit_start_indicator in the TS header information part of the TS packet that hits the same filter is 1, the continuation flag is cleared. Judge that stored. Here, the start position of the new section is indicated by pointer_field.

  In the case of the PES system, the determination as to whether the received PES data is data that fits in the TS packet or data that does not fit is performed only for the PES header part.

  In a state where the PES header write pointer (pointer indicating how far the PES header has been stored in the register 7a3 of the PES analysis unit. It is determined that the PES header has ended due to the end of the PES header length) has not ended. When the process ends (at the 188th byte), it is determined that the PES header has straddled the TS packet, and the continuation flag of the number hitting the filter is set. This continuation flag is used to identify which register set of a plurality of register sets provided in the PES analysis unit.

  The continuation flag possessed by the PES header analysis unit is cleared when the PES header unit is stored in the register 7a3 of the PES analysis unit.

  Since the PES data itself after the PES header part can be separated and identified only by the PID, the PES length information is not referred to. Instead, the beginning of the PES is identified by unit_start_indicator in the TS packet header portion, and separation and extraction are performed from the beginning of the PES data.

  A block diagram around the section analysis register 7a2 is shown in FIG. 10, and a block diagram around the PES analysis register 7a3 is shown in FIG. The operations from TS data analysis to section separation (leading section extraction) are as shown in the timing chart of FIG. From the analysis of TS data, the multi-section extraction / separation operation is as shown in the timing chart of FIG. From the analysis of the TS data, the operation when the TS packet (188 bytes) ends in the section header at the time of section separation and extraction is as shown in the timing chart of FIG. From the analysis of TS data, the operation when the TS packet (188 bytes) ends in the middle of a section during section separation and extraction is as shown in the timing chart of FIG. From the analysis of the TS data, the data extraction / separation operation before the data indicated by the pointer field is as shown in the timing chart of FIG. The operation when there is no pointer field when extracting a section is as shown in the timing chart of FIG. An example of MPEG2-TS including a section is shown in FIG. 18, and an example of a PES header part is shown in FIG.

  Hereinafter, SRAMs (two-plane memories) 3a to 3c for temporarily holding the extraction / separation results will be described.

  Necessary data is filtered from the TS packet which is a lump of 188 bytes, and data determined to be separated and extracted are stored in the SRAMs 3a to 3c. FIG. 7 shows a two-sided SRAM (188 byte memory × 2) 3a for a section / independent PES system, a two-sided SRAM (188 byte memory × 2) 3b for an audio system, and a video system. However, as described in the third embodiment to be described later, if there are essentially two 188-byte SRAMs, a configuration in which two-surface SRAM (188-byte memory × 2) 3c is provided is shown. It is enough.

  Next, the management unit 9 that temporarily stores data separated from the TS data into sections, audio ES, video ES, independent PES1, and independent PES2 in the SRAMs 3a to 3c provided in the D stage will be described.

  Information and functions handled by the management unit 9 are listed below.

-Filter number (SDRAM4 storage area identification number: managed by section when multi-section)
-Count the number of data writes to SRAM 3a-3c, and the total number of bytes temporarily stored in SRAM 3a-3c (multi-section, managed by section)
Information on whether or not the TS data includes the head data of PES / ES (in the case of the head of PES / ES, in order to store the address storing the head byte of PES / ES when SDRAM4 is stored together with PTS / DTS extraction) Will be used later)
Receives PTS / DTS information from the TS analyzer 7a.

  When transferring from the SRAMs 3a to 3c to the SDRAM 4, the PTS / DTS information and the frame number are managed with the address and the set storing the first byte of the PES / ES.

  Timing information notifying the timing at which data read from the SRAM 2 of the TS analysis input unit can be directly written to the SRAMs 3a to 3c of the DEMUX output unit is received from the section analysis unit 7a2 and the PES analysis unit 7a3.

  The TS data reading counter value of the SRAM 2 of the TS analysis input unit is received (the DEMUX output units SRAM 3a to 3c have two surfaces, but are used for managing the surface switching).

  Next, the operation of the two-plane memories 3a to 3c connected to the subsequent stage of the D stage will be described.

(A) Writing section header (identification information) data to SRAM 3a The data in the section header is stacked in a register 7a2 provided in the section analyzer. These data are written into the section / PES shared SRAM 3a during the period indicated by the lowest signal in the timing chart shown in FIG.

  At this time, the SRAM management unit 9 uses the determined filter number to identify the storage area in the SDRAM 4 and write pointers used for writing to the SDRAM 4 (32 sections are basically used for the section. One of these is used.In the case of the estimated hit operation, since writing to a plurality of areas is performed, there are cases where a plurality of write pointers are used).

(B) Writing of section body data to SRAM 3a As shown in the timing chart of FIG. 12, when data transfer from the DFF storing the header information of the section to the SRAM 3a is completed, the SRAM 2 of the TS analysis input section continues. The data read from is directly transferred to the SRAMs 3a to 3c of the DEMUX output unit.

(C) Writing to the SRAM 3a of the independent PES Only the TS header is deleted, whether the head of the PES or the middle of the PES is confirmed with the payload_unit_start_indicator, and writing to the SRAM 3a is performed from the head of the PES. Since there is a case where TS is crossed, as in the case of section TS crossing processing, if the continuation flag is set, it is stored in the SRAM 3a as PES intermediate data if the continuation flag is set. Will be written as data).

(D) Writing of audio PES to SRAM 3b Only the TS header is deleted, whether the head of the PES or the middle of the PES is confirmed by payload_unit_start_indicator, and writing from the head of the PES to the SRAM 3b is performed. Since there is a case where TS is crossed, as in the case of section crossing TS, if the continuation flag is set, it is stored in the SRAM 3b as PES intermediate data if the continuation flag is set. Will be written as data).

  If it is at the head of the PES, the corresponding PTS / DTS, the write destination address of the PES head byte, and the frame number are simultaneously held. As a storage destination of this data (PTS / DTS / address, frame number), an AV synchronization control SRAM 10 (see FIG. 8) is used.

(E) Writing to the SRAM 3c of the video ES The TS header and the PES header are deleted, whether the head of the ES or the middle of the ES is confirmed by using payload_unit_start_indicator, and writing to the SRAM 3c is performed from the head of the ES. Since there is a case where TS is crossed, as in the case of section crossing TS, if the continuation flag is set, if the continuation flag is set, it is stored in the SRAM 3c as data in the middle of ES (on SDRAM4, there is no continuous Will be written as data).

  If it is the head of the ES, the corresponding PTS / DTS, the write destination address of the ES head byte, and the frame number are simultaneously held. As a storage destination of this data (PTS / DTS / address, frame number), an AV synchronization control SRAM 10 (see FIG. 8) is used.

(5) Processing of W stage In the W stage, data is transferred and written to the SDRAM 4 from the 188-byte two-plane memories 3a to 3c in the final stage of the D stage. The W stage is also a stage of 1 TS packet period. The data written from the SRAMs 3a to 3c to the SDRAM 4 includes a section, an independent PES, an audio PES, and a video ES.

  In section writing, writing to a plurality of areas of the SDRAM 4 may occur. In the multi-section, a plurality of different sections may be stored in one TS packet, and in this case, the write area to the SDRAM 4 is different for each section.

  In the case of an independent PES, an audio PES, and a video ES, a situation in which the write area to the SDRAM 4 is different does not occur in the operation in units of 1 TS packet period.

  Information and functions handled in the write control to the SDRAM 4 (Store transaction issuance process) are listed below.

  Of the two DEMUX output SRAMs 3a to 3c, the surface on the SDRAM 4 transfer side is confirmed.

  A write write pointer to be used is specified using the stored filter number (SDRAM 4 storage area identification number: managed by section when multi-section).

  In the case of the head of PES / ES, the PTS / DTS extraction result is stored in the AV synchronization control SRAM 10a (see FIG. 8), and the address storing the head byte of the PES / ES is written in the AV synchronization control SRAM 10a. At this time, the address is written in the AV synchronization control SRAM 10b managed by the same address as the PTS / DTS. At this time, the DEMUX unit 7 uniquely assigns an identification number, which is a frame number, and performs identification from 0 to 63.

  The frame number has a meaning corresponding to the PES unit (ES unit). Here, it is interpreted that one frame corresponds to one PES packet data. In other words, one frame corresponds to 1 ES data.

  Management of audio PES and video ES stored in the SDRAM 4 using the frame number.

  There are 64 types of frame numbers for audio PES and 64 types for video ES, and a total of 128 types can be identified.

  The method for temporarily storing the frame number, PTS / DTS, and PES / ES head address is as shown in FIG.

  The total number of bytes of ES / PES / section data temporarily stored in the SRAMs 3a to 3c (the total number of bytes for each section in multi-section) is converted into a transaction. Here, it is assumed that a transaction within a range supported for DTV-S is used. For this reason, the Store transaction to be used is converted into a transaction using 8 bytes and byte enable. For a 1-byte transfer, an 8-byte transaction and a byte enable are used.

  -An 8-byte write operation issues a transaction in alignment (aligned) with an 8-byte boundary.

  In accordance with the operation of the two-surface memory 2 of the TS input portion, the surface of the DEMUX output two-surface memories 3a to 3c is switched in units of TS packets. The surface switching operation is performed at a speed of approximately 40 μsec (1 TS packet reception rate). The write operation to the SDRAM 4 needs to be completed in accordance with this 40 μsec unit (unit for switching the two-plane memories 3a to 3c). If the write operation is not completed within this period, continuous data cannot be guaranteed as the DEMUX operation, and a bus error interrupt is generated.

  The write start timing to the SDRAM 4 is the timing at which the transaction generation preparation is completed from the switching timing of the two-plane memories 3a to 3c (the TS counter timing of the read counter from the SRAM 2 of the TS input unit). (In other words, issue a Store transaction).

  The TS analysis input unit SRAM2 receives the TS data read counter value. The DEMUX output units SRAM 3a to 3c have two surfaces, and are used for this surface switching management.

  As described above, the ES data after the PES header portion is deleted from the PES data can be extracted and stored in the SDRAM 4, and the necessary data is read from the SDRAM 4 while performing time management, and the ES and the video decoder and audio decoder in the subsequent stage are read out. The system decoder 100a can be configured.

  According to the system decoder 100a according to the first embodiment, since a pipeline operation that completes processing in units of TS packets is possible, a large-scale memory dedicated to the PES decoder becomes unnecessary. Therefore, there is an effect that the chip manufacturing cost can be reduced as compared with the case where the PES decoding memory is configured on-chip or off-chip. Further, since a large-scale memory dedicated to the PES decoder is not necessary, access to this memory can be reduced. Therefore, it is possible to allocate the bandwidth of the external bus to other access. For example, it is possible to allocate an access band for the CPU to use the SDRAM 4 as a work memory. In addition, since the external memory access is reduced, the external access frequency can be lowered, the power consumption is reduced, and the number of external pins can be reduced, so that the chip manufacturing cost can be reduced.

Embodiment 2. FIG.
(1) Basic Configuration of System Decoder 100b FIG. 20 is a block diagram showing the configuration of the first half processing unit of the system decoder 100b according to Embodiment 2 of the present invention. As shown in FIG. 20, the first half processing unit of the system decoder 100b receives the MPEG2-TS input and performs the demux processing by receiving the TS-IF unit 5 that synchronizes 188 bytes and the output of the TS-IF unit 5. A DEMUX unit 7 and a Media I / F unit 8 that writes data output from the DEMUX unit 7 to the SDRAM 4 are configured. The Media I / F unit 8 includes a writing unit 8a and a MediaBus I / F unit 8b. That is, the system decoder 100b according to the second embodiment is obtained by omitting the descrambling unit 6 from the system decoder 100a according to the first embodiment shown in FIG.

  First, a pipeline configuration in units of TS packets in the system decoder 100b will be described, and then an architecture that enables Demux processing including the PES decoder will be described.

(2) Pipeline configuration of system decoder 100b As a pipeline operation in units of TS packets of the system decoder 100b, a two-sided memory 1 of 188 bytes on one side is arranged at the rear stage of the TS-IF unit 5 to configure an IF stage. ing.

  In the IF stage, the following processing is performed.

  MPEG2-TS data (TSDATA) sent together with the input clock (TSCLK) is captured by TSCLK. At this time, the data valid (TSVALID) sent simultaneously with TSDATA is referred to, and the data is taken in only when it is valid data. In addition, the capture unit can be selected in units of 1 byte or 1 bit.

  The “47” code which is the head data of the MPEG2-TS packet is searched, and it is confirmed that the “47” code exists every 188 bytes.

  In order to speed up the synchronization acquisition candidate processing, a plurality of counters that operate independently are mounted to handle a plurality of synchronization acquisition candidates. When the synchronization acquisition of any one of the synchronization acquisition candidates is established, the other synchronization acquisition candidates are canceled.

  When synchronization acquisition is established, data of the MPEG2-TS packet starts to be stored in the 188-byte memory 1 in order from the first “47” code.

  The 188-byte memory 1 has two surfaces, and the surface on which writing on all the surfaces has been completed is switched to a reading surface from the subsequent pipeline stage.

  Two-sided memories 3a to 3c each having 188 bytes on one side are also arranged at the subsequent stage of the DEMUX unit 7 to constitute the D stage.

  In the D stage, the following processing is performed.

  The MPEG2-TS data is sequentially read from the side where writing has been completed in the two-sided memory 1 of 188 bytes provided at the subsequent stage of the IF stage.

  Among the read MPEG2-TS packet data, the TS header portion and, if present, the control data of the adaptation area are sequentially set in the TS analysis register 7a1.

  This read address is used to identify which one of the 188 bytes of the MPEG2-TS packet is being read.

  The base of MPEG2-TS analysis and extraction / separation in the D stage refers to the read address from the 188-byte two-sided memory 1 and the value of the TS analysis register 7a1, and the data structure of the MPEG2-TS packet Analysis proceeds.

  At the stage where the read address from the two-plane memory 1 has advanced to the end of reading the PID, it is determined whether or not the PID has been designated for extraction and separation.

  In this PID determination, if it is a section system, a PES system, or a PES system, it is determined whether it is an independent PES system, an audio system, or a video system.

  The transport scramble control, adaptation field control, and continuity counter value are set in the TS analysis register 7a1.

  The continuity counter value and the adaptation field control value are checked to determine whether the packet is an MPEG2-TS packet having a payload to be discarded, whether there is an adaptation area, and whether there is a payload.

  Next, if there is an adaptation field, the data in the adaptation area is continuously set in the TS analysis register 7a1.

  The beginning of the adaptation area is the adaptation length, and this length is checked. If the value is not 0, the adaptation length value is set in the adaptation length counter, and down-counting is started. When the adaptation length is 0, it is determined that the next byte is a pointer field in the case of section data, and the first byte of the PES in the case of PES data.

  If the adaptation length is not 0, the next byte includes a PCR flag (identifier indicating whether the packet is an MPEG2-TS packet including PCR) or a discontinuity indicating whether the included PCR is a discontinuous PCR. The tee indicator is set in the TS analysis register 7a1.

  If the PCR flag indicates that there is a PCR, the PCR is extracted. At this time, whether or not to load the PCR value to the STC which is the clock of the system decoder 100b is controlled by the load control register value of the PCR.

  If the discontinuity indicator is set, it is determined that the PCR included in the MPEG2-TS packet is a discontinuous PCR. The load control of the discontinuous PCR to the STC is controlled by the PCR load control register value.

  The loading of the discontinuous PCR into the STC also means that the relationship with the time stamp values of the video ES and audio ES already stored in the SDRAM 4 becomes discontinuous, so that the AV frame data already stored is stored. The valid bit of the time stamp corresponding to (video ES / audio ES) is invalidated. Here, the Valid bit is used for identifying whether the time stamp value is valid or invalid. When it is valid, it is used as a time stamp value used for comparison with the STC when performing processing for waiting until the time when the frame data is to be output from the system decoder 100b. If it is invalid, the process for waiting until the time to be output is not performed.

  When the adaptation field ends, the process branches depending on whether the PID filtering result is a section system or a PES system.

  When the unit start indicator of the TS header is set, it is determined that there is a 1-byte pointer field in front of the payload because the section head includes section start data. In the case of the PES system, it is determined that PES data is stored from the beginning of the payload.

  In the case of a section system, a section header part is set in the section analysis register 7a2.

  The first byte of the section is a table ID. Section filtering is performed after the section headers are aligned, but the MPEG2-TS packet may end with a table ID. In this case, filtering by PID and table ID is performed and it is confirmed whether or not the continuation flag is set. Sets a continuation flag for storing whether or not a section straddling has been received.

  Here, the continuation flag is provided in pairs for all the filters.

  The continuation flag is cleared when the unit start indicator in the TS header portion stored in the MPEG2-TS packet that hits the filter for which the continuation flag is set is 1. The section continued in the MPEG2-TS packet ends, and it is determined that a new section is stored, and the continuation flag is cleared.

  Here, when the MPEG2-TS packet ends in the middle of the section header portion, the next MPEG2-TS packet data is not necessarily the subsequent packet data, so the section analysis register 7a2 is a section filter as a register set. Installed for a few minutes.

  In the case of the PES system, the PES header portion is set in the PES analysis register 7a3.

  The head of the PES header is a fixed code “000001” of the packet start code prefix. The 8th byte from the beginning of the PES header is a PTSDTS flag (an identifier indicating whether or not a time stamp that is PTS or DTS is included). If the time stamp is included, extraction is scheduled to be performed.

  When the next byte is the PES header length and the value of the PES header length is not 0, a value is set in the PES header length down counter, and down counting is performed.

  At the time when the PES header length down-count is completed, the first byte of the ES data exists.

  In the extraction of ES data, the ES extraction is realized by performing the deletion process of the PES header part.

  When the MPEG2-TS packet ends in the middle of the PES header part, it is determined from the PES header length down counter value and the continuation flag which byte of the PES header part should be resumed. .

  Here, when the MPEG2-TS packet ends in the middle of the PES header part, the next MPEG2-TS packet data is not necessarily the subsequent packet data, so the PES header analysis register 7a3 is a register set. There are as many PES filters as PID setting.

  Whether the section system or the PES system is used, the 188-byte read address from the memory 1 is used to recognize which byte of the MPEG2-TS packet is processed, the end of the MPEG2-TS, and whether the continuation flag is set. Is determined.

  Thereafter, the writing from the Media I / F unit 8 to the SDRAM 4 becomes the SDRAM writing stage (W stage).

  In the W stage, the following processing is performed.

  Of the two-sided memories 3a to 3c of 188 bytes provided at the subsequent stage of the D stage, the data on the surface where writing has been completed is written into the SDRAM 4.

  The writing unit is a data unit extracted and separated from 188 bytes of the MPEG2-TS packet for all sections, PES, and ES. Here, some sections have 13 bytes, and the maximum number of write destinations (write destination areas in the SDRAM 4) in the W stage is 14. In the case of the PES system, the maximum number of write destinations (write destination areas in the SDRAM 4) in the W stage is one. This is because in the case of the PES system, a plurality of PES packets are not stored in one MPEG2-TS packet.

  If the writing to the SDRAM 4 is not completed within the period of the W stage, the bus error interrupt is generated because the 188-byte two-plane memories 3a to 3c fail.

  Pipeline operations in units of TS packets (in units of 188 bytes) are delimited by the two-plane memories 1, 3a to 3c existing in these stages. The above is the first half processing unit of the system decoder 100b. The three-stage pipeline operation of the first half processing unit of the system decoder 100b is as shown in FIG.

(3) Second Half Processing Unit of System Decoder 100b FIG. 21 is a block diagram showing the basic configuration of the second half processing unit of the system decoder 100b. In the latter half processing unit of the system decoder 100b, the data written in the SDRAM 4 is read out and output from the system decoder 100b with AV synchronization. Here, the processing after reading from the SDRAM 4 operates independently of the pipeline operation in units of TS packets.

(4) Demux Processing (4-1) Configuration of DEMUX Unit 7 Demux processing including mainly ES extraction processing from the PES decoder will be described below. Here, the operation of the D stage of the DEMUX unit 7 will be described. The D stage includes a PID filter operation unit 7b, a TS analysis unit 7a, a Section analysis unit 7a2, a PES analysis unit 7a3, and SRAM units 3a to 3c for temporarily storing separation results. A timing chart showing the operations of the D stage and the W stage is as shown in FIG.

(4-2) Processing of DEMUX Unit 7 TS packet data for one packet (from the 0th byte to the 187th byte) is read from the two-plane memory 1 connected to the subsequent stage of the TS-IF unit 5. This read address identifies the number of data from the beginning of the TS packet. The TS packet is stored in a register 7a1 provided in the TS analysis unit 7a according to the read address value. The TS data to be stored in the TS analysis unit 7a holds data in the TS header part, a part of data corresponding to adaptation, and a pointer field in the case of a section.

  Here, when the information up to the PID is written in the register 7a1 of the TS analysis unit 7a, the classification of TS packet types (section, video, audio, or independent PES) is performed. Based on this result, it is possible to identify the section system or the PES system (video, audio, independent PES). Using this result, it is determined whether to use the register 7a2 of the section analysis unit or the register 7a3 of the PES analysis unit.

  In the case of the PES system, only the necessary portion (13 bytes from the beginning of the PES and including the PES header length) of the information corresponding to the PES header is stored in the register 7a3 of the PES analysis unit. Here, depending on the size of the adaptation, the PES header may be larger than the TS packet unit (188 bytes). Therefore, registers 7a3 corresponding to the number of filters for performing PES decoding are mounted, and each register 7a3 has a PES header write pointer that can grasp the written position. When straddling TS packets, this PES header write pointer is stopped. Here, when the down counter value of the PES header length does not end by the end of the TS packet, the TS packet is straddled by the PES header portion. On the other hand, when the PES header length down counter is completed before the TS packet is completed, the TS packet is straddled after the PES header part. At the end of the PES header length down counter, the PES header write pointer is cleared. In the case of continuous reception restart, the PES header information extraction can be restarted by referring to the filter hit determination by PID and the PES header write pointer managed for each PID. Since PES can be filtered only by PID, no continuation flag is required.

  In the case of a section system, only the necessary portion (for 6 bytes from the beginning of the section, depending on the section length) of the information corresponding to the section header is stored in the register 7a2 of the section analysis section. Here, depending on the size of the adaptation, the TS packet may end before the data corresponding to the section header section is stored in the register 7a2 of the section analysis section. For this reason, each section analysis unit has a section header write pointer and a continuation flag for each filter number so that the section analysis unit can grasp how much the section header has been written. By referring to the section header write pointer value and the continuation flag, the section header information extraction can be resumed even if the data of the subsequent section is received for a while after straddling the TS packet. .

  Next, processing when the TS packet unit is exceeded will be described.

  In the case of the section system, the determination as to whether the received section data is data that can be contained in the TS packet or not can be made as follows: The determination is made based on the determination and (b) whether or not the section length down-count is completed at the end of the TS packet (at the 188th byte) based on the section length information existing in the section header section. If it is determined that it is not contained in the TS packet, the continuation flag of the number hitting the filter is set and the section length down counter value is cleared.

  In addition, when the value of unit_start_indicator in the TS header information part of the TS packet that hits the same filter is 1, the continuation flag is cleared. Judge that stored. Here, the start position of the new section is indicated by pointer_field.

  In the case of the PES system, the determination as to whether the received PES data is data that fits in the TS packet or data that does not fit is performed only for the PES header part.

  In a state where the PES header write pointer (pointer indicating how far the PES header has been stored in the register 7a3 of the PES analysis unit. It is determined that the PES header has ended due to the end of the PES header length) has not ended. When the process ends (at the 188th byte), it is determined that the PES header has straddled the TS packet, and the continuation flag of the number hitting the filter is set. This continuation flag is used to identify which register set of a plurality of register sets provided in the PES analysis unit.

  The continuation flag possessed by the PES header analysis unit is cleared when the PES header unit is stored in the register 7a3 of the PES analysis unit.

  Since the PES data itself after the PES header part can be separated and identified only by the PID, the PES length information is not referred to. Instead, the beginning of the PES is identified by unit_start_indicator in the TS packet header portion, and separation and extraction are performed from the beginning of the PES data.

  Hereinafter, SRAMs (two-plane memories) 3a to 3c for temporarily holding the extraction / separation results will be described.

  Necessary data is filtered from the TS packet which is a lump of 188 bytes, and data determined to be separated and extracted are stored in the SRAMs 3a to 3c. FIG. 20 shows a two-sided SRAM (188 byte memory × 2) 3a for the section / independent PES system, a two-sided SRAM (188 byte memory × 2) 3b for the audio system, and a video system. However, as described in the third embodiment to be described later, if there are essentially two 188-byte SRAMs, a configuration is shown in which two-side SRAM (188-byte memory × 2) 3c is provided. It is enough.

(5) Processing of W stage In the W stage, data is transferred and written to the SDRAM 4 from the 188-byte two-plane memories 3a to 3c in the final stage of the D stage. The W stage is also a stage of 1 TS packet period. The data written from the SRAMs 3a to 3c to the SDRAM 4 includes a section, an independent PES, an audio PES, and a video ES.

  In section writing, writing to a plurality of areas of the SDRAM 4 may occur. In the multi-section, a plurality of different sections may be stored in one TS packet, and in this case, the write area to the SDRAM 4 is different for each section.

  In the case of an independent PES, an audio PES, and a video ES, a situation in which the write area to the SDRAM 4 is different does not occur in the operation in units of 1 TS packet period.

  As described above, the ES data after the PES header portion is deleted from the PES data can be extracted and stored in the SDRAM 4, and the necessary data is read from the SDRAM 4 while performing time management, and the ES and the video decoder and the audio decoder in the subsequent stage are read out. Can be configured.

  According to the system decoder 100b according to the second embodiment, since a pipeline operation that completes processing in units of TS packets is possible, a large-scale memory dedicated to the PES decoder is not necessary. Therefore, there is an effect that the chip manufacturing cost can be reduced as compared with the case where the PES decoding memory is configured on-chip or off-chip. Further, since a large-scale memory dedicated to the PES decoder is not necessary, access to this memory can be reduced. Therefore, it is possible to allocate the bandwidth of the external bus to other access. For example, it is possible to allocate an access band for the CPU to use the SDRAM 4 as a work memory. In addition, since the external memory access is reduced, the external access frequency can be lowered, the power consumption is reduced, and the number of external pins can be reduced, so that the chip manufacturing cost can be reduced.

  In addition, since the descrambling unit 6 and the two-plane memory 2 are omitted from the system decoder 100a according to the first embodiment shown in FIG. 7, the circuit scale can be reduced as compared with the system decoder 100a. .

Embodiment 3 FIG.
(1) Basic Configuration of System Decoder 100c FIG. 22 is a block diagram showing the configuration of the first half processing unit of the system decoder 100c according to Embodiment 3 of the present invention. As shown in FIG. 22, the first half processing unit of the system decoder 100c receives the MPEG2-TS input and synchronizes with the TS-IF unit 5 that synchronizes 188 bytes, and receives the output of the TS-IF unit 5 and decrypts the cipher. A descrambling unit 6, a DEMUX unit 7 that receives the output of the descrambling unit 6 and performs Demux processing, and a Media I / F unit 8 that writes data output from the DEMUX unit 7 to the SDRAM 4 are configured. The Media I / F unit 8 includes a writing unit 8a and a MediaBus I / F unit 8b.

  First, a pipeline configuration in units of TS packets in the system decoder 100c will be described, and then an architecture that enables Demux processing including the PES decoder will be described.

(2) Pipeline configuration of the system decoder 100c As a pipeline operation in units of TS packets of the system decoder 100c, a two-sided memory 1 of 188 bytes on one side is arranged at the rear stage of the TS-IF unit 5 to configure an IF stage. ing.

  In the IF stage, the following processing is performed.

  MPEG2-TS data (TSDATA) sent together with the input clock (TSCLK) is captured by TSCLK. At this time, the data valid (TSVALID) sent simultaneously with TSDATA is referred to, and the data is taken in only when it is valid data. In addition, the capture unit can be selected in units of 1 byte or 1 bit.

  The “47” code which is the head data of the MPEG2-TS packet is searched, and it is confirmed that the “47” code exists every 188 bytes.

  In order to speed up the synchronization acquisition candidate processing, a plurality of counters that operate independently are mounted to handle a plurality of synchronization acquisition candidates. When the synchronization acquisition of any one of the synchronization acquisition candidates is established, the other synchronization acquisition candidates are canceled.

  When synchronization acquisition is established, data of the MPEG2-TS packet starts to be stored in the 188-byte memory 1 in order from the first “47” code.

  The 188-byte memory 1 has two surfaces, and the surface on which writing on all the surfaces has been completed is switched to a reading surface from the subsequent pipeline stage.

  A two-sided memory 2 of 188 bytes on one side is also arranged at the subsequent stage of the descramble unit 6 to constitute an S stage.

  In the S stage, the following processing is performed.

  The MPEG2-TS data is sequentially read from the side where writing has been completed in the two-sided memory 1 of 188 bytes provided after the IF stage.

  It is determined whether the packet is an MPEG2-TS packet having a descrambling designation PID.

  In the case of an MPEG2-TS packet having a PID for descrambling designation, a descrambling process is performed on the payload of the MPEG2-TS packet.

  By performing descrambling over a plurality of clocks in units of 1 byte, descrambling of 188 bytes of data is performed.

  The descrambled data starts to be stored in the 188-byte memory 2 from the first byte of MPEG2-TS.

  The 188-byte memory 2 has two surfaces, and the surface on which writing on all the surfaces has been completed is switched to a reading surface from the subsequent pipeline stage.

  In the case of MPEG2-TS data that is not subject to descrambling processing, the descrambling processing is not performed and the data is written into the 188-byte memory 2. For example, header information of a TS packet or an MPEG2-TS packet not specified by PID is written to the 188-byte memory 2 without performing the descrambling process.

  The data not subject to descrambling processing has the same latency as the data subject to descrambling processing. In other words, the time required for the MPEG2-TS data to pass through the descrambling unit 6 is the same required time regardless of whether or not the descrambling process is performed.

  Further, a two-sided memory 3a having a single side of 188 bytes is provided at the subsequent stage of the DEMUX unit 7 to constitute a D stage.

  In the D stage, the following processing is performed.

  The scrambled MPEG2-TS data is sequentially read from the 188-byte two-sided memory 2 provided at the subsequent stage of the descrambling stage from the side where the writing has been completed.

  Among the read MPEG2-TS packet data, the TS header portion and, if present, the control data of the adaptation area are sequentially set in the TS analysis register 7a1.

  This read address is used to identify which one of the 188 bytes of the MPEG2-TS packet is being read.

  The base of MPEG2-TS analysis and extraction / separation at the D stage refers to the read address from the 188-byte two-sided memory 2 and the value of the TS analysis register 7a1, and the data structure of the MPEG2-TS packet Analysis proceeds.

  At the stage where the read address from the two-plane memory 2 has advanced to the end of reading the PID, it is determined whether or not the PID has been designated for extraction and separation.

  In this PID determination, if it is a section system, a PES system, or a PES system, it is determined whether it is an independent PES system, an audio system, or a video system.

  The transport scramble control, adaptation field control, and continuity counter value are set in the TS analysis register 7a1.

  The continuity counter value and the adaptation field control value are checked to determine whether the packet is an MPEG2-TS packet having a payload to be discarded, whether there is an adaptation area, and whether there is a payload.

  Next, if there is an adaptation field, the data in the adaptation area is continuously set in the TS analysis register 7a1.

  The beginning of the adaptation area is the adaptation length, and this length is checked. If the value is not 0, the adaptation length value is set in the adaptation length counter, and down-counting is started. When the adaptation length is 0, it is determined that the next byte is a pointer field in the case of section data, and the first byte of the PES in the case of PES data.

  If the adaptation length is not 0, the next byte includes a PCR flag (identifier indicating whether the packet is an MPEG2-TS packet including PCR) or a discontinuity indicating whether the included PCR is a discontinuous PCR. The tee indicator is set in the TS analysis register 7a1.

  If the PCR flag indicates that there is a PCR, the PCR is extracted. At this time, whether or not to load the PCR value to the STC which is the clock of the system decoder 100c is controlled by the PCR load control register value.

  If the discontinuity indicator is set, it is determined that the PCR included in the MPEG2-TS packet is a discontinuous PCR. The load control of the discontinuous PCR to the STC is controlled by the PCR load control register value.

  The loading of the discontinuous PCR into the STC also means that the relationship with the time stamp values of the video ES and audio ES already stored in the SDRAM 4 becomes discontinuous, so that the AV frame data already stored is stored. The valid bit of the time stamp corresponding to (video ES / audio ES) is invalidated. Here, the Valid bit is used for identifying whether the time stamp value is valid or invalid. When it is valid, it is used as a time stamp value used for comparison with the STC when performing processing for waiting until the time when the frame data is to be output from the system decoder 100c. If it is invalid, the process for waiting until the time to be output is not performed.

  When the adaptation field ends, the process branches depending on whether the PID filtering result is a section system or a PES system.

  When the unit start indicator of the TS header is set, it is determined that there is a 1-byte pointer field in front of the payload because the section head includes section start data. In the case of the PES system, it is determined that PES data is stored from the beginning of the payload.

  In the case of a section system, a section header part is set in the section analysis register 7a2.

  The first byte of the section is a table ID. Section filtering is performed after the section headers are aligned, but the MPEG2-TS packet may end with a table ID. In this case, filtering by PID and table ID is performed and it is confirmed whether or not the continuation flag is set. Sets a continuation flag for storing whether or not a section straddling has been received.

  Here, the continuation flag is provided in pairs for all the filters.

  The continuation flag is cleared when the unit start indicator in the TS header portion stored in the MPEG2-TS packet that hits the filter for which the continuation flag is set is 1. The section continued in the MPEG2-TS packet ends, and it is determined that a new section is stored, and the continuation flag is cleared.

  Here, when the MPEG2-TS packet ends in the middle of the section header portion, the next MPEG2-TS packet data is not necessarily the subsequent packet data, so the section analysis register 7a2 is a section filter as a register set. Installed for a few minutes.

  In the case of the PES system, the PES header portion is set in the PES analysis register 7a3.

  The head of the PES header is a fixed code “000001” of the packet start code prefix. The 8th byte from the beginning of the PES header is a PTSDTS flag (an identifier indicating whether or not a time stamp that is PTS or DTS is included). If the time stamp is included, extraction is scheduled to be performed.

  When the next byte is the PES header length and the value of the PES header length is not 0, a value is set in the PES header length down counter, and down counting is performed.

  At the time when the PES header length down-count is completed, the first byte of the ES data exists.

  In the extraction of ES data, the ES extraction is realized by performing the deletion process of the PES header part.

  When the MPEG2-TS packet ends in the middle of the PES header part, it is determined from the PES header length down counter value and the continuation flag which byte of the PES header part should be resumed. .

  Here, when the MPEG2-TS packet ends in the middle of the PES header part, the next MPEG2-TS packet data is not necessarily the subsequent packet data, so the PES header analysis register 7a3 is a register set. There are as many PES filters as PID setting.

  Whether the section system or the PES system is used, the 188-byte read address from the memory 2 indicates which byte of the MPEG2-TS packet is being processed, recognizes the end of the MPEG2-TS, and sets the continuation flag. Is determined.

  Thereafter, the writing from the Media I / F unit 8 to the SDRAM 4 becomes the SDRAM writing stage (W stage).

  In the W stage, the following processing is performed.

  Of the two-sided memory 3a of 188 bytes provided at the subsequent stage of the D stage, the data on the side where writing has been completed is written into the SDRAM 4.

  The writing unit is a data unit extracted and separated from 188 bytes of the MPEG2-TS packet for all sections, PES, and ES. Here, some sections have 13 bytes, and the maximum number of write destinations (write destination areas in the SDRAM 4) in the W stage is 14. In the case of the PES system, the maximum number of write destinations (write destination areas in the SDRAM 4) in the W stage is one. This is because in the case of the PES system, a plurality of PES packets are not stored in one MPEG2-TS packet.

  If writing to the SDRAM 4 is not completed within the period of the W stage, the 188-byte dual memory 3a fails, and a bus error interrupt is generated.

  Pipeline operations in units of TS packets (in units of 188 bytes) are divided by the two-plane memories 1, 2 and 3a existing in each stage. The above is the first half processing unit of the system decoder 100c. The four-stage pipeline operation of the first half processing unit of the system decoder 100c is as shown in FIG.

(3) Second Half Processing Unit of System Decoder 100c The basic configuration of the second half processing unit of the system decoder 100c is as shown in the block diagram of FIG. In the latter half processing section of the system decoder 100c, the data written in the SDRAM 4 is read out and output from the system decoder 100c with AV synchronization. Here, the processing after reading from the SDRAM 4 operates independently of the pipeline operation in units of TS packets.

(4) Demux Processing (4-1) Configuration of DEMUX Unit 7 Demux processing including mainly ES extraction processing from the PES decoder will be described below. Here, the operation of the D stage of the DEMUX unit 7 will be described. The D stage includes a PID filter operation unit 7b, a TS analysis unit 7a, a Section analysis unit 7a2, a PES analysis unit 7a3, and an SRAM unit 3a for temporarily storing a separation result. A timing chart showing the operations of the D stage and the W stage is as shown in FIG.

(4-2) Processing of DEMUX Unit 7 TS packet data for one packet (from the 0th byte to the 187th byte) is read from the two-plane memory 2 connected to the subsequent stage of the descrambling unit 6. This read address identifies the number of data from the beginning of the TS packet. The TS packet is stored in a register 7a1 provided in the TS analysis unit 7a according to the read address value. The TS data to be stored in the TS analysis unit 7a holds data in the TS header part, a part of data corresponding to adaptation, and a pointer field in the case of a section.

  Here, when the information up to the PID is written in the register 7a1 of the TS analysis unit 7a, the classification of TS packet types (section, video, audio, or independent PES) is performed. Based on this result, it is possible to identify the section system or the PES system (video, audio, independent PES). Using this result, it is determined whether to use the register 7a2 of the section analysis unit or the register 7a3 of the PES analysis unit.

  In the case of the PES system, only the necessary portion (13 bytes from the beginning of the PES and including the PES header length) of the information corresponding to the PES header is stored in the register 7a3 of the PES analysis unit. Here, depending on the size of the adaptation, the PES header may be larger than the TS packet unit (188 bytes). Therefore, registers 7a3 corresponding to the number of filters for performing PES decoding are mounted, and each register 7a3 has a PES header write pointer that can grasp the written position. When straddling TS packets, this PES header write pointer is stopped. Here, when the down counter value of the PES header length does not end by the end of the TS packet, the TS packet is straddled by the PES header portion. On the other hand, when the PES header length down counter is completed before the TS packet is completed, the TS packet is straddled after the PES header part. At the end of the PES header length down counter, the PES header write pointer is cleared. In the case of continuous reception restart, the PES header information extraction can be restarted by referring to the filter hit determination by PID and the PES header write pointer managed for each PID. Since PES can be filtered only by PID, no continuation flag is required.

  In the case of a section system, only the necessary portion (for 6 bytes from the beginning of the section, depending on the section length) of the information corresponding to the section header is stored in the register 7a2 of the section analysis section. Here, depending on the size of the adaptation, the TS packet may end before the data corresponding to the section header section is stored in the register 7a2 of the section analysis section. For this reason, each section analysis unit has a section header write pointer and a continuation flag for each filter number so that the section analysis unit can grasp how much the section header has been written. By referring to the section header write pointer value and the continuation flag, the section header information extraction can be resumed even if the data of the subsequent section is received for a while after straddling the TS packet. .

  Next, processing when the TS packet unit is exceeded will be described.

  In the case of the section system, the determination as to whether the received section data is data that can be contained in the TS packet or not can be made as follows: The determination is made based on the determination and (b) whether or not the section length down-count is completed at the end of the TS packet (at the 188th byte) based on the section length information existing in the section header section. If it is determined that it is not contained in the TS packet, the continuation flag of the number hitting the filter is set and the section length down counter value is cleared.

  In addition, when the value of unit_start_indicator in the TS header information part of the TS packet that hits the same filter is 1, the continuation flag is cleared. Judge that stored. Here, the start position of the new section is indicated by pointer_field.

  In the case of the PES system, the determination as to whether the received PES data is data that fits in the TS packet or data that does not fit is performed only for the PES header part.

  In a state where the PES header write pointer (pointer indicating how far the PES header has been stored in the register 7a3 of the PES analysis unit. It is determined that the PES header has ended due to the end of the PES header length) has not ended. When the process ends (at the 188th byte), it is determined that the PES header has straddled the TS packet, and the continuation flag of the number hitting the filter is set. This continuation flag is used to identify which register set of a plurality of register sets provided in the PES analysis unit.

  The continuation flag possessed by the PES header analysis unit is cleared when the PES header unit is stored in the register 7a3 of the PES analysis unit.

  Since the PES data itself after the PES header part can be separated and identified only by the PID, the PES length information is not referred to. Instead, the beginning of the PES is identified by unit_start_indicator in the TS packet header portion, and separation and extraction are performed from the beginning of the PES data.

  A block diagram around the section analysis register 7a2 is shown in FIG. 10, and a block diagram around the PES analysis register 7a3 is shown in FIG. The operations from TS data analysis to section separation (leading section extraction) are as shown in the timing chart of FIG. From the analysis of TS data, the multi-section extraction / separation operation is as shown in the timing chart of FIG. From the analysis of TS data, when a section is separated and extracted, the operation when the TS packet (188 bytes) ends in the section header is as shown in the timing chart of FIG. From the analysis of TS data, the operation when the TS packet (188 bytes) ends in the middle of a section during section separation and extraction is as shown in the timing chart of FIG. From the analysis of the TS data, the data extraction / separation operation before the data indicated by the pointer field is as shown in the timing chart of FIG. The operation when there is no pointer field when extracting a section is as shown in the timing chart of FIG. An example of MPEG2-TS including a section is shown in FIG. 18, and an example of a PES header part is shown in FIG.

  Hereinafter, the SRAM (two-sided memory) 3a for temporarily holding the extraction / separation result will be described.

  Necessary data is filtered from the TS packet which is a lump of 188 bytes, and the data determined to be separated and extracted is stored in the SRAM 3a. In the system decoder 100c according to the third embodiment, as shown in FIG. 22, a two-plane SRAM (188-byte memory × 2 pieces) 3a common to the section / independent PES system, the audio system, and the video system is provided. It has been.

(5) W Stage Processing In the W stage, data is transferred and written from the 188-byte two-plane memory 3a in the final stage of the D stage to the SDRAM 4. The W stage is also a stage of 1 TS packet period. The data written from the SRAM 3a to the SDRAM 4 includes a section, an independent PES, an audio PES, and a video ES.

  In section writing, writing to a plurality of areas of the SDRAM 4 may occur. In the multi-section, a plurality of different sections may be stored in one TS packet, and in this case, the write area to the SDRAM 4 is different for each section.

  In the case of an independent PES, an audio PES, and a video ES, a situation in which the write area to the SDRAM 4 is different does not occur in the operation in units of 1 TS packet period.

  As described above, the ES data after the PES header portion is deleted from the PES data can be extracted and stored in the SDRAM 4, and necessary data is read from the SDRAM 4 while performing time management, and the ES or video decoder in the subsequent stage is read out. Can be configured.

  According to the system decoder 100c according to the third embodiment, since a pipeline operation that completes processing in units of TS packets is possible, a large-scale memory dedicated to the PES decoder is not necessary. Therefore, there is an effect that the chip manufacturing cost can be reduced as compared with the case where the PES decoding memory is configured on-chip or off-chip. Further, since a large-scale memory dedicated to the PES decoder is not necessary, access to this memory can be reduced. Therefore, it is possible to allocate the bandwidth of the external bus to other access. For example, it is possible to allocate an access band for the CPU to use the SDRAM 4 as a work memory. In addition, since the external memory access is reduced, the external access frequency can be lowered, the power consumption is reduced, and the number of external pins can be reduced, so that the chip manufacturing cost can be reduced.

  Moreover, since the two-plane memories 3b and 3c are omitted from the system decoder 100a according to the first embodiment shown in FIG. 7, the circuit scale can be reduced as compared with the system decoder 100a.

Embodiment 4 FIG.
(1) Basic Configuration of System Decoder 100d FIG. 23 is a block diagram showing the configuration of the first half processing unit of the system decoder 100d according to Embodiment 4 of the present invention. As shown in FIG. 23, the first half processing unit of the system decoder 100d receives the MPEG2-TS input and performs the demux processing by receiving the TS-IF unit 5 that synchronizes 188 bytes and the output of the TS-IF unit 5. A DEMUX unit 7 and a Media I / F unit 8 that writes data output from the DEMUX unit 7 to the SDRAM 4 are configured. The Media I / F unit 8 includes a writing unit 8a and a MediaBus I / F unit 8b. That is, the system decoder 100d according to the fourth embodiment is obtained by omitting the descrambling unit 6 from the system decoder 100c according to the third embodiment shown in FIG.

  First, a pipeline configuration in units of TS packets in the system decoder 100d will be described, and then an architecture that enables Demux processing including the PES decoder will be described.

(2) Pipeline configuration of system decoder 100d As a pipeline operation in units of TS packets of the system decoder 100d, a two-sided memory 1 of 188 bytes on one side is arranged at the rear stage of the TS-IF unit 5 to configure an IF stage. ing.

  In the IF stage, the following processing is performed.

  MPEG2-TS data (TSDATA) sent together with the input clock (TSCLK) is captured by TSCLK. At this time, the data valid (TSVALID) sent simultaneously with TSDATA is referred to, and the data is taken in only when it is valid data. In addition, the capture unit can be selected in units of 1 byte or 1 bit.

  The “47” code which is the head data of the MPEG2-TS packet is searched, and it is confirmed that the “47” code exists every 188 bytes.

  In order to speed up the synchronization acquisition candidate processing, a plurality of counters that operate independently are mounted to handle a plurality of synchronization acquisition candidates. When the synchronization acquisition of any one of the synchronization acquisition candidates is established, the other synchronization acquisition candidates are canceled.

  When synchronization acquisition is established, data of the MPEG2-TS packet starts to be stored in the 188-byte memory 1 in order from the first “47” code.

  The 188-byte memory 1 has two surfaces, and the surface on which writing on all the surfaces has been completed is switched to a reading surface from the subsequent pipeline stage.

  A two-sided memory 3a having one side of 188 bytes is also arranged after the DEMUX unit 7 to constitute a D stage.

  In the D stage, the following processing is performed.

  The MPEG2-TS data is sequentially read from the side where writing has been completed in the two-sided memory 1 of 188 bytes provided at the subsequent stage of the IF stage.

  Among the read MPEG2-TS packet data, the TS header portion and, if present, the control data of the adaptation area are sequentially set in the TS analysis register 7a1.

  This read address is used to identify which one of the 188 bytes of the MPEG2-TS packet is being read.

  The base of MPEG2-TS analysis and extraction / separation in the D stage refers to the read address from the 188-byte two-sided memory 1 and the value of the TS analysis register 7a1, and the data structure of the MPEG2-TS packet Analysis proceeds.

  At the stage where the read address from the two-plane memory 1 has advanced to the end of reading the PID, it is determined whether or not the PID has been designated for extraction and separation.

  In this PID determination, if it is a section system, a PES system, or a PES system, it is determined whether it is an independent PES system, an audio system, or a video system.

  The transport scramble control, adaptation field control, and continuity counter value are set in the TS analysis register 7a1.

  The continuity counter value and the adaptation field control value are checked to determine whether the packet is an MPEG2-TS packet having a payload to be discarded, whether there is an adaptation area, and whether there is a payload.

  Next, if there is an adaptation field, the data in the adaptation area is continuously set in the TS analysis register 7a1.

  The beginning of the adaptation area is the adaptation length, and this length is checked. If the value is not 0, the adaptation length value is set in the adaptation length counter, and down-counting is started. When the adaptation length is 0, it is determined that the next byte is a pointer field in the case of section data, and the first byte of the PES in the case of PES data.

  If the adaptation length is not 0, the next byte includes a PCR flag (identifier indicating whether the packet is an MPEG2-TS packet including PCR) or a discontinuity indicating whether the included PCR is a discontinuous PCR. The tee indicator is set in the TS analysis register 7a1.

  If the PCR flag indicates that there is a PCR, the PCR is extracted. At this time, whether or not to load the PCR value to the STC which is the clock of the system decoder 100d is controlled by the PCR load control register value.

  If the discontinuity indicator is set, it is determined that the PCR included in the MPEG2-TS packet is a discontinuous PCR. The load control of the discontinuous PCR to the STC is controlled by the PCR load control register value.

  The loading of the discontinuous PCR into the STC also means that the relationship with the time stamp values of the video ES and audio ES already stored in the SDRAM 4 becomes discontinuous, so that the AV frame data already stored is stored. The valid bit of the time stamp corresponding to (video ES / audio ES) is invalidated. Here, the Valid bit is used for identifying whether the time stamp value is valid or invalid. When it is valid, it is used as a time stamp value used for comparison with the STC when processing for waiting until the time when the frame data is to be output from the system decoder 100d is performed. If it is invalid, the process for waiting until the time to be output is not performed.

  When the adaptation field ends, the process branches depending on whether the PID filtering result is a section system or a PES system.

  When the unit start indicator of the TS header is set, it is determined that there is a 1-byte pointer field in front of the payload because the section head includes section start data. In the case of the PES system, it is determined that PES data is stored from the beginning of the payload.

  In the case of a section system, a section header part is set in the section analysis register 7a2.

  The first byte of the section is a table ID. Section filtering is performed after the section headers are aligned, but the MPEG2-TS packet may end with a table ID. In this case, filtering by PID and table ID is performed and it is confirmed whether or not the continuation flag is set. Sets a continuation flag for storing whether or not a section straddling has been received.

  Here, the continuation flag is provided in pairs for all the filters.

  The continuation flag is cleared when the unit start indicator in the TS header portion stored in the MPEG2-TS packet that hits the filter for which the continuation flag is set is 1. The section continued in the MPEG2-TS packet ends, and it is determined that a new section is stored, and the continuation flag is cleared.

  Here, when the MPEG2-TS packet ends in the middle of the section header portion, the next MPEG2-TS packet data is not necessarily the subsequent packet data, so the section analysis register 7a2 is a section filter as a register set. Installed for a few minutes.

  In the case of the PES system, the PES header portion is set in the PES analysis register 7a3.

  The head of the PES header is a fixed code “000001” of the packet start code prefix. The 8th byte from the beginning of the PES header is a PTSDTS flag (an identifier indicating whether or not a time stamp that is PTS or DTS is included). If the time stamp is included, extraction is scheduled to be performed.

  When the next byte is the PES header length and the value of the PES header length is not 0, a value is set in the PES header length down counter, and down counting is performed.

  At the time when the PES header length down-count is completed, the first byte of the ES data exists.

  In the extraction of ES data, the ES extraction is realized by performing the deletion process of the PES header part.

  When the MPEG2-TS packet ends in the middle of the PES header part, it is determined from the PES header length down counter value and the continuation flag which byte of the PES header part should be resumed. .

  Here, when the MPEG2-TS packet ends in the middle of the PES header part, the next MPEG2-TS packet data is not necessarily the subsequent packet data, so the PES header analysis register 7a3 is a register set. There are as many PES filters as PID setting.

  Whether the section system or the PES system is used, the 188-byte read address from the memory 1 is used to recognize which byte of the MPEG2-TS packet is processed, the end of the MPEG2-TS, and whether the continuation flag is set. Is determined.

  Thereafter, the writing from the Media I / F unit 8 to the SDRAM 4 becomes the SDRAM writing stage (W stage).

  In the W stage, the following processing is performed.

  Of the two-sided memory 3a of 188 bytes provided at the subsequent stage of the D stage, the data on the side where writing has been completed is written into the SDRAM 4.

  The writing unit is a data unit extracted and separated from 188 bytes of the MPEG2-TS packet for all sections, PES, and ES. Here, some sections have 13 bytes, and the maximum number of write destinations (write destination areas in the SDRAM 4) in the W stage is 14. In the case of the PES system, the maximum number of write destinations (write destination areas in the SDRAM 4) in the W stage is one. This is because in the case of the PES system, a plurality of PES packets are not stored in one MPEG2-TS packet.

  If writing to the SDRAM 4 is not completed within the period of the W stage, the 188-byte dual memory 3a fails, and a bus error interrupt is generated.

  Pipeline operations in units of TS packets (in units of 188 bytes) are delimited by the two-plane memories 1 and 3a existing in each stage. The above is the first half processing unit of the system decoder 100d. The three-stage pipeline operation of the first half processing unit of the system decoder 100d is as shown in FIG.

(3) Second Half Processing Unit of System Decoder 100d The basic configuration of the second half processing unit of the system decoder 100d is as shown in the block diagram of FIG. In the latter half processing section of the system decoder 100d, the data written in the SDRAM 4 is read out and outputted from the system decoder 100d with AV synchronization. Here, the processing after reading from the SDRAM 4 operates independently of the pipeline operation in units of TS packets.

(4) Demux Processing (4-1) Configuration of DEMUX Unit 7 Demux processing including mainly ES extraction processing from the PES decoder will be described below. Here, the operation of the D stage of the DEMUX unit 7 will be described. The D stage includes a PID filter operation unit 7b, a TS analysis unit 7a, a Section analysis unit 7a2, a PES analysis unit 7a3, and an SRAM unit 3a for temporarily storing a separation result. A timing chart showing the operations of the D stage and the W stage is as shown in FIG.

(4-2) Processing of DEMUX Unit 7 TS packet data for one packet (from the 0th byte to the 187th byte) is read from the two-plane memory 1 connected to the subsequent stage of the TS-IF unit 5. This read address identifies the number of data from the beginning of the TS packet. The TS packet is stored in a register 7a1 provided in the TS analysis unit 7a according to the read address value. The TS data to be stored in the TS analysis unit 7a holds data in the TS header part, a part of data corresponding to adaptation, and a pointer field in the case of a section.

  Here, when the information up to the PID is written in the register 7a1 of the TS analysis unit 7a, the classification of TS packet types (section, video, audio, or independent PES) is performed. Based on this result, it is possible to identify the section system or the PES system (video, audio, independent PES). Using this result, it is determined whether to use the register 7a2 of the section analysis unit or the register 7a3 of the PES analysis unit.

  In the case of the PES system, only the necessary portion (13 bytes from the beginning of the PES and including the PES header length) of the information corresponding to the PES header is stored in the register 7a3 of the PES analysis unit. Here, depending on the size of the adaptation, the PES header may be larger than the TS packet unit (188 bytes). Therefore, registers 7a3 corresponding to the number of filters for performing PES decoding are mounted, and each register 7a3 has a PES header write pointer that can grasp the written position. When straddling TS packets, this PES header write pointer is stopped. Here, when the down counter value of the PES header length does not end by the end of the TS packet, the TS packet is straddled by the PES header portion. On the other hand, when the PES header length down counter is completed before the TS packet is completed, the TS packet is straddled after the PES header part. At the end of the PES header length down counter, the PES header write pointer is cleared. In the case of continuous reception restart, the PES header information extraction can be restarted by referring to the filter hit determination by PID and the PES header write pointer managed for each PID. Since PES can be filtered only by PID, no continuation flag is required.

  In the case of a section system, only the necessary portion (for 6 bytes from the beginning of the section, depending on the section length) of the information corresponding to the section header is stored in the register 7a2 of the section analysis section. Here, depending on the size of the adaptation, the TS packet may end before the data corresponding to the section header section is stored in the register 7a2 of the section analysis section. For this reason, each section analysis unit has a section header write pointer and a continuation flag for each filter number so that the section analysis unit can grasp how much the section header has been written. By referring to the section header write pointer value and the continuation flag, the section header information extraction can be resumed even if the data of the subsequent section is received for a while after straddling the TS packet. .

  Next, processing when the TS packet unit is exceeded will be described.

  In the case of the section system, the determination as to whether the received section data is data that can be contained in the TS packet or not can be made as follows: The determination is made based on the determination and (b) whether or not the section length down-count is completed at the end of the TS packet (at the 188th byte) based on the section length information existing in the section header section. If it is determined that it is not contained in the TS packet, the continuation flag of the number hitting the filter is set and the section length down counter value is cleared.

  In addition, when the value of unit_start_indicator in the TS header information part of the TS packet that hits the same filter is 1, the continuation flag is cleared. Judge that stored. Here, the start position of the new section is indicated by pointer_field.

  In the case of the PES system, the determination as to whether the received PES data is data that fits in the TS packet or data that does not fit is performed only for the PES header part.

  In a state where the PES header write pointer (pointer indicating how far the PES header has been stored in the register 7a3 of the PES analysis unit. It is determined that the PES header has ended due to the end of the PES header length) has not ended. When the process ends (at the 188th byte), it is determined that the PES header has straddled the TS packet, and the continuation flag of the number hitting the filter is set. This continuation flag is used to identify which register set of a plurality of register sets provided in the PES analysis unit.

  The continuation flag possessed by the PES header analysis unit is cleared when the PES header unit is stored in the register 7a3 of the PES analysis unit.

  Since the PES data itself after the PES header part can be separated and identified only by the PID, the PES length information is not referred to. Instead, the beginning of the PES is identified by unit_start_indicator in the TS packet header portion, and separation and extraction are performed from the beginning of the PES data.

  Hereinafter, the SRAM (two-sided memory) 3a for temporarily holding the extraction / separation result will be described.

  Necessary data is filtered from the TS packet which is a lump of 188 bytes, and the data determined to be separated and extracted is stored in the SRAM 3a. In the system decoder 100d according to the fourth embodiment, as shown in FIG. 23, a two-plane SRAM (188-byte memory × 2 pieces) 3a common to the section / independent PES system, the audio system, and the video system is provided. It has been.

(5) W Stage Processing In the W stage, data is transferred and written from the 188-byte two-plane memory 3a in the final stage of the D stage to the SDRAM 4. The W stage is also a stage of 1 TS packet period. The data written from the SRAM 3a to the SDRAM 4 includes a section, an independent PES, an audio PES, and a video ES.

  In section writing, writing to a plurality of areas of the SDRAM 4 may occur. In the multi-section, a plurality of different sections may be stored in one TS packet, and in this case, the write area to the SDRAM 4 is different for each section.

  In the case of an independent PES, an audio PES, and a video ES, a situation in which the write area to the SDRAM 4 is different does not occur in the operation in units of 1 TS packet period.

  As described above, the ES data after the PES header portion is deleted from the PES data can be extracted and stored in the SDRAM 4, and the necessary data is read from the SDRAM 4 while performing time management, and the ES and the video decoder and the audio decoder in the subsequent stage are read out. Can be configured.

  According to the system decoder 100d according to the fourth embodiment, since a pipeline operation that completes processing in units of TS packets is possible, a large-scale memory dedicated to the PES decoder is not necessary. Therefore, there is an effect that the chip manufacturing cost can be reduced as compared with the case where the PES decoding memory is configured on-chip or off-chip. Further, since a large-scale memory dedicated to the PES decoder is not necessary, access to this memory can be reduced. Therefore, it is possible to allocate the bandwidth of the external bus to other access. For example, it is possible to allocate an access band for the CPU to use the SDRAM 4 as a work memory. In addition, since the external memory access is reduced, the external access frequency can be lowered, the power consumption is reduced, and the number of external pins can be reduced, so that the chip manufacturing cost can be reduced.

  In addition, since the descrambling unit 6 and the two-plane memory 2 are omitted from the system decoder 100c according to the third embodiment shown in FIG. 22, the circuit scale can be reduced as compared with the system decoder 100c. .

Embodiment 5. FIG.
(1) Basic Configuration of System Decoder 100e FIG. 24 is a block diagram showing the configuration of the first half processing unit of the system decoder 100e according to Embodiment 5 of the present invention. As shown in FIG. 24, the first half processing unit of the system decoder 100e receives the MPEG2-TS input and performs the demux processing by receiving the TS-IF unit 5 that synchronizes 188 bytes and the output of the TS-IF unit 5. A DEMUX unit 7 and a Media I / F unit 8 that writes data output from the DEMUX unit 7 to the SDRAM 4 are configured. The Media I / F unit 8 includes a writing unit 8a and a MediaBus I / F unit 8b.

  First, a pipeline configuration in units of TS packets in the system decoder 100e will be described, and then an architecture that enables Demux processing including the PES decoder will be described.

(2) Pipeline configuration of system decoder 100e As a pipeline operation in units of TS packets of the system decoder 100e, a two-sided memory 1 of 188 bytes on one side is arranged at the rear stage of the TS-IF unit 5 to configure an IF stage. ing.

  In the IF stage, the following processing is performed.

  MPEG2-TS data (TSDATA) sent together with the input clock (TSCLK) is captured by TSCLK. At this time, the data valid (TSVALID) sent simultaneously with TSDATA is referred to, and the data is taken in only when it is valid data. In addition, the capture unit can be selected in units of 1 byte or 1 bit.

  The “47” code which is the head data of the MPEG2-TS packet is searched, and it is confirmed that the “47” code exists every 188 bytes.

  In order to speed up the synchronization acquisition candidate processing, a plurality of counters that operate independently are mounted to handle a plurality of synchronization acquisition candidates. When the synchronization acquisition of any one of the synchronization acquisition candidates is established, the other synchronization acquisition candidates are canceled.

  When synchronization acquisition is established, data of the MPEG2-TS packet starts to be stored in the 188-byte memory 1 in order from the first “47” code.

  The 188-byte memory 1 has two surfaces, and the surface on which writing on all the surfaces has been completed is switched to a reading surface from the subsequent pipeline stage.

  A register set 20 is provided at the subsequent stage of the DEMUX unit 7 to configure the D stage.

  In the D stage, the following processing is performed.

  The MPEG2-TS data is sequentially read from the side where writing has been completed in the two-sided memory 1 of 188 bytes provided at the subsequent stage of the IF stage.

  Among the read MPEG2-TS packet data, the TS header portion and, if present, the control data of the adaptation area are sequentially set in the TS analysis register 7a1.

  This read address is used to identify which one of the 188 bytes of the MPEG2-TS packet is being read.

  The base of MPEG2-TS analysis and extraction / separation in the D stage refers to the read address from the 188-byte two-sided memory 1 and the value of the TS analysis register 7a1, and the data structure of the MPEG2-TS packet Analysis proceeds.

  At the stage where the read address from the two-plane memory 1 has advanced to the end of reading the PID, it is determined whether or not the PID has been designated for extraction and separation.

  In this PID determination, if it is a section system, a PES system, or a PES system, it is determined whether it is an independent PES system, an audio system, or a video system.

  The transport scramble control, adaptation field control, and continuity counter value are set in the TS analysis register 7a1.

  The continuity counter value and the adaptation field control value are checked to determine whether the packet is an MPEG2-TS packet having a payload to be discarded, whether there is an adaptation area, and whether there is a payload.

  Next, if there is an adaptation field, the data in the adaptation area is continuously set in the TS analysis register 7a1.

  The beginning of the adaptation area is the adaptation length, and this length is checked. If the value is not 0, the adaptation length value is set in the adaptation length counter, and down-counting is started. When the adaptation length is 0, it is determined that the next byte is a pointer field in the case of section data, and the first byte of the PES in the case of PES data.

  If the adaptation length is not 0, the next byte includes a PCR flag (identifier indicating whether the packet is an MPEG2-TS packet including PCR) or a discontinuity indicating whether the included PCR is a discontinuous PCR. The tee indicator is set in the TS analysis register 7a1.

  If the PCR flag indicates that there is a PCR, the PCR is extracted. At this time, whether or not to load the PCR value to the STC which is the clock of the system decoder 100e is controlled by the load control register value of the PCR.

  If the discontinuity indicator is set, it is determined that the PCR included in the MPEG2-TS packet is a discontinuous PCR. The load control of the discontinuous PCR to the STC is controlled by the PCR load control register value.

  The loading of the discontinuous PCR into the STC also means that the relationship with the time stamp values of the video ES and audio ES already stored in the SDRAM 4 becomes discontinuous, so that the AV frame data already stored is stored. The valid bit of the time stamp corresponding to (video ES / audio ES) is invalidated. Here, the Valid bit is used for identifying whether the time stamp value is valid or invalid. When it is valid, it is used as a time stamp value used for comparison with the STC when performing processing for waiting until the time when the frame data is to be output from the system decoder 100e. If it is invalid, the process for waiting until the time to be output is not performed.

  When the adaptation field ends, the process branches depending on whether the PID filtering result is a section system or a PES system.

  When the unit start indicator of the TS header is set, it is determined that there is a 1-byte pointer field in front of the payload because the section head includes section start data. In the case of the PES system, it is determined that PES data is stored from the beginning of the payload.

  In the case of a section system, a section header part is set in the section analysis register 7a2.

  The first byte of the section is a table ID. Section filtering is performed after the section headers are aligned, but the MPEG2-TS packet may end with a table ID. In this case, filtering by PID and table ID is performed and it is confirmed whether or not the continuation flag is set. Sets a continuation flag for storing whether or not a section straddling has been received.

  Here, the continuation flag is provided in pairs for all the filters.

  The continuation flag is cleared when the unit start indicator in the TS header portion stored in the MPEG2-TS packet that hits the filter for which the continuation flag is set is 1. The section continued in the MPEG2-TS packet ends, and it is determined that a new section is stored, and the continuation flag is cleared.

  Here, when the MPEG2-TS packet ends in the middle of the section header portion, the next MPEG2-TS packet data is not necessarily the subsequent packet data, so the section analysis register 7a2 is a section filter as a register set. Installed for a few minutes.

  In the case of the PES system, the PES header portion is set in the PES analysis register 7a3.

  The head of the PES header is a fixed code “000001” of the packet start code prefix. The 8th byte from the beginning of the PES header is a PTSDTS flag (an identifier indicating whether or not a time stamp that is PTS or DTS is included). If the time stamp is included, extraction is scheduled to be performed.

  When the next byte is the PES header length and the value of the PES header length is not 0, a value is set in the PES header length down counter, and down counting is performed.

  At the time when the PES header length down-count is completed, the first byte of the ES data exists.

  In the extraction of ES data, the ES extraction is realized by performing the deletion process of the PES header part.

  When the MPEG2-TS packet ends in the middle of the PES header part, it is determined from the PES header length down counter value and the continuation flag which byte of the PES header part should be resumed. .

  Here, when the MPEG2-TS packet ends in the middle of the PES header part, the next MPEG2-TS packet data is not necessarily the subsequent packet data, so the PES header analysis register 7a3 is a register set. There are as many PES filters as PID setting.

  Whether the section system or the PES system is used, the 188-byte read address from the memory 2 indicates which byte of the MPEG2-TS packet is being processed, recognizes the end of the MPEG2-TS, and sets the continuation flag. Is determined.

  Thereafter, writing from the Media I / F unit 8 to the SDRAM 4 is performed as needed. Here, the following processing is performed.

  Of the register set 20 provided after the D stage, the data of the register for which writing has been completed is written to the SDRAM 4. Here, the register set 20 is composed of two registers, and the capacity of each register is a write transaction unit to the SDRAM 4.

  The write unit is a size that can be issued by a Store transaction. Each of the section, PES, and ES is a data unit of about several bytes extracted and separated from 188 bytes of the MPEG2-TS packet.

  The writing process to the SDRAM 4 is executed at the D stage. If the writing to the SDRAM 4 is not completed within the period of the D stage, a bus error interrupt is generated.

  Pipeline operations in units of TS packets (in units of 188 bytes) are delimited in the two-plane memory 1 connected to the subsequent stage of the IF stage. The above is the first half processing unit of the system decoder 100e. The two-stage pipeline operation of the first half processing unit of the system decoder 100e is as shown in FIG.

(3) Second Half Processing Unit of System Decoder 100e The basic configuration of the second half processing unit of the system decoder 100e is as shown in the block diagram of FIG. In the latter half processing unit of the system decoder 100e, the data written in the SDRAM 4 is read out and output from the system decoder 100e with AV synchronization. Here, the processing after reading from the SDRAM 4 operates independently of the pipeline operation in units of TS packets.

(4) Demux Processing (4-1) Configuration of DEMUX Unit 7 Demux processing including mainly ES extraction processing from the PES decoder will be described below. Here, the operation of the D stage of the DEMUX unit 7 will be described. The D stage includes a PID filter operation unit 7b, a TS analysis unit 7a, a Section analysis unit 7a2, a PES analysis unit 7a3, and a register set 20 for temporarily storing a separation result. FIG. 25 is a timing chart showing the operation of the D stage.

(4-2) Processing of DEMUX Unit 7 TS packet data for one packet (from the 0th byte to the 187th byte) is read from the two-plane memory 1 connected to the subsequent stage of the TS-IF unit 5. This read address identifies the number of data from the beginning of the TS packet. The TS packet is stored in a register 7a1 provided in the TS analysis unit 7a according to the read address value. The TS data to be stored in the TS analysis unit 7a holds data in the TS header part, a part of data corresponding to adaptation, and a pointer field in the case of a section.

  Here, when the information up to the PID is written in the register 7a1 of the TS analysis unit 7a, the classification of TS packet types (section, video, audio, or independent PES) is performed. Based on this result, it is possible to identify the section system or the PES system (video, audio, independent PES). Using this result, it is determined whether to use the register 7a2 of the section analysis unit or the register 7a3 of the PES analysis unit.

  In the case of the PES system, only the necessary portion (13 bytes from the beginning of the PES and including the PES header length) of the information corresponding to the PES header is stored in the register 7a3 of the PES analysis unit. Here, depending on the size of the adaptation, the PES header may be larger than the TS packet unit (188 bytes). Therefore, registers 7a3 corresponding to the number of filters for performing PES decoding are mounted, and each register 7a3 has a PES header write pointer that can grasp the written position. When straddling TS packets, this PES header write pointer is stopped. Here, when the down counter value of the PES header length does not end by the end of the TS packet, the TS packet is straddled by the PES header portion. On the other hand, when the PES header length down counter is completed before the TS packet is completed, the TS packet is straddled after the PES header part. At the end of the PES header length down counter, the PES header write pointer is cleared. In the case of continuous reception restart, the PES header information extraction can be restarted by referring to the filter hit determination by PID and the PES header write pointer managed for each PID. Since PES can be filtered only by PID, no continuation flag is required.

  In the case of a section system, only the necessary portion (for 6 bytes from the beginning of the section, depending on the section length) of the information corresponding to the section header is stored in the register 7a2 of the section analysis section. Here, depending on the size of the adaptation, the TS packet may end before the data corresponding to the section header section is stored in the register 7a2 of the section analysis section. For this reason, each section analysis unit has a section header write pointer and a continuation flag for each filter number so that the section analysis unit can grasp how much the section header has been written. By referring to the section header write pointer value and the continuation flag, the section header information extraction can be resumed even if the data of the subsequent section is received for a while after straddling the TS packet. .

  Next, processing when the TS packet unit is exceeded will be described.

  In the case of the section system, the determination as to whether the received section data is data that can be contained in the TS packet or not can be made as follows: The determination is made based on the determination and (b) whether or not the section length down-count is completed at the end of the TS packet (at the 188th byte) based on the section length information existing in the section header section. If it is determined that it is not contained in the TS packet, the continuation flag of the number hitting the filter is set and the section length down counter value is cleared.

  In addition, when the value of unit_start_indicator in the TS header information part of the TS packet that hits the same filter is 1, the continuation flag is cleared. Judge that stored. Here, the start position of the new section is indicated by pointer_field.

  In the case of the PES system, the determination as to whether the received PES data is data that fits in the TS packet or data that does not fit is performed only for the PES header part.

  In a state where the PES header write pointer (pointer indicating how far the PES header has been stored in the register 7a3 of the PES analysis unit. It is determined that the PES header has ended due to the end of the PES header length) has not ended. When the process ends (at the 188th byte), it is determined that the PES header has straddled the TS packet, and the continuation flag of the number hitting the filter is set. This continuation flag is used to identify which register set of a plurality of register sets provided in the PES analysis unit.

  The continuation flag possessed by the PES header analysis unit is cleared when the PES header unit is stored in the register 7a3 of the PES analysis unit.

  Since the PES data itself after the PES header part can be separated and identified only by the PID, the PES length information is not referred to. Instead, the beginning of the PES is identified by unit_start_indicator in the TS packet header portion, and separation and extraction are performed from the beginning of the PES data.

  Hereinafter, the register set 20 for temporarily holding the extraction / separation result will be described.

  Necessary data is filtered from the TS packet that is a lump of 188 bytes, and the data determined to be separated and extracted is stored in the register set 20 in units of Store transactions. Accordingly, it is sufficient to configure the register set 20 with two registers each having a few bytes (eight bytes as an example).

(5) D-stage SDRAM write processing Data is transferred and written from the 8-byte two-sided register set 20 in the final stage of the D stage to the SDRAM 4. Writing to the SDRAM 4 is processed within 1 TS packet period of the D stage. Data written from the register set 20 to the SDRAM 4 includes a section, an independent PES, an audio PES, and a video ES.

  In section writing, writing to a plurality of areas of the SDRAM 4 may occur. In the multi-section, a plurality of different sections may be stored in one TS packet, and in this case, the write area to the SDRAM 4 is different for each section.

  In the case of an independent PES, an audio PES, and a video ES, a situation in which the write area to the SDRAM 4 is different does not occur in the operation in units of 1 TS packet period.

  As described above, the ES data after the PES header portion is deleted from the PES data can be extracted and stored in the SDRAM 4, and the necessary data is read from the SDRAM 4 while performing time management, and the ES and the video decoder and audio decoder in the subsequent stage are read out. The system decoder 100a can be configured.

  According to the system decoder 100e according to the fifth embodiment, since a pipeline operation that completes processing in units of TS packets is possible, a large-scale memory dedicated to the PES decoder is not necessary. Therefore, there is an effect that the chip manufacturing cost can be reduced as compared with the case where the PES decoding memory is configured on-chip or off-chip. Further, since a large-scale memory dedicated to the PES decoder is not necessary, access to this memory can be reduced. Therefore, it is possible to allocate the bandwidth of the external bus to other access. For example, it is possible to allocate an access band for the CPU to use the SDRAM 4 as a work memory. In addition, since the external memory access is reduced, the external access frequency can be lowered, the power consumption is reduced, and the number of external pins can be reduced, so that the chip manufacturing cost can be reduced.

  In addition, since the descrambling unit 6 and the two-plane memories 2 and 3a to 3c are omitted from the system decoder 100a according to the first embodiment shown in FIG. 7, the circuit scale is greatly increased as compared with the system decoder 100a. Can be reduced.

It is a block diagram which shows roughly the structure of the system decoder based on 1st invention. It is a timing chart which shows the pipeline process of the system decoder which concerns on 1st invention. It is a block diagram which shows roughly the structure of the system decoder based on 2nd invention. It is a timing chart which shows the pipeline process of the system decoder which concerns on 2nd invention. It is a block diagram which shows roughly the structure of the system decoder based on 3rd invention. It is a timing chart which shows the pipeline process of the system decoder which concerns on 3rd invention. It is a block diagram which shows the structure of the first half process part of the system decoder which concerns on Embodiment 1 of this invention. It is a block diagram which shows the basic composition of the latter half process part of the system decoder which concerns on Embodiment 1 of this invention. 6 is a timing chart showing operations of a D stage and a W stage with respect to the system decoder according to the first embodiment of the present invention. FIG. 3 is a block diagram showing a configuration around a section analysis register in the system decoder according to the first embodiment of the present invention. FIG. 2 is a block diagram showing a configuration around a PES analysis register in the system decoder according to the first embodiment of the present invention. 4 is a timing chart showing operations from analysis of TS data to section separation with respect to the system decoder according to the first embodiment of the present invention. 5 is a timing chart showing multi-section extraction / separation operation from analysis of TS data, with respect to the system decoder according to the first embodiment of the present invention. FIG. 6 is a timing chart showing an operation when a TS packet is terminated in a section header at the time of section separation and extraction from analysis of TS data, with respect to the system decoder according to the first embodiment of the present invention. 5 is a timing chart showing an operation when a TS packet is terminated in the middle of a section from the analysis of TS data, when a section is separated and extracted, with respect to the system decoder according to the first embodiment of the present invention. 6 is a timing chart showing an operation of extracting and separating data before data indicated by a pointer field from analysis of TS data, with respect to the system decoder according to the first embodiment of the present invention. 6 is a timing chart showing an operation when there is no pointer field when a section is extracted with respect to the system decoder according to the first embodiment of the present invention. It is a figure which shows the example of MPEG2-TS containing a section regarding the system decoder which concerns on Embodiment 1 of this invention. It is a figure which shows the example of a PES header part regarding the system decoder which concerns on Embodiment 1 of this invention. It is a block diagram which shows the structure of the first half process part of the system decoder which concerns on Embodiment 2 of this invention. It is a block diagram which shows the basic composition of the latter half process part of the system decoder which concerns on Embodiment 2 of this invention. It is a block diagram which shows the structure of the first half process part of the system decoder which concerns on Embodiment 3 of this invention. It is a block diagram which shows the structure of the first half process part of the system decoder which concerns on Embodiment 4 of this invention. It is a block diagram which shows the structure of the first half process part of the system decoder which concerns on Embodiment 5 of this invention. It is a timing chart which shows operation | movement of D stage regarding the system decoder which concerns on Embodiment 5 of this invention.

Explanation of symbols

1-3, 3a-3c Memory, 4 External storage device, 5 TS-IF part, 6 Descramble part, 7 DEMUX part.

Claims (4)

A synchronization acquisition unit that synchronously acquires TS (Transport Stream) data;
A memory set connected to the subsequent stage of the synchronization acquisition unit, each memory having a storage capacity corresponding to a data unit of TS data, and alternately performing a write operation and a read operation of TS data input from the synchronization acquisition unit Including a first storage unit,
A descrambling unit connected to a subsequent stage of the first storage unit and performing descrambling processing on the TS data read from the first storage unit;
A memory set connected to the subsequent stage of the descramble unit, each memory having a storage capacity corresponding to a data unit of TS data, and alternately performing a write operation and a read operation of the TS data input from the descramble unit A second storage unit including:
An extraction / separation unit that is connected to the subsequent stage of the second storage unit and extracts and separates necessary TS data from a plurality of TS data read from the second storage unit;
A memory set connected to the subsequent stage of the extraction / separation unit, each memory having a storage capacity corresponding to a data unit of TS data, and alternately performing a write operation and a read operation of the TS data input from the extraction / separation unit A third storage unit including:
A system decoder having a four-stage pipeline structure in units of TS packets, comprising a writing unit connected to a subsequent stage of the third storage unit and writing TS data read from the third storage unit to an external memory. A synchronization acquisition unit that synchronously acquires TS (Transport Stream) data;
A memory set connected to the subsequent stage of the synchronization acquisition unit, each memory having a storage capacity corresponding to a data unit of TS data, and alternately performing a write operation and a read operation of TS data input from the synchronization acquisition unit Including a first storage unit,
An extraction / separation unit connected to a subsequent stage of the first storage unit, for extracting and separating necessary TS data from a plurality of TS data read from the first storage unit;
A memory set connected to the subsequent stage of the extraction / separation unit, each memory having a storage capacity corresponding to a data unit of TS data, and alternately performing a write operation and a read operation of the TS data input from the extraction / separation unit A second storage unit including:
A system decoder having a three-stage pipeline structure in units of TS packets, the system decoder including a writing unit connected to a subsequent stage of the second storage unit and writing TS data read from the second storage unit to an external memory. A synchronization acquisition unit that synchronously acquires TS (Transport Stream) data;
A memory set connected to the subsequent stage of the synchronization acquisition unit, each memory having a storage capacity corresponding to a data unit of TS data, and alternately performing a write operation and a read operation of TS data input from the synchronization acquisition unit Including a first storage unit,
An extraction / separation unit connected to a subsequent stage of the first storage unit, for extracting and separating necessary TS data from a plurality of TS data read from the first storage unit;
A system decoder having a two-stage pipeline structure in units of TS packets, comprising a writing unit connected to a subsequent stage of the extraction / separation unit and writing TS data input from the extraction / separation unit to an external memory. The extraction / separation unit invalidates a time stamp added to the TS data when PCR (Program Clock Reference) of the extracted and separated TS data is discontinuous. The system decoder according to one.

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