JP2006133754A - Display device and its driving method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display apparatus capable of switching a screen between a display in a vertical direction and a display in a horizontal direction. <P>SOLUTION: The scanning direction of a first gate signal line driver circuit is perpendicular to the scanning direction of a source signal line driver circuit, and the scanning direction of a second gate signal line driver circuit is perpendicular to the scanning direction of the first gate signal line driver circuit. In a normal display, vertical scanning of a screen is performed by the first gate signal line driver circuit. Meanwhile, on switching between display in a vertical direction and display in a horizontal direction, vertical scanning of the screen is performed by the second gate signal line driver circuit. Since the pixels are driven by a field sequential method and a pixel is not divided into RGB portions, switching between vertical and horizontal directions can be facilitated. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a display device in which a pixel portion is formed using a liquid crystal element, a driving method thereof, and an electronic apparatus using such a display device for a display portion. In particular, the present invention relates to a display device using field sequential driving and an electronic apparatus using such a display device for a display unit.

  In recent years, display devices in which a semiconductor thin film is formed on an insulator such as a glass substrate, in particular, electronic circuits using thin film transistors (hereinafter referred to as TFTs) have been used in various fields. In particular, active matrix type display devices such as LCD (Liquid Crystal Display) are often used and used in many products. An active matrix display device using TFTs has hundreds of thousands to millions of pixels arranged in a matrix, and displays the image by controlling the charge of each pixel by the TFT arranged in each pixel. It is carried out.

  Furthermore, as a recent technology, in addition to the pixel TFT that constitutes the pixel, a technology related to a polysilicon TFT that simultaneously forms a drive circuit on a substrate by using a TFT in the peripheral region of the pixel portion has been developed. As a result, display devices have become an indispensable device for display units and the like of mobile information terminals, which have greatly contributed to lower power consumption, and whose application fields have been remarkably expanding in recent years.

  An example of a general display device is shown in FIG. FIG. 2A illustrates an example of a liquid crystal display device in which a pixel portion and a driver circuit are integrally formed over an insulator. A pixel portion 201 is disposed at the center of the substrate 200, and a source signal line driver circuit 202, a gate signal line driver circuit 203, and the like are formed around the pixel portion 201. In FIG. 2A, the gate signal line driver circuit 203 is arranged symmetrically on both the left and right sides of the pixel portion 201, but this may be arranged on only one side. However, considering the reliability and efficiency of the operation of the circuit, it is preferable to use a symmetrical arrangement as shown in FIG.

  Signals input to the source signal line driver circuit 202 and the gate signal line driver circuit 203 are supplied from the outside via a flexible printed circuit (FPC) 204.

  A counter electrode or the like is formed on the counter substrate 210 and is bonded to the substrate 200 with a certain gap through a sealant 205. Thereafter, a liquid crystal material is injected into a gap between the substrate 200 and the counter substrate 210 from an injection port prepared in advance, and the injection port is sealed with a sealing material 206.

  In the pixel portion 201, as illustrated in FIG. 2B, m source signal lines and n gate signal lines are arranged orthogonally. A pixel as shown in FIG. 2C is formed at a location (220) corresponding to the intersection of the source signal line and the gate signal line. A source signal line 221, a gate signal line 222, a pixel TFT 223, a liquid crystal element 224, a storage capacitor 225, and a counter electrode 226 are included. Here, the number of pixels is m × n pixels.

  The operation of the display device will be briefly described with reference to FIG. In general, screen flickering (referred to as flicker) is not recognized by human eyes, and the screen is drawn about 60 times per second. Here, a period indicated by 501, that is, a period required to draw the screen once is referred to as one frame period (FIG. 5A).

  In one frame period, gate signal lines are selected in order from the first row. The selection period 504 per row is expressed as one horizontal period. A period 502 until the selection of the last line (the nth line) is denoted as a line scanning period. Thereafter, the same operation is performed in the next frame period with the vertical blanking period 503 interposed therebetween (FIG. 5B).

  In one horizontal period, video signals are written to the pixels in the selected row in order from the source signal line. This period 505 is referred to as a dot sampling period. A period 507 required to write a video signal to one pixel is referred to as a 1-dot sampling period. When video signal writing is completed in one row of pixels, a similar operation is performed in the next horizontal period with the horizontal blanking period 506 interposed therebetween (FIG. 5C).

  Next, a specific operation of the circuit will be described. FIG. 6A illustrates a configuration example of a source signal line driver circuit of a display device, which includes a shift register 602 using a plurality of stages of flip-flop circuits 601 (FF), a NAND 603, a buffer 604, and a sampling switch 605. ing.

  In the description of the operation, reference is made to FIG. The shift register 602 sequentially outputs pulses from the first stage according to the clock signal (CK), the clock inversion signal (CKb), and the start pulse (SP).

  When the pulse output from the shift register 602 has an overlap at the adjacent stage, the pulse is input to the NAND 603 and has no overlap at the adjacent stage. Thereafter, the NAND output passes through the buffer 604 and becomes a sampling pulse.

  When the sampling pulse is input to the sampling switch 605, the sampling switch 605 is turned ON, and the potential of the video signal (Video) is charged to the source signal line connected to the sampling switch. At the same time, writing is performed on one pixel connected to the above-described source signal line in the row in which the gate signal line is selected. In FIG. 6B, a period indicated by 610 is a one-dot sampling period.

  Next, the gate signal line driver circuit illustrated in FIG. 7A is described. A portion between the shift register and the buffer is almost the same as that of the source signal line driver circuit, and includes a shift register 702 using a plurality of stages of flip-flops 701, a NAND 703, and a buffer 704.

  In the description of the operation, reference is made to FIG. Similarly to the source signal line driver circuit, the shift register 702 sequentially outputs pulses from the first stage according to the clock signal (CK), the clock inversion signal (CKb), and the start pulse (SP).

  When the pulse output from the shift register 702 has an overlap at the adjacent stage, the pulse is input to the NAND 703 to be a pulse having no overlap at the adjacent stage. Thereafter, the NAND output passes through the buffer 704 and becomes a gate signal line selection pulse.

  In the row to which the gate signal line selection pulse is input, the video signal written to the source signal line as described above is written to each pixel. In FIG. 7B, the period indicated by 710 is one horizontal period, and the period indicated by 720 is the aforementioned one-dot sampling period.

  By the way, the display device is generally used by being fixed in the direction in which the device is installed. However, when the application is multi-functional, such as a personal computer, the display device is horizontally long in a certain application. There is a case where it is desired to use the display device in a layout and in a certain application in a vertically long layout. In such a case, as shown in FIG. 3A, there is a method of displaying in a state where the housing of the display device is rotated by 90 °.

  The timing for driving the display device in this case is shown in FIG. Here, a period indicated by 1001 is referred to as one frame period. In one frame period, gate signal lines are selected in order from the first row. The selection period 1004 per row is expressed as one horizontal period. A period 1002 until the selection of the last line (m-th line) is referred to as a line scanning period. Thereafter, the same operation is performed in the next frame period with the vertical blanking period 1003 interposed therebetween. In one horizontal period, video signals are written to the pixels in the selected row in order from the source signal line. This period 1005 is referred to as a dot sampling period. A period 1007 required for writing a video signal to one pixel is referred to as a one-dot sampling period. When video signal writing is completed in one row of pixels, the same operation is performed in the next horizontal period with the horizontal blanking period 1006 interposed therebetween.

  Also, some recent mobile phones have a TV broadcast receiving function, and it is desirable that the mobile phone can be set to be horizontally long when displaying a TV image and can be vertically long when character information is displayed.

  In the pixel portion of the active matrix display device, as shown in FIG. 2B, m × n pixels are arranged in a matrix, and video signal writing is performed from a pixel at coordinates (1, 1). In order, (1, 2), (1, 3), and (1, 4) are performed. When (1, m) is reached, one horizontal cycle is completed. This is repeated n times, and when the writing of the pixel at the coordinates (m, n) is finally completed, the writing of one screen is completed.

  Returning again to FIG. In the case of the landscape display (left) and the portrait display (right), the pixels of the coordinates (1, 1) where writing is performed first are indicated by 301 and 302, respectively. As shown in FIG. 3A, in the case of displaying the same screen in the landscape display and the portrait display, when the input of the video signal corresponds to the landscape display, the input order is as follows. Upper left → upper right → ... → lower right, but when using this video signal for portrait display, the writing order of the display device itself does not change. Lower right → ... Lower left order.

  However, since it is preferable that the display device can be flexibly switched between vertical and horizontal displays, it is not efficient to prepare video signals of different formats each time. Thus, display is performed by temporarily storing the video signal in the memory and reading it out using the frame memory.

  Since the frame memory stores the video signal of each pixel for each memory cell, reading from an arbitrary address is possible regardless of the order of writing. By changing the reading order of the video signals once written in the frame memory, the above-described vertical / horizontal display can be switched.

  In the frame memory for storing the video signal for one frame, each storage circuit is managed by an address as shown in FIG. Therefore, when a video signal is input, (1, 1) (2, 1) ... (m, 1), (1, 2) (2, 2) ... (m, 2), ... .., (1, n) (2, n)... (M, n) are written in the order, and in the case of landscape display, they are read in the same order as written.

  On the other hand, in the case of the portrait display, when it is desired to display as shown in FIG. 3A, (m, 1) (m, 2) ... (m, n), (m-1, 1) (m- 2, 2)... (M−1, n),..., (1, 1) (1, 2).

  As shown in FIG. 4A, the frame memory is generally provided for at least two frames (first frame memory 402 and second frame memory 403), and the video signal 401 is stored in one frame memory. While writing is performed, reading from another frame memory is performed, and a screen is displayed through format conversion 404.

In this way, the screen can be switched between vertical and horizontal directions while the display device is normally driven. However, normal screen display can be performed only by this method only when m = n, that is, the number of vertical and horizontal pixels is equal. When performing vertical / horizontal display conversion in a display device with different vertical and horizontal pixel numbers on the screen, format conversion is required.
As shown in [i] of FIG. 4B, the video signal is a video signal written to the first pixel to m pixels in the first row, a video signal written to the first pixel to m pixels in the second row,.・ It is composed of n pieces. In this case, it corresponds to horizontal m × vertical n pixels. In order to switch the display in the vertical and horizontal directions, it is necessary to convert it into a form corresponding to horizontal n × vertical m pixels as shown in [ii] of FIG. This is called format conversion. Since the format conversion itself may be performed using a known technique, its details are omitted.

  Recently, various software has been supplied also to small portable terminals such as mobile phones, and the use in one device tends to diversify. Therefore, the above-described vertical / horizontal display switching technology is important. However, when the vertical and horizontal data are exchanged using the frame memory as described above, there is a problem that the video becomes discontinuous and noise is likely to occur.

  Therefore, the present inventor has previously invented a display device that performs screen vertical / horizontal switching without using a frame memory. The display device includes a source signal line driver circuit, a first gate signal line driver circuit, and a second gate signal line driver circuit. The scanning direction of the second gate signal line driving circuit is configured to be orthogonal to the scanning direction of the first gate signal line driving circuit.

  Here, it is assumed that the scanning direction is a direction orthogonal to the arrangement of the signal lines controlled by the respective driving circuits. Further, the normal display is referred to as the first display, and the case where the display is switched between the vertical and horizontal directions is referred to as the second display.

  In normal display, the vertical scanning of the screen is performed by the first gate signal line driving circuit. The video is displayed in a direction according to the scanning direction of the first gate signal line. On the other hand, in the second display, the vertical scanning of the screen is performed by the second gate signal line driving circuit. The video is displayed in a direction according to the scanning direction of the second gate signal line.

Details are described in Patent Document 1. The contents described in Patent Document 1 provide a display device capable of switching between vertical and horizontal display without adding a frame memory or the like.
JP2003-76315

  However, the display device using the vertical / horizontal display switching described above has the following problems. That is, it is necessary to increase the number of signal lines as compared with a conventional display device. In particular, increasing the number of source signal lines lowers the aperture ratio of the pixel. As shown in FIG. 19, the pixel has three pixel electrodes of red (hereinafter R), green (hereinafter G), and blue (hereinafter B). By increasing the number of source signal lines, the pixel is further elongated to increase the aperture ratio. Reduce. In FIG. 19, the pixels are RGB source signal lines 1901, 1902, 1903, first gate signal lines 1907, RGB second gate signal lines 1904, 1905, 1906, and RGB pixel electrodes 1908, 1909, 1910, respectively. , RGB pixel transistors 1911, 1912, 1913. In the pixel of this configuration, since the number of second gate signal lines is larger than that of a normal liquid crystal pixel, the aperture ratio is reduced.

  The display device of the present invention can perform a first display and a second display, and includes a source signal line driver circuit, a first gate signal line driver circuit, and a second gate signal line driver circuit. Here, the scanning direction of the second gate signal line driving circuit is orthogonal to the scanning direction of the first gate signal line driving circuit.

  In the first display, the vertical scanning of the screen is performed by the first gate signal line driving circuit. The video is displayed in a direction according to the scanning direction of the first gate signal line. On the other hand, in the second display, the vertical scanning of the screen is performed by the second gate signal line driving circuit. The video is displayed in a direction according to the scanning direction of the second gate signal line. In addition, the pixel driving is field sequential driving. In field sequential driving, one frame period is divided into three sub-frame periods, and RGB light is independently irradiated in each period to perform color display with one pixel.

  One display device capable of the first display and the second display of the present invention includes a light-emitting source whose emission color periodically changes, a source signal line driver circuit, a first gate signal line driver circuit, A second gate signal line driver circuit and a plurality of pixels are included. The scanning direction of the first gate signal line driving circuit is orthogonal to the scanning direction of the second gate signal line driving circuit.

  One display device capable of the first display and the second display of the present invention includes a light-emitting source whose emission color periodically changes, a source signal line driver circuit, a first gate signal line driver circuit, A second gate signal line driver circuit and a plurality of pixels are included. The plurality of pixels include a source signal line, a first gate signal line, a second gate signal line orthogonal to the first gate signal line, a first transistor, and a second transistor. Yes. A gate electrode of the first transistor is electrically connected to a first gate signal line, an input electrode of the first transistor is electrically connected to a source signal line, and an output electrode of the second transistor Are electrically connected to the input electrode of the second transistor. The gate electrode of the second transistor is electrically connected to the second gate signal line.

  In the above, when the first display is performed, the driving frequency of the source signal line driver circuit is higher than the driving frequency of the first gate signal line driver circuit, and when the second display is performed, the source signal is The drive frequency of the line drive circuit is preferably lower than the drive frequency of the first gate signal line drive circuit.

  In the above, at least one of the source signal line driver circuit, the first gate signal line driver circuit, and the second gate signal line driver circuit, and the plurality of pixels are formed over the same substrate. preferable.

  One display device capable of the first display and the second display of the present invention includes a light-emitting source whose emission color periodically changes, a first source signal line driving circuit, and a second source signal line driving. The circuit includes a circuit, a first gate signal line driver circuit, a second gate signal line driver circuit, and a plurality of pixels. The first source signal line driver circuit, the second source signal line driver circuit, the first gate signal line driver circuit, the second gate signal line driver circuit, and the plurality of pixels are all over the same substrate. Is formed. The scanning direction of the first gate signal line driving circuit and the scanning direction of the second gate signal line driving circuit are orthogonal to each other.

  One display device capable of the first display and the second display of the present invention includes a light-emitting source whose emission color periodically changes, a first source signal line driving circuit, and a second source signal line driving. The circuit includes a circuit, a first gate signal line driver circuit, a second gate signal line driver circuit, and a plurality of pixels. The plurality of pixels include a first source signal line, a second source signal line, a first gate signal line, a second gate signal line orthogonal to the first gate signal line, and a first transistor. And a second transistor. The gate electrode of the first transistor is electrically connected to the first gate signal line, and the input electrode of the first transistor is electrically connected to the first source signal line. The gate electrode of the second transistor is electrically connected to the second gate signal line, and the input electrode is electrically connected to the second source signal line.

  In the above, when the first display is performed, the video is displayed in an orientation according to the scanning direction of the first gate signal line driver circuit, and when the second display is performed, the video is the second It is preferable that the display is performed in the direction according to the scanning direction of the gate signal line driving circuit.

  In the above, at least one of the first source signal line driver circuit, the first source signal line driver circuit, the first gate signal line driver circuit, and the second gate signal line driver circuit, The plurality of pixels are preferably formed on the same substrate.

  In the above, each of the plurality of pixels may include a liquid crystal element.

  One of the driving methods of the display device capable of the first display and the second display of the present invention is a source signal line driver circuit, a first gate signal line driver circuit, a second gate signal line driver circuit, In the display device having a plurality of pixels, the scanning direction of the first gate signal line driving circuit and the scanning direction of the second gate signal line driving circuit are crossed, and the plurality of pixels are It is characterized by field sequential driving.

  In the above driving method, when performing the first display, the driving frequency of the source signal line driving circuit is higher than the driving frequency of the first gate signal line driving circuit, and when performing the second display, It is preferable that the driving frequency of the source signal line driver circuit is lower than the driving frequency of the first gate signal line driver circuit.

  One of driving methods of a display device capable of first display and second display of the present invention is a first source signal line driver circuit, a second source signal line driver circuit, and a first gate signal line. In a display device having a driving circuit, a second gate signal line driving circuit, and a plurality of pixels, the scanning direction of the first gate signal line driving circuit and the scanning of the second gate signal line driving circuit It is characterized by crossing the direction and driving a plurality of pixels in a field sequential manner.

  In the above driving method, when the first display is performed, the video is displayed in an orientation according to the scanning direction of the first gate signal line driving circuit, and when the second display is performed, the video is It is preferable that the display be performed in an orientation according to the scanning direction of the second gate signal line driver circuit.

According to the present invention, it is possible to easily switch the screen between vertical and horizontal directions, improve the aperture ratio, and provide a high-quality display device.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the present invention can be implemented in many different modes, and those skilled in the art can easily understand that the modes and details can be variously changed without departing from the spirit and scope of the present invention. Is done. Therefore, the present invention is not construed as being limited to the description of this embodiment mode.

  FIG. 1A shows an embodiment of the present invention. Over the substrate 100, a pixel portion 105, a source signal line driver circuit 102, a first gate signal line driver circuit 103, and a second gate signal line driver circuit 104 are formed.

  In the pixel portion 105, one pixel 101 is partitioned in a region surrounded by signal lines extending from the first gate signal line driver circuit 103, the second gate signal line driver circuit 104, and the source signal line driver circuit 102. Has been. A circuit configuration of the pixel 101 is illustrated in FIG. Each pixel has a source signal line 111, a first gate signal line 112, a second gate signal line 113, a first pixel TFT 114, a second pixel TFT 115, a liquid crystal element 116, a storage capacitor 117, and a counter electrode 118. is doing.

  The gate electrode of the first pixel TFT 114 is electrically connected to the first gate signal line 112, and ON / OFF is controlled by a pulse input to the first gate signal line 112. The gate electrode of the second pixel TFT 115 is electrically connected to the second gate signal line 113, and ON / OFF is controlled by a pulse input to the second gate signal line 113.

  A video signal input from the source signal line 111 is input to the pixel when both the first pixel TFT 114 and the second pixel TFT 115 are ON, and electric charge is held in the storage capacitor 117.

  The operation of the circuit will be described. In the present embodiment, the number of pixels is m × n. However, the format conversion of the video signal does not matter, so that the format conversion is not required to simplify the description. = N will be described as an example. Please refer to FIG. 1 and FIG.

  In the case of performing the first display, that is, the normal display, the second gate signal line driver circuit 104 keeps the second pixel TFT 115 ON over the entire screen. Thus, the pixel is controlled only by turning on and off the first pixel TFT 114. After that, the source signal line driving circuit and the first gate signal line driving circuit are driven in the same manner as in the prior art to display an image. As shown in FIG. 8A, the order of pixel writing is (1, 1) (2, 1)... (M, 1), (1, 2) (2, 2). m, 2), ..., (1, n) (2, n) ... (m, n).

  Next, the second display, that is, a case where the screen is switched between vertical and horizontal will be described. FIG. 8B shows a state in which FIG. 8A is rotated 90 ° clockwise. Since the display device of the present invention does not use a frame memory, the input order of video signals is not changed. Therefore, the order of writing to the pixels in the state shown in FIG. 8B is (1, n) (1, n-1)... (1,1), (2, n) (2, n -1) ... (2, 1), ..., (m, n) (m, n-1) ... (m, 1).

  Therefore, during the second display, the source signal line driver circuit 801 is driven at a lower speed than usual, and outputs a sampling pulse every horizontal period. Accordingly, since the sampling switch is kept open for one horizontal period, the video signal for one horizontal period is continuously written for each source signal line. On the other hand, the first gate signal line driving circuit 802 is driven at a higher speed than usual and outputs a gate signal line selection pulse every one dot sampling period. As a result, in each pixel, the first pixel TFT is turned on for one dot sampling period, and the video signal at that time is written. The second gate signal line driver circuit 803 operates in the same manner as the source signal line driver circuit 801. That is, when a sampling pulse is output from the source signal line driving circuit 801 and a video signal is input to a source signal line in a certain column, the second gate signal line in that column is selected and the selected second gate signal line is selected. Since all the second pixel TFTs connected to the gate signal line are turned on, writing of the video signal is permitted only to that column.

  FIG. 20 is a plan view of the pixel of the present invention. Since field sequential driving is performed, it is not necessary to separate the pixels into RGB. Accordingly, the number of necessary signal lines can be reduced, and the aperture ratio can be dramatically increased. In FIG. 20, a pixel includes a source signal line 2001, a first gate signal line 2003, a second gate signal line 2002, a pixel electrode 2004, and a pixel TFT 2005.

  Next, a field sequential embodiment will be described. In field sequential driving, color display is performed using a light source whose emission color periodically changes and an optical shutter such as a liquid crystal. As a light source whose emission color periodically changes, there is a light source that switches on and turns off RGB cold cathode tubes and LEDs. In addition, there is a method in which a color filter is rotated in front of a white light source to individually extract RGB components. For portable devices, it is preferable to use a device that switches on and turns on RGB LEDs.

  Generally, in a video such as a television, one frame period is about 16.6 ms. When this is divided into three sub-frames for each of RGB, it takes about 5.53 ms. However, considering the writing time to the pixel, the response speed of the liquid crystal, etc., the actual lighting period of each of RGB is preferably about 2 ms.

  FIG. 21 shows a timing chart. The operation will be described below. Here, for the sake of explanation, the order of the video is assumed to be the order of R, G, B. First, R data is written to the pixel. The liquid crystal responds sequentially from the written pixel. After the writing is finished and the response of the liquid crystal is finished, the R light source is turned on. After turning on the R light source for a certain time, the R light source is turned off. In FIG. 21, the time from the start of writing in the first row to the end of writing in the nth row is t1. The response time of the liquid crystal is t2. The lighting time of the light source (LED or the like) is t3.

  Next, G data is written into the pixel. The liquid crystal responds sequentially from the written pixel. After the writing is finished and the response of the liquid crystal is finished, the G light source is turned on. After turning on the G light source for a certain time, the G light source is turned off. Further, B data is written to the pixels. The liquid crystal responds sequentially from the written pixel. After the writing is finished and the response of the liquid crystal is finished, the B light source is turned on. After turning on the light source of B for a certain time, the light source of B is turned off.

  By repeating this, field sequential driving becomes possible. High-speed liquid crystal is required for field sequential driving, but in the present invention, liquid crystal materials such as OCB (Optically Compensated Bend), FLC (ferroelectric liquid crystal), and AFLC (anti-ferroelectric liquid crystal) can be used. There is, but is not limited to this. It can also be realized by using a TN (twisted nematic) liquid crystal by reducing the cell gap or using a transient state.

  FIG. 11 shows an example of the OCB liquid crystal. The OCB liquid crystal is a liquid crystal material having a wide viewing angle and a quick response, and thus is suitable for field sequential driving.

  Retardation films 1102 and 1105 and polarizing plates 1101 and 1106 are attached to the substrates 1103 and 1104. A liquid crystal material 1107 is sandwiched between the substrates 1103 and 1104. The OCB liquid crystal has a Bend (bowed) alignment structure that is vertically symmetric, and is configured such that the upper layer portion and the lower layer portion of the cell compensate each other. A wide viewing angle can be obtained by combining the retardation films 1102 and 1105 with a hybrid discotic film whose inclination angle changes in accordance with the arrangement of the liquid crystal layers.

  When the vertical / horizontal display switching is performed by the method described in the embodiment, attention is paid to the scanning direction of the first gate signal line driving circuit. In the case of normal display, as shown in FIG. 8A, the first gate signal line driver circuit sequentially selects and scans the gate signal lines from the first row to the n-th row. On the other hand, when the vertical and horizontal directions are switched, as shown in FIG. 8B, the first gate signal line driver circuit reversely turns the gate signal lines from the nth row to the first row in order. Select and scan. Therefore, when switching between vertical and horizontal display, it is necessary to switch the scanning direction of the first gate signal line driving circuit.

FIG. 9 shows a configuration of a driving circuit to which a scanning direction switching circuit is added. A shift register 902, a NAND 904, and a buffer 905 using a plurality of flip-flops 901 are the same as those in the conventional example shown in FIG. When the scanning direction switching signal (UD) and the scanning direction switching inversion signal (UDb) are input to the scanning direction switching circuit 903, the scanning direction switching signal (UD) is H, and the scanning direction switching inversion signal (UDb) is L. The gate signal lines are selected in the order of G ₁ , G ₂ ,..., G _n , and the scanning direction switching signal (UD) is L.
When the scanning direction switching inversion signal (UDb) is H, the selection of the gate signal line is in the order of G _n , G _n−1 ,... G ₁ .

  In carrying out the present invention, the configuration of the drive circuit is not limited to the configurations of FIG. 6, FIG. 7, FIG. For example, the present invention can be implemented even when a decoder is used instead of the shift register.

  In this example, an example in which the vertical / horizontal display is easily switched by a method different from the embodiment will be described.

  FIG. 12A illustrates the structure of the display device. A pixel portion 1206 is formed over a substrate 1200, and further, a first source signal line driver circuit 1202, a first gate signal line driver circuit 1203, a second source signal line driver circuit 1204, and a second gate signal line driver circuit. 1205 is formed. Here, the scanning direction of the first source signal line driver circuit and the scanning direction of the second source signal line driver circuit are perpendicular to each other. The scanning direction of the first gate signal line driving circuit and the scanning direction of the second gate signal line driving circuit are perpendicular to each other.

  In the pixel portion 1206, a portion indicated by 1201 is one pixel, and its structure is shown in FIG. One pixel includes a first source signal line 1211, a first gate signal line 1212, a second source signal line 1213, a second gate signal line 1214, a first pixel TFT 1215, a second pixel TFT 1216, a liquid crystal element 1217, a storage capacitor 1218, and a counter electrode 1219.

  In the case of this embodiment, since there are two source signal lines, two gate signal lines, and two pixel TFTs, there are two independent paths for writing video signals to the liquid crystal element. When performing the first display, that is, the normal display, for example, the first pixel TFT is controlled by operating the first source signal line driver circuit and the first gate signal line driver circuit, and the first source signal line driver circuit is operated. A video signal input to the signal line 1211 is written to the pixel. At this time, neither the second source signal line driver circuit nor the second gate signal line driver circuit is operated.

  On the other hand, when switching the second display, that is, the vertical and horizontal directions of the screen, the second pixel TFT is controlled by operating the second source signal line driving circuit and the second gate signal line driving circuit, The video signal input to the source signal line 1213 is written into the pixel. At this time, neither the first source signal line driver circuit nor the first gate signal line driver circuit is operated.

  In this way, by controlling one pixel by alternately using two sets of drive circuits, it is possible to easily switch between vertical and horizontal display.

  In a display device with a high resolution and a large screen, it is necessary to drive more pixels within a certain period. In the conventional driving method, the driving frequency is high, and therefore, split driving is often employed.

  FIG. 14 shows a configuration example of a source signal line driver circuit in the case of performing division driving, which includes a shift register 1402 using a plurality of flip-flops 1401, a NAND 1403, a buffer 1404, a sampling switch 1405, and the like.

  The circuit shown in FIG. 6 writes video signals to one pixel at a time by one sampling pulse, whereas the circuit shown in FIG. 14 inputs four video signals in parallel. The video signal is written to four pixels at a time by one sampling pulse. In this way, the driving frequency of the source signal line driving circuit can be suppressed to (1 / dividing number) as compared with a conventional display device having the same number of pixels. In the case of FIG. 14, since four-point simultaneous sampling is performed, the number of divisions is four, and the drive frequency of the source signal line driver circuit can be suppressed to ¼.

  In the present embodiment, a method of switching between vertical and horizontal display in a display device that performs such divided driving will be described.

  Refer to FIG. FIG. 15A illustrates a writing order in normal display of a display device including a source signal line driver circuit that performs quadrant driving. Four video signal lines are simultaneously sampled for four pixels, and written to the four pixels (1, 1) (2, 1) (3, 1) (4, 1) simultaneously with the first sampling pulse. Subsequently, the data is simultaneously written in the four pixels (5, 1) (6, 1) (7, 1) (8, 1) by the next sampling pulse.

  Therefore, the input order of the video signals input to the video signal lines (Video 1 to Video 4) is as shown in FIG.

  FIG. 15B shows a writing order when the display device shown in FIG. 15A is switched between vertical and horizontal display. In normal display, simultaneous sampling is performed at four points arranged in the horizontal direction, whereas when vertical and horizontal are switched, simultaneous sampling is performed at four points arranged in the vertical direction.

  In the case of normal display, the first pixels simultaneously written are (1, 1) (2, 1) (3, 1) (4, 1). The pixels to be written are four pixels (1, n) (2, n) (3, n) (4, n).

  At this time, the video signals to be written to these four pixels are video signals to be written to the four pixels (1, 1) (1, 2) (1, 3) (1, 4) in the case of normal display. .

  Therefore, when switching between vertical and horizontal displays, the input order of the video signals input to the video signal lines (Video 1 to Video 4) is as shown in FIG.

  In this case, since a procedure for rearranging video signals for four horizontal cycles is required, a memory for storing video signals for four horizontal cycles is required. However, a frame memory is required as in the conventional case. Even in comparison, the storage capacity is extremely small.

  As described above, the present invention can be implemented also in a display device that performs division driving.

  In this embodiment, a method for simultaneously manufacturing a pixel portion and TFTs of a driver circuit (n-channel TFT and p-channel TFT) provided around the pixel portion on the same substrate will be described in detail.

  Refer to FIG. First, a base insulating film 5002 is formed over a substrate 5001 to obtain a first semiconductor film having a crystal structure, and then etching processing into a desired shape is performed to form semiconductor layers 5003 to 5006 separated into island shapes. .

In this embodiment, a glass substrate (# 1737 substrate) is used as the substrate 5001, and the base insulating film 5002 is formed by a plasma CVD method at a film formation temperature of 400 ° C., source gases SiH ₄ , N
A silicon oxynitride film 5002a (composition ratio Si = 32%, O = 27%, N = 24%, H = 17%) formed from H ₃ and N ₂ O is formed to a thickness of 50 nm (preferably 10 to 200 nm). Next, after cleaning the surface with ozone water, the oxide film on the surface is removed with dilute hydrofluoric acid (1/100 dilution). Then film formation temperature 400 ° C. by a plasma CVD method, a raw material gas SiH _4, N ₂ O hydrogenated silicon oxynitride film made from 5002b (composition ratio Si = 32%, O = 59 %, N = 7%, H = 2%) to a thickness of 100 nm (preferably 50 to 200 nm), and a semiconductor film having an amorphous structure with a film forming temperature of 300 ° C. and a film forming gas of SiH ₄ by plasma CVD without being released to the atmosphere. (Here, an amorphous silicon film) is formed with a thickness of 54 nm (preferably 25 to 80 nm).

Although the base film insulating film 5002 is shown as a two-layer structure in this embodiment, the base film insulating film 5002 may be formed as a single-layer film or a structure in which three or more layers are stacked. The material of the semiconductor film is not limited, but preferably, silicon or silicon germanium (Si _x Ge _1-x (X = 0.0001 to 0.02)) alloy or the like is used, and known means (sputtering method, LPCVD) Or a plasma CVD method or the like). The plasma CVD apparatus may be a single wafer type apparatus or a batch type apparatus. Alternatively, the base insulating film and the semiconductor film may be successively formed without being exposed to the air in the same film formation chamber.

Next, after cleaning the surface of the semiconductor film having an amorphous structure, a very thin oxide film (not shown) of about 2 nm is formed on the surface with ozone water. Next, a small amount of impurity element (boron or phosphorus) is doped in order to control the threshold value of the TFT. Here, diborane (B ₂
An ion doping method in which H ₆ ) is plasma-excited without mass separation is used, the doping condition is an acceleration voltage of 15 kV, diborane is diluted to 1% with hydrogen, a gas flow rate of 30 sccm, and a dose of 2 × 10 ¹² atoms / cm ² . Boron is added to the quality silicon film.

  Next, a nickel acetate solution containing 10 ppm of nickel in terms of weight is applied by a spinner. Instead of coating, a method of spreading nickel element over the entire surface by sputtering may be used.

  Next, heat treatment is performed for crystallization, so that a semiconductor film having a crystal structure is formed. For this heat treatment, heat treatment in an electric furnace or irradiation with strong light may be used. When the heat treatment is performed in an electric furnace, the heat treatment may be performed at 500 ° C. to 650 ° C. for 4 to 24 hours. Here, after heat treatment for dehydrogenation (500 ° C., 1 hour), heat treatment for crystallization (550 ° C., 4 hours) is performed to obtain a silicon film having a crystal structure. Note that although crystallization is performed here using heat treatment using a furnace, crystallization may be performed using a lamp annealing apparatus. Although a crystallization technique using nickel as a metal element for promoting crystallization of silicon is used here, other known crystallization techniques such as a solid phase growth method and a laser crystallization method may be used.

Next, after removing the oxide film on the surface of the silicon film having a crystal structure with dilute hydrofluoric acid or the like, a first laser beam (XeCl: wavelength 308 nm) for increasing the crystallization rate and repairing defects left in the crystal grains ) Is performed in the air or in an oxygen atmosphere. As the laser light, excimer laser light with a wavelength of 400 nm or less, second harmonic, third harmonic, or CW laser of YAG laser is used. In any case, a pulsed laser beam having a repetition frequency of about 10 to 1000 Hz is used, and the laser beam is condensed to 100 to 500 mJ / cm ² by an optical system.
Irradiation with an overlap rate of 0 to 95% may be performed to scan the surface of the silicon film. Here, irradiation with the first laser light is performed in the atmosphere at a repetition frequency of 30 Hz and an energy density of 393 mJ / cm ² . Note that an oxide film is formed on the surface by irradiation with the first laser light because it is performed in the air or in an oxygen atmosphere.

Next, after removing the oxide film formed by irradiation with the first laser beam with dilute hydrofluoric acid, irradiation with the second laser beam is performed in a nitrogen atmosphere or in a vacuum to flatten the surface of the semiconductor film. As this laser light (second laser light), excimer laser light with a wavelength of 400 nm or less, second harmonic, third harmonic, or CW laser of YAG laser is used. The energy density of the second laser light is made larger (preferably 30 to 60 mJ / cm ² larger) than the energy density of the first laser light. Here, the second laser beam is irradiated at a repetition frequency of 30 Hz and an energy density of 453 mJ / cm ² , and the unevenness P on the semiconductor film surface is detected.
-V value is 5 nm or less.

  In this embodiment, the second laser beam is irradiated on the entire surface. However, since the reduction of the off-current is particularly effective for the TFT in the pixel portion, it is possible to selectively irradiate at least the pixel portion. Good. Moreover, the process by only one laser irradiation may be sufficient.

  Next, the surface is treated with ozone water for 120 seconds to form a barrier layer (not shown) made of an oxide film having a total thickness of 1 to 5 nm.

Next, an amorphous silicon film containing an argon element serving as a gettering site is formed with a thickness of 150 nm on the barrier layer by a sputtering method. The film forming conditions by the sputtering method of this embodiment are as follows: the film forming pressure is 0.3 Pa, the gas (Ar) flow rate is 50 sccm, the film forming power is 3 kW, and the substrate temperature is 150 ° C. Note that the atomic concentration of the argon element contained in the amorphous silicon film under the above conditions is 3 × 10 ^{20 to} 6 × 10 ²⁰ atoms / cm ³ , and the atomic concentration of oxygen is 1 × 10 ^{19 to} 3 × 10 ¹⁹ atoms. / Cm ³ . Thereafter, heat treatment is performed at 650 ° C. for 3 minutes using a lamp annealing apparatus to perform gettering.

  Next, the amorphous silicon film containing an argon element as a gettering site is selectively removed using the barrier layer as an etching stopper, and then the barrier layer is selectively removed with dilute hydrofluoric acid. Note that during gettering, nickel tends to move to a region with a high oxygen concentration, and thus it is desirable to remove the barrier layer made of an oxide film after gettering.

  Next, after forming a thin oxide film with ozone water on the surface of the obtained silicon film having a crystal structure (also called a polysilicon film), a mask made of resist is formed and etched into a desired shape to form islands. The separated semiconductor layers 5003 to 5006 are formed. After the semiconductor layer is formed, the resist mask is removed.

  Next, the oxide film is removed with an etchant containing hydrofluoric acid, and at the same time, the surface of the silicon film is washed, and then an insulating film containing silicon as a main component to be the gate insulating film 5007 is formed. In this embodiment, a silicon oxynitride film (composition ratio: Si = 32%, O = 59%, N = 7%, H = 2%) is formed to a thickness of 115 nm by plasma CVD.

  Next, a first conductive film 5008 with a thickness of 20 to 100 nm and a second conductive film 5009 with a thickness of 100 to 400 nm are stacked over the gate insulating film 5007. In this embodiment, a tantalum nitride (TaN) film having a thickness of 50 nm and a tungsten (W) film having a thickness of 370 nm are sequentially stacked over the gate insulating film 5007 (FIG. 16A).

The conductive material for forming the first conductive film and the second conductive film is an element selected from Ta, W, Ti, Mo, Al, and Cu, or an alloy material or a compound material containing the element as a main component. Form. Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus, or an AgPdCu alloy may be used as the first conductive film and the second conductive film. Further, the present invention is not limited to the two-layer structure. For example, a three-layer structure in which a 50 nm-thickness tungsten film, a 500 nm-thickness aluminum and silicon alloy (Al-Si) film, and a 30 nm-thickness titanium nitride film are sequentially stacked. Also good. In the case of a three-layer structure, tungsten nitride may be used instead of tungsten of the first conductive film, or aluminum instead of the aluminum and silicon alloy (Al-Si) film of the second conductive film. A titanium alloy film (Al—Ti) may be used, or a titanium film may be used instead of the titanium nitride film of the third conductive film. Moreover, a single layer structure may be sufficient.
Next, as shown in FIG. 16B, a resist mask 5010 is formed by a light exposure step, and a first etching process is performed to form gate electrodes and wirings. The first etching process is performed under the first and second etching conditions. For etching, an ICP (Inductively Coupled Plasma) etching method may be used. Using the ICP etching method, the film is formed into a desired taper shape by appropriately adjusting the etching conditions (the amount of power applied to the coil-type electrode, the amount of power applied to the substrate-side electrode, the electrode temperature on the substrate side, etc.) Can be etched. As an etching _{gas, Cl 2, BCl 3, SiCl} 4, CCl 4 chlorine gas or CF ₄ to the typified like, SF _6, fluorine-based gas NF ₃ and the like typified, or O ₂ as appropriate Can be used.

In this embodiment, 150 W of RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. The W film is etched under this first etching condition so that the end portion of the first conductive layer is tapered. Under the first etching conditions, the etching rate with respect to W is 200.39 nm / min, the etching rate with respect to TaN is 80.32 nm / min, and the selection ratio of W with respect to TaN is about 2.5. Further, the taper angle of W is about 26 ° under this first etching condition. Thereafter, the second etching condition is changed without removing the resist mask 5010, CF ₄ and Cl ₂ are used as etching gases, the gas flow ratio is 30/30 sccm, and the pressure is 1.0 Pa. Then, 500 W RF (13.56 MHz) power was applied to the coil-type electrode to generate plasma, and etching was performed for about 30 seconds. 20 W RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. In the second etching conditions using the gas mixture of CF ₄ and Cl ₂ are etched to the same extent, the W film and the TaN film. The etching rate for W under the second etching conditions is 58.97 nm / min, and the etching rate for TaN is 66.43 nm / min. Note that in order to perform etching without leaving a residue on the gate insulating film, it is preferable to increase the etching time at a rate of about 10 to 20%.

  In the first etching process, the shape of the mask made of resist is made suitable, and the end portions of the first conductive layer and the second conductive layer are tapered due to the effect of the bias voltage applied to the substrate side. It becomes. The angle of the tapered portion may be 15 to 45 °.

  Thus, the first shape conductive layers 5011 to 5016 (the first conductive layers 5011a to 5016a and the second conductive layers 5011b to 5016b) formed of the first conductive layer and the second conductive layer by the first etching treatment. Form. In the insulating film 5007 to be a gate insulating film, regions not covered with the first shape conductive layers 5011 to 5016 are etched and thinned by about 10 to 20 nm.

Next, a second etching process is performed without removing the resist mask. Here, SF ₆ , Cl _2, and O ₂ are used as etching gases, and the respective gas flow ratios are set to 24/12.
Etching was performed for 25 seconds by generating plasma by applying 700 W RF (13.56 MHz) power to the coil-type electrode at a pressure of 1.3 Pa at / 24 sccm. 10 W RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. In the second etching process, the etching rate with respect to W is 227.3 nm / min, the etching rate with respect to TaN is 32.1 nm / min, the selection ratio of W with respect to TaN is 7.1, and the gate insulating film 5007 The etching rate with respect to SiON is 33.7 nm / min, and the selection ratio of W with respect to SiON is 6.83. In this way, when SF ₆ is used as the etching gas, the selectivity with respect to the gate insulating film 5007 is high, so that film loss can be suppressed. In this embodiment, the gate insulating film 5007 is reduced only by about 8 nm.

  By this second etching process, the taper angle of W became 70 °. The second shape conductive layers 5017 to 5022 are formed by the second etching process. At this time, the first conductive layer is hardly etched and becomes the first conductive layers 5017a to 5022a. Note that the first conductive layers 5017a to 5022a are approximately the same size as the first conductive layers 5011a to 5016a. Actually, by the second etching process, the width of the first conductive layer may recede by about 0.3 μm as compared with that before the second etching process, that is, the entire line width may recede by about 0.6 μm. There is no change in size.

In place of the two-layer structure, a three-layer structure in which a 50-nm-thick tungsten film, a 500-nm-thick aluminum and silicon alloy (Al-Si) film, and a 30-nm-thick titanium nitride film are sequentially stacked, As the first etching condition of the first etching process, BCl ₃ , Cl _2, and O ₂ are used as source gases, the respective gas flow ratios are set to 65/10/5 sccm, and the substrate side (sample stage) is 300 W. RF (13.56 MHz) power is applied, 450 W RF (13.56 MHz) power is applied to the coiled electrode at a pressure of 1.2 Pa, plasma is generated, and etching is performed for 117 seconds. As the second etching condition of the first etching process, CF ₄ , Cl ₂ and O ₂ are used, and the respective gas flow ratios are set to 25/25 /
10 sccm, 20 W of RF (13.56 MHz) power is also applied to the substrate side (sample stage), and 500 W of RF (13.56 MHz) power is applied to the coil electrode at a pressure of 1.0 Pa to generate plasma. The second etching process may be performed using BCl ₃ and Cl ₂ with a gas flow ratio of 20/60 sccm, and 100 W on the substrate side (sample stage). RF (13.56 MHz) power is applied, and 600 W of RF (13.56 MHz) power is applied to the coil-type electrode at a pressure of 1.2 Pa to generate plasma and perform etching.

Next, after removing the resist mask, a first doping process is performed to obtain the state of FIG. The doping process may be performed by ion doping or ion implantation. The conditions of the ion doping method are a dose amount of 1.5 × 10 ¹⁴ atoms / cm ² and an acceleration voltage of 60 to 100 keV. Typically, phosphorus (P) or arsenic (As) is used as the impurity element imparting n-type conductivity. In this case, the first conductive layer and the second conductive layers 5017 to 5021 serve as a mask for the impurity element imparting n-type conductivity, and the first impurity regions 5023 to 5026 are formed in a self-aligning manner. An impurity element imparting n-type conductivity is added to the first impurity regions 5023 to 5026 in a concentration range of 1 × 10 ¹⁶ to 1 × 10 ¹⁷ atoms / cm ³ . Here, a region having the same concentration range as the first impurity region is also referred to as an n−− region.

  In this embodiment, the first doping process is performed after removing the resist mask, but the first doping process may be performed without removing the resist mask.

Next, as shown in FIG. 17A, a mask 5027 made of resist is formed, and a second doping process is performed. The condition of the ion doping method in the second doping treatment is that the dose is 1.5 × 10 ¹⁵ atoms / cm ² , the acceleration voltage is 60 to 100 keV, and phosphorus (P
). Here, impurity regions are formed in each semiconductor layer in a self-aligned manner using the second conductive layers 5017b to 5021b as masks. Of course, it is not added to the region covered with the mask 5027. Thus, second impurity regions 5028 and 5029 and a third impurity region 5030 are formed. An impurity element imparting n-type conductivity is added to the second impurity regions 5028 and 5029 in a concentration range of 1 × 10 ²⁰ to 1 × 10 ²¹ atoms / cm ³ . Here, a region having the same concentration range as the second impurity region is also referred to as an n ⁺ region.

The third impurity region is formed by the first conductive layer 5017a at a lower concentration than the second impurity region, and imparts n-type in a concentration range of 1 × 10 ¹⁸ to 1 × 10 ¹⁹ atoms / cm ^3. Impurity elements are added. Note that the third impurity region has a concentration gradient in which the impurity concentration increases toward the end of the tapered portion because doping is performed by passing the portion of the first conductive layer 5017a having a tapered shape. Yes. Here, a region having the same concentration range as the third impurity region is also referred to as an n ⁻ region. An area 5031 covered with the mask 5027 is
The impurity element is not added in the second doping treatment, and the first impurity region is left as it is.

Next, after removing the resist mask 5027, a resist mask 5032 is newly formed, and a third doping process is performed as shown in FIG.
In the driver circuit, a fourth impurity region 5033 in which an impurity element imparting P-type conductivity is added to the semiconductor layer forming the P-channel TFT and the semiconductor layer forming the storage capacitor by the third doping process. , 5034 and fifth impurity regions 5035, 5036 are formed.
Further, an impurity element imparting p-type conductivity is added to the fourth impurity regions 5033 and 5034 in a concentration range of 1 × 10 ²⁰ to 1 × 10 ²¹ atoms / cm ³ . The fourth impurity regions 5033 and 5034 are initially regions to which phosphorus (P) is added in the previous step (n−− region), but the concentration of the impurity element imparting P-type is the same. It is added 1.5 to 3 times, and the conductivity type is P type. Here, a region having the same concentration range as the fourth impurity region is also referred to as a P ⁺ region.

The fifth impurity regions 5035 and 5036 are formed in regions overlapping the tapered portions of the second conductive layers 5018b and 5021b, and have a concentration range of 1 × 10 ¹⁸ to 1 × 10 ²⁰ atoms / cm ^3. An impurity element imparting P-type is added. Here, the fifth
A region having the same concentration range as the impurity region is also referred to as a P ⁻ region.

  Through the above steps, an impurity region having N-type or P-type conductivity is formed in each semiconductor layer. The conductive layers 5017 to 5020 serve as TFT gate electrodes. The conductive layer 5021 serves as one electrode forming a storage capacitor in the pixel portion. Further, the conductive layer 5022 forms a source signal line in the pixel portion.

  Next, an insulating film (not shown) that covers almost the entire surface is formed. In this example, a 50 nm-thickness silicon oxide film was formed by plasma CVD. Of course, this insulating film is not limited to the silicon oxide film, and another insulating film containing silicon may be used as a single layer or a laminated structure.

  Next, a step of activating the impurity element added to each semiconductor layer is performed. This activation step may be a rapid thermal annealing method (RTA method) using a lamp light source, a method of irradiating a YAG laser or an excimer laser from the back surface, a heat treatment using a furnace, or a combination thereof. By different methods.

  Further, in this embodiment, an example in which an insulating film is formed before the activation is shown, but an insulating film may be formed after the activation.

  Next, a first interlayer insulating film 5037 made of a silicon nitride film is formed and subjected to heat treatment (heat treatment at 300 to 550 ° C. for 1 to 12 hours) to hydrogenate the semiconductor layer (FIG. 17C). ). This step is a step of terminating dangling bonds in the semiconductor layer with hydrogen contained in the first interlayer insulating film 5037. The semiconductor layer can be hydrogenated regardless of the presence of an insulating film (not shown) made of a silicon oxide film.

Next, a second interlayer insulating film 5038 made of an organic insulating material is formed over the first interlayer insulating film 5037. In this embodiment, an acrylic resin film having a thickness of 1.6 μm is formed. Next, contact holes reaching the respective electrodes or impurity regions are opened. In this embodiment, a plurality of etching processes are sequentially performed. In this embodiment, the second interlayer insulating film 5038 is etched using the first interlayer insulating film 5037 as an etching stopper, and then the first interlayer insulating film 5037 is etched using the insulating film (not shown) as an etching stopper. The film (not shown) is etched.
Thereafter, wirings and pixel electrodes are formed using Al, Ti, Mo, W, or the like. As the material of these electrodes and pixel electrodes, it is desirable to use a material having excellent reflectivity such as a film containing Al or Ag as a main component or a laminated film thereof. Thus, wirings 5039 to 5042, a pixel electrode 5043, and a gate signal line 5044 are formed.

  As described above, a driver circuit having an N-channel TFT and a P-channel TFT, a pixel TFT having an N-channel TFT, and a pixel portion having a storage capacitor can be formed over the same substrate (FIG. 17 (D)). In this specification, such a substrate is referred to as an active matrix substrate for convenience.

  In the active matrix substrate shown in FIG. 17D, the N-channel TFT has two types of structures. One is a GOLD structure having a third impurity region overlapping with the gate electrode as seen in the N-channel TFT of the driving circuit, and the other is the first not overlapping with the gate electrode as seen in the pixel TFT. This is an LDD structure having one impurity region.

  The former is a structure effective for suppressing hot carrier deterioration and the like, and is particularly suitable for a place where reliability is required for operation. The latter is a structure effective for reducing off-current leakage, and is suitable for a circuit where a negative bias voltage is frequently applied, a circuit for controlling a pixel portion, and the like.

  On the other hand, a counter substrate 5045 is prepared. A counter electrode 5046 made of a transparent conductive film is formed on the counter substrate side.

  Subsequently, alignment films 5047 and 5048 are formed on the active matrix substrate and the counter substrate, respectively, and a rubbing process is performed. In this embodiment, before forming the alignment film 5048 on the active matrix substrate side, a columnar spacer (not shown) for securing a space between the substrates using an organic resin film such as an acrylic resin is used. Formed in the desired position. Further, instead of the columnar spacers, spherical spacers may be scattered over the entire surface of the substrate.

  Then, the active matrix substrate on which the pixel portion and the driving circuit are formed and the counter substrate are bonded together with a sealant (not shown). A filler is mixed in the sealing material, and two substrates are bonded together with a uniform gap by the filler and the columnar spacer. Thereafter, a liquid crystal material 5049 is injected into the gap between the two substrates and completely sealed with a sealing material (not shown). A known liquid crystal material may be used for the liquid crystal material 5049. If necessary, the active matrix substrate or the counter substrate is divided into a desired shape. Furthermore, a polarizing plate or the like was appropriately provided using a known technique. Then, the FPC is pasted using a known technique. Thus, the active matrix type liquid crystal display device shown in FIG. 18 is completed.

  A liquid crystal display device shown in FIG. 22A includes a printed circuit board 46, a controller 11, a central processing unit (CPU) 12, a memory 21, a power supply circuit 13, an audio processing circuit 39, a transmission / reception circuit 14, and other resistors, Elements such as a buffer and a capacitor are mounted. The liquid crystal panel 10 is connected to a printed wiring board 46 via a flexible wiring board (FPC) 18.

  The liquid crystal panel 10 includes a source signal line drive circuit 17, a first gate signal line drive circuit 16a ", and a second gate signal line drive circuit 16b. The scanning direction of the second gate signal line driving circuit is orthogonal to the scanning direction of the first gate signal line driving circuit. This configuration is the same as that in FIG. Since the liquid crystal panel 10 performs field sequential driving, it is not necessary to separate the pixels in the pixel unit 15 into RGB. Accordingly, the number of necessary signal lines can be reduced, and the aperture ratio can be dramatically increased.

  Various control signals are input and output through an interface (I / F) 19 provided on the printed wiring board 46. An antenna port 20 for transmitting and receiving signals to and from the antenna is provided on the printed wiring board 46.

  In this embodiment, the printed wiring board 46 is connected to the liquid crystal panel 10 via the FPC 18, but the present invention is not necessarily limited to this configuration. The controller 11, the audio processing circuit 39, the memory 21, the CPU 12, or the power supply circuit 13 may be directly mounted on the liquid crystal panel 10 using a COG (Chip on Glass) method. The printed wiring board 46 is provided with various elements such as a capacitive element and a buffer to prevent noise from being applied to the power supply voltage and the signal and the rise of the signal from being slowed down.

  FIG. 22B is a block diagram of the liquid crystal display device illustrated in FIG. The liquid crystal display device includes a VRAM 42, a DRAM 35, a flash memory 36, and the like as the memory 21. The VRAM 42 stores image data to be displayed on the panel, the DRAM 35 stores image data or audio data, and the flash memory stores various programs.

  In the power supply circuit 13, a power supply voltage to be supplied to the liquid crystal panel 10, the controller 11, the CPU 12, the sound processing circuit 39, the memory 21, and the transmission / reception circuit 14 is generated. Depending on the panel specifications, the power supply circuit 13 may be provided with a current source.

  The CPU 12 includes a control signal generation circuit 30, a decoder 31, a register 32, an arithmetic circuit 33, a RAM 34, a CPU interface 45, and the like. Various signals input to the CPU 12 via the interface 45 are once held in the register 32 and then input to the arithmetic circuit 33, the decoder 31, and the like. The arithmetic circuit 33 performs an operation based on the input signal and designates a place to send various commands. On the other hand, the signal input to the decoder 31 is decoded and input to the control signal generation circuit 30. The control signal generation circuit 30 generates a signal including various instructions based on the input signal, and the location specified in the arithmetic circuit 33, specifically, the memory 21, the transmission / reception circuit 14, the sound processing circuit 39, the controller 11, etc. Send to.

  The memory 21, the transmission / reception circuit 14, the sound processing circuit 39, and the controller 11 operate according to the received commands. The operation will be briefly described below.

  A signal input from the input unit 41 is sent to the CPU 12 mounted on the printed wiring board 46 via the interface 19. The control signal generation circuit 30 converts the image data stored in the VRAM 42 into a predetermined format according to a signal sent from the input means 41 such as a pointing device or a keyboard, and sends the image data to the controller 11.

  The controller 11 performs data processing on a signal including image data sent from the CPU 12 according to the specifications of the panel and supplies the processed signal to the liquid crystal panel 10. Further, the controller 11 generates an Hsync signal, a Vsync signal, a clock signal CLK, an AC voltage (AC Cont), and a switching signal L / R based on the power supply voltage input from the power supply circuit 13 and various signals input from the CPU 12. It is generated and supplied to the liquid crystal panel 10.

  In the transmission / reception circuit 14, a signal transmitted / received as a radio wave is processed by the antenna 43, specifically, a high frequency such as an isolator, a band pass filter, a VCO (Voltage Controlled Oscillator), an LPF (Low Pass Filter), a coupler, and a balun Includes circuitry. A signal including audio information among signals transmitted and received in the transmission / reception circuit 14 is sent to the audio processing circuit 39 in accordance with a command from the CPU 12.

  A signal including audio information sent in accordance with an instruction from the CPU 12 is demodulated into an audio signal by the audio processing circuit 39 and sent to the speaker 38. The audio signal sent from the microphone 37 is modulated by the audio processing circuit 39 and sent to the transmission / reception circuit 14 in accordance with a command from the CPU 12.

  The controller 11, the CPU 12, the power supply circuit 13, the sound processing circuit 39, and the memory 21 can be mounted as a package of this embodiment. This embodiment can be applied to any circuit other than a high-frequency circuit such as an isolator, a band pass filter, a VCO (Voltage Controlled Oscillator), an LPF (Low Pass Filter), a coupler, and a balun.

  According to the present embodiment, it is possible to easily switch the screen between vertical and horizontal directions, and it is possible to obtain a liquid crystal display device without complicating the external time.

  FIG. 23 shows one mode of a cellular phone including this liquid crystal display device. The liquid crystal panel 10 is detachably incorporated in the housing 51 so that it can be easily integrated with the liquid crystal display device. The shape and size of the housing 51 can be changed as appropriate in accordance with the electronic device to be incorporated.

  The liquid crystal panel 10 that is field-sequentially driven is combined with a light emission source 50 that periodically changes its emission color. The light emitting source 50 is composed of a light emitting diode and a light emitting diode having a different emission color. Further, an organic EL element, an inorganic EL element, or a composite EL element using a synergistic effect of an organic material and an inorganic material may be used as the light source of the light emission source 50. A housing 51 to which the liquid crystal panel 10 and the light source 50 are fixed is fitted to the printed wiring board 46 and assembled as a module.

  On the printed wiring board 46, a controller, a CPU, a memory, a power supply circuit, and other elements such as a resistor, a buffer, and a capacitive element are mounted. Furthermore, an audio processing circuit, a transmission / reception circuit, or the like may be mounted depending on the application. The liquid crystal panel 10 is connected to the printed wiring board 46 via the FPC 18.

  Such a liquid crystal display device, the input means 41, and the battery 53 are accommodated in a housing 52. The pixel portion of the liquid crystal panel 10 is disposed so as to be visible from an opening window formed in the housing 52.

  Since the liquid crystal panel 10 performs field sequential driving, it is not necessary to separate the pixels in the pixel portion into RGB. Accordingly, the number of necessary signal lines can be reduced, and the aperture ratio can be dramatically increased. In addition, since the color filter can be omitted, it contributes to weight reduction and thickness reduction of the mobile phone. In addition, since the display orientation can be switched between vertical and horizontal, the outer shape of the housing 52 can be designed freely. In other words, FIG. 23 shows an example of the external shape of a mobile phone, but the electronic device including a liquid crystal display device can have various modes.

  As described in Embodiment 5, the present invention can be applied to manufacture of display devices used in various electronic devices. Examples of such an electronic device include a display device, a portable information terminal (electronic notebook, mobile computer, etc.), a mobile phone, and the like. An example of them is shown in FIG.

  FIG. 13A illustrates a liquid crystal display, which includes a housing 3001, a support base 3002, a display portion 3003, and the like. The present invention can be applied to the display portion 3003. In addition, in the case of switching between vertical and horizontal display in such a desktop-mounted display, it is preferable that a rotation mechanism is provided in an attachment portion of the housing 3001 to the support base 3002 so that the housing 3001 itself can be rotated.

  FIG. 13B illustrates a portable information terminal, which includes a main body 3031, a stylus 3032, a display portion 3033, operation buttons 3034, an external interface 3035, and the like. The present invention can be applied to the display portion 3033. This portable information terminal can easily switch between vertical and horizontal images according to the content displayed on the screen, and can display images with high image quality.

  FIG. 13C illustrates a mobile phone, which includes a main body (A) 3061a including a voice input portion 3063, operation buttons 3065, and the like (B) including a display portion 3064, a voice output portion 3062, an antenna 3066, and the like. ) 3061b. The present invention can be applied to the display portion 3064. This mobile phone can easily switch between vertical and horizontal images according to the content displayed on the screen, and can display images with high image quality. For example, as shown in FIGS. 24A and 24B, when a rotation mechanism is provided in the hinge portion 3067 that connects the main body (A) 3061a and the main body (B) 3061b, the main body (B) 3061b itself can be rotated. good. It can be conveniently used when an image pickup device such as a CCD and a lens are provided in the hinge portion 3067 and a camera is incorporated. As shown in FIG. 24B, by rotating the main body (B) 3061b and switching the image display of the display portion 3064 vertically and horizontally, the image can be visually recognized on the display portion 3064 while being imaged.

  It should be noted that the examples shown in the present embodiment are only examples and are not limited to these applications.

The figure which shows one Embodiment of this invention. The figure which shows the outline | summary of the display apparatus used conventionally. The figure explaining the mode of switching of a vertical / horizontal display. The figure which shows the flow of a process in the case of using a frame memory for switching of a vertical / horizontal display, and format conversion. 4A and 4B illustrate timing when a display device is driven. FIG. 6 is a diagram illustrating a configuration and a timing chart of a source signal line driver circuit. FIG. 4 is a diagram illustrating a configuration and a timing chart of a gate signal line driver circuit. The figure explaining the order of writing video signals in normal display and vertical / horizontal switching display. FIG. 6 is a diagram showing a configuration of a gate signal line driver circuit having a scanning direction switching circuit. The figure explaining the timing at the time of driving a display apparatus, when a vertical / horizontal display is switched. The figure which shows the structure of OCB liquid crystal. 1 is a diagram showing a configuration of a display device having two independent drive circuits according to an embodiment of the present invention. FIG. 11 illustrates an example of an electronic device to which the present invention can be applied. The figure which shows the structure of the source signal line drive circuit in the case of performing a division drive. The figure explaining the display order in the case of implementing this invention in the display apparatus which performs a division drive, and the input order of a video signal. 4A and 4B illustrate an example of a manufacturing process of an active matrix liquid crystal display device. 4A and 4B illustrate an example of a manufacturing process of an active matrix liquid crystal display device. 4A and 4B illustrate an example of a manufacturing process of an active matrix liquid crystal display device. The figure which shows the pixel when not using a field sequential. The figure which shows the pixel at the time of using a field sequential. The figure which shows the timing of a field sequential. FIG. 6 illustrates one embodiment of a liquid crystal display device. FIG. 14 illustrates one embodiment of a mobile phone including a liquid crystal display device. FIG. 6 illustrates one embodiment of a mobile phone.

Explanation of symbols

100 Substrate 101 Pixel 102 Source signal line driver circuit 103 First gate signal line driver circuit 104 Second gate signal line driver circuit 105 Pixel unit 111 Source signal line 112 Gate signal line 113 Gate signal line 114 Pixel TFT
115 pixel TFT
116 Liquid crystal element 117 Retention capacitor 118 Counter electrode

Claims (15)

A light emitting source whose emission color periodically changes, a source signal line driving circuit, a first gate signal line driving circuit, a second gate signal line driving circuit, and a plurality of pixels;
A display device capable of first display and second display, wherein a scanning direction of the first gate signal line driving circuit and a scanning direction of the second gate signal line driving circuit are orthogonal to each other. A light emitting source whose emission color periodically changes, a source signal line driving circuit, a first gate signal line driving circuit, a second gate signal line driving circuit, and a plurality of pixels;
The plurality of pixels include a source signal line, a first gate signal line, a second gate signal line orthogonal to the first gate signal line, a first transistor, and a second transistor. And
The gate electrode of the first transistor is electrically connected to the first gate signal line, the input electrode of the first transistor is electrically connected to the source signal line, and the first transistor The output electrode of the second transistor is electrically connected to the input electrode of the second transistor,
A display device capable of a first display and a second display, wherein a gate electrode of the second transistor is electrically connected to the second gate signal line. In claim 1 or claim 2,
When performing the first display, the driving frequency of the source signal line driving circuit is higher than the driving frequency of the first gate signal line driving circuit,
When performing the second display, the driving frequency of the source signal line driver circuit is lower than the driving frequency of the first gate signal line driver circuit. Possible display device. In any one of Claims 1 thru | or 3,
At least one of the source signal line driver circuit, the first gate signal line driver circuit, and the second gate signal line driver circuit, and the plurality of pixels are formed over the same substrate. A display device capable of displaying 1 and second display. A light emitting source whose emission color periodically changes, a first source signal line driving circuit, a second source signal line driving circuit, a first gate signal line driving circuit, and a second gate signal line driving circuit And a plurality of pixels,
A display device capable of a first display and a second display, wherein a scanning direction of the first gate signal line driving circuit and a scanning direction of the second gate signal line driving circuit are orthogonal to each other. A light emitting source whose emission color periodically changes, a first source signal line driving circuit, a second source signal line driving circuit, a first gate signal line driving circuit, and a second gate signal line driving circuit And a plurality of pixels,
The plurality of pixels include a first source signal line, a second source signal line, a first gate signal line, a second gate signal line orthogonal to the first gate signal line, and a first And a second transistor,
A gate electrode of the first transistor is electrically connected to the first gate signal line; an input electrode of the first transistor is electrically connected to the first source signal line;
The gate electrode of the second transistor is electrically connected to the second gate signal line, and the input electrode of the second transistor is electrically connected to the second source signal line. A display device capable of performing a first display and a second display as features. In claim 5 or claim 6,
The plurality of pixels are the same as at least one of the first source signal line driver circuit, the second source signal line driver circuit, the first gate signal line driver circuit, and the second gate signal line driver circuit. A display device capable of first display and second display, wherein the display device is formed on a substrate. In any one of Claims 1 thru | or 7,
When performing the first display, the top and bottom of the video are displayed in an orientation according to the scanning direction of the first gate signal line driving circuit,
When performing the second display, the top and bottom of the video are displayed in the direction according to the scanning direction of the second gate signal line driving circuit, and the first display and the second display are possible. Display device. In any one of Claims 1 thru | or 8,
Each of the plurality of pixels includes a liquid crystal element, and a display device capable of a first display and a second display.   An electronic apparatus using the display device according to any one of claims 1 to 9. A source signal line driver circuit, a first gate signal line driver circuit, a second gate signal line driver circuit, and a plurality of pixels;
The scanning direction of the first gate signal line driving circuit and the scanning direction of the second gate signal line driving circuit are orthogonal to each other,
The method for driving a display device capable of performing a first display and a second display, wherein the plurality of pixels are driven in a field sequential manner. In claim 11,
When performing the first display, the driving frequency of the source signal line driving circuit is higher than the driving frequency of the first gate signal line driving circuit,
When performing the second display, the driving frequency of the source signal line driver circuit is lower than the driving frequency of the first gate signal line driver circuit. Possible display device driving method. A first source signal line driver circuit, a second source signal line driver circuit, a first gate signal line driver circuit, a second gate signal line driver circuit, and a plurality of pixels;
The scanning direction of the first gate signal line driving circuit and the scanning direction of the second gate signal line driving circuit are orthogonal to each other,
The method for driving a display device capable of first display and second display, wherein the plurality of pixels are field-sequentially driven. In any one of Claims 11 thru | or 13,
When performing the first display, the top and bottom of the video are displayed in an orientation according to the scanning direction of the first gate signal line driving circuit,
When performing the second display, the top and bottom of the video are displayed in the direction according to the scanning direction of the second gate signal line driving circuit, and the first display and the second display are possible. Drive method for a simple display device. An electronic apparatus using the method for driving a display device according to any one of claims 11 to 14.

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