JP2006129330A - Frequency synthesizer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a frequency synthesizer not causing a problem of a filter while solving a problem of phase noise by employing a frequency offset type. <P>SOLUTION: An image rejection mixer 10 that offsets an oscillation frequency of a voltage controlled oscillator 1, is connected to the voltage controlled oscillator 1, and a frequency of an output signal of that image rejection mixer 10 is divided by a frequency divider 3, 4 and supplied to a phase comparator 8. Whereas, a reference signal generator 6 is provided to generate a reference frequency, and the output signal of the reference signal generator 6 or a reference signal of a phase comparison frequency fψ resulting from dividing the frequency of the above output signal is supplied to the phase comparator 8. In the phase comparator 8, a phase difference between the signal supplied from the frequency divider 3, 4 and the reference signal fψ is then detected and based on the phase difference, a control voltage is supplied to the voltage controlled oscillator 1. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a PLL (Phase Locked Loop) frequency synthesizer. More specifically, the present invention relates to a PLL type frequency synthesizer that can realize low phase noise at any frequency.

  A conventional frequency synthesizer has a configuration as shown in FIG. 4 (see, for example, Patent Document 1). That is, in FIG. 4, a part of an output oscillated from a voltage controlled oscillator (hereinafter also referred to as VCO) 1 is branched and divided by a modulus prescaler 3 of 1 / M, 1 / (M + 1). Further, it is sent to a programmable 1 / N programmable frequency divider 4 for frequency division. An A counter 5 is connected to the modulus prescaler 3 and the programmable frequency divider 4 so that the count number from the A counter 5 is added. As a result, 1 / (M · N + A) of the oscillation frequency of the VCO. Are output to the phase comparator (PFD) 8.

  On the other hand, the reference signal generator 6 is an oscillator having a stable reference frequency fr such as a crystal oscillator, and the oscillation frequency is divided by a 1 / Nr frequency divider 7 to obtain a phase as a signal having a phase comparison frequency fφ. Input to the comparator 8. The phase comparator 8 checks whether or not the phases of both signals match. If they do not match, the difference is converted into a voltage and fed back to the VCO 1 so that the phases completely match. The voltage of VCO1 is controlled. A loop filter (L / F) 9 is connected to the output side of the phase comparator 8 so as to remove harmonic components generated by the phase comparator 8 and to determine the response characteristics and steady-state characteristics of the system. Yes. Then, an oscillation output having a predetermined frequency fo is supplied from the VCO 1. With this configuration, the output frequency fo is expressed by the following equation (1).

fo = (M · N + A) · fφ (1)
Here, if fo / fφ is a multiplication number No, No must be an integer. This is because, in many cases, the synthesizer has a function to vary the frequency stepwise, so that N and A shown in the equation (1) are programmable, and fo is changed to an integral multiple of fφ. . Therefore, the absolute frequency fo of the output is an integral multiple of the frequency step size (relative frequency) and the multiplication number (No). Therefore, when fo needs a fine numerical frequency such as 2617.5 MHz, it cannot be made an integral multiple unless the frequency below the minimum unit of fo such as 0.5 MHz is set to fφ. .

  On the other hand, in such a frequency synthesizer, it is known that the phase noise characteristic deteriorates when the multiplication number No is large, that is, when fφ is small. That is, it is known that the synthesizer phase noise is generally obtained by adding 20 · log (No) (common logarithm value) to the noise of the reference signal generator 6 or the floor noise of the phase comparator 8. .

  For example, when the output frequency fo is 2617.5 MHz, fφ is 0.5 MHz, and No is 2617.5 ÷ 0.5 = 5235. In this case, the frequency step size is fφ. Further, since the noise of the reference signal source is 1 kHz and −154 dBc / Hz, the phase noise characteristic in the band is −154 + 20 · log 5235 = −80 (dBc / Hz). On the other hand, the measurement result of the phase noise characteristic at this time is as shown in FIG. That is, the measured value of the phase noise characteristic and the calculated value are almost the same.

As a modification of the structure shown in FIG. 4, as shown in FIG. 5, a mixer 21 and a band pass filter BPF 22 are connected in front of the modulus prescaler 3, and the mixer 21 outputs the VCO 1 output and the offset frequency fos. There is known a frequency offset type synthesizer in which the oscillation frequency of the VCO 1 is shifted by the offset frequency fos by mixing with the output of. With this configuration, by offsetting the fractional frequency of the oscillation frequency fo as the offset frequency fos, the phase comparison frequency fφ (step size frequency) can be increased, and the multiplication number No can be decreased. However, the filter 22 is necessary to remove the spurious generated in the mixer 21, but if (fo-fos) is close to fo, the configuration of the filter 22 becomes difficult. That is, in order to increase fφ with such a configuration, for example, by setting fos to 17.5 MHz, fφ can be set to 10 MHz. However, as a practical problem, a signal 17.5 MHz away from 2600 MHz is removed. The filter is very difficult to manufacture. When a crystal filter or the like is used as the narrow band filter, there is a problem that the PLL loop characteristic is affected and the PLL itself does not converge.
JP-A-10-51506

  As described above, when the oscillation frequency of the voltage controlled oscillator is divided as it is and the phase comparison frequency fφ (frequency step size) formed based on the reference oscillator is reduced, the multiplication number No is increased and the phase noise is increased. There is a problem of becoming. On the other hand, if the output of the voltage controlled oscillator is mixed with a signal having an offset frequency that is much smaller than the oscillation frequency, and the frequency offset type is divided into a differential frequency, the noise problem is solved. There is a problem that it is very difficult to form a filter that is close to the frequency of 1.

  The present invention has been made to solve such a problem, and an object of the present invention is to provide a frequency synthesizer having a configuration in which a problem of a filter does not occur while solving a problem of phase noise by using a frequency offset type. .

  A frequency synthesizer according to the present invention includes a voltage controlled oscillator, an image rejection mixer that is connected to the voltage controlled oscillator and suppresses an image component by offsetting an oscillation frequency of the voltage controlled oscillator, and the image rejection mixer. A frequency divider for dividing the frequency of the output signal, a reference signal generator for generating a reference frequency, an output signal of the divider and a signal having a phase comparison frequency generated from the reference signal generator A phase comparator that detects a phase difference and supplies a control voltage to the voltage-controlled oscillator based on the phase difference. Here, the phrase “generated from the reference signal generator” means that the signal itself output from the reference signal generator includes the output frequency changed by a frequency divider or the like.

  The image rejection mixer includes, for example, a 90-degree distributor that distributes the output of the voltage-controlled oscillator into signals having a phase difference of 90 degrees, and first and second connected to the output side of the 90-degree distributor, respectively. And an offset frequency signal whose frequency can be varied by a programmable frequency divider and a mixed output of each of the first and second mixers. It consists of a synthesizer that synthesizes and outputs.

  With this configuration, the oscillation frequency of the voltage controlled oscillator is offset, and the offset of the oscillation frequency is formed by the image rejection mixer. Therefore, the phase comparison frequency fφ can be increased, and the filter Without being affected by harmonics, the multiplication factor fo / fφ can be reduced. As a result, phase noise characteristics can be reduced. That is, since the offset frequency input to the image rejection mixer can be set to a frequency that is easily multiplied by an integer even with respect to the large phase comparison frequency fφ, the phase comparison frequency fφ can be increased. In addition, since an image rejection mixer is used, signals whose phases are shifted by 90 degrees are synthesized, and spurious can be canceled out. As a result, the spurious problem can be solved without inserting a filter, the spurious problem can be solved, and the phase comparison frequency fφ can be increased, so that the multiplication factor can be reduced. Thus, phase noise characteristics can also be improved.

  Next, the frequency synthesizer of the present invention will be described with reference to the drawings. The frequency synthesizer according to the present invention suppresses the image component by offsetting the oscillation frequency of the voltage controlled oscillator 1 to the voltage controlled oscillator (VCO) 1 as shown in the circuit diagram of one embodiment in FIG. An image rejection mixer 10 is connected, and the frequency of the output signal of the image rejection mixer 10 is divided by a frequency divider (modulus prescaler 3, programmable frequency divider 4) and supplied to the phase comparator 8. . On the other hand, a reference signal generator 6 for generating a reference frequency fr is provided, and a reference signal having a phase comparison frequency fφ generated from the reference signal generator 6 is supplied to the phase comparator 8. Then, the phase comparator 8 detects a phase difference between the signal supplied from the programmable frequency divider 4 and the phase comparison frequency fφ of the reference signal, and a control voltage is determined based on the phase difference. 1 is provided. Between the phase comparator 8 and the voltage controlled oscillator 1, there is a loop filter (L / F) 9 for removing harmonic components generated by the phase comparator 8 and determining the response characteristics and steady-state characteristics of the system. It is connected.

  As shown in FIG. 1, in the image rejection mixer 10, a part of the output of the voltage-controlled oscillator 1 is input to a 90-degree hybrid (90 ° HYB) 11 that branches with a phase difference of 90 degrees. The first and second mixers 12 and 13 respectively connected to the branch ports of the hybrid 11 are mixed with the signals I and Q having the offset frequency fos to offset the frequency fo of the voltage controlled oscillator 1 and fo ± fos As a result, both outputs are combined by the combiner 14 to output an offset signal from which spurious signals are removed. In the example shown in FIG. 1, the signal of the offset frequency fos passes through a programmable frequency divider 15 in which a part of the output of the reference signal generator 6 is branched and the frequency division ratio 1 / n can be changed by a computer. Applied. As a result, the offset frequency can be freely changed by changing the frequency division ratio 1 / n by a computer.

  When the signal of 7.5 MHz is added as the signal of the offset frequency fos of the image rejection mixer 10 and the frequency of the input signal Fin to the 90-degree hybrid 11 is 2607.5 MHz, the output signal Fout of the frequency 2600 MHz is obtained. The result of examining the spurious characteristics is shown in FIG. As can be seen from FIG. 2, Fout of 20 dBc or more is obtained with respect to Fin. Many digital synthesizers have a prescaler that digitally divides the frequency, and are digital circuit configurations. Therefore, a spurious signal having a suppression ratio of 20 dB that has passed through the image rejection mixer is ignored in the digital circuit configuration. be able to. Further, as described above, since this circuit can be configured as a digital programmable circuit, the offset frequency can be freely adjusted. As a result, a PLL circuit can be configured without providing a filter.

  The other parts of the PLL are the same as the conventional configuration. That is, a part of the output of the voltage controlled oscillator 1 is branched and input to the image rejection mixer 10 described above, and the output is input to the modulus prescaler 3 and divided by 1 / M. The frequency division ratio N is inputted to the programmable frequency divider 4 which can be freely changed by a computer and is divided into 1 / N. In the modulus prescaler 3 and the programmable frequency divider 4, the frequency division ratio can be finely adjusted by an A counter 5 which can also control the number of additions by a computer. As a result, the frequency fo oscillated by the voltage controlled oscillator 1 becomes (fo−fos) / (M · N + A) and is supplied to the phase comparator 8.

  On the other hand, the output of the reference signal generator 6 that oscillates at the reference frequency fr is frequency-divided by 1 / Nr by the frequency divider 7 and input to the phase comparator 8, and (fo−fos) / ( M · N + A) and fr / Nr signals are compared in phase. If the phases do not completely match, the difference is set as a voltage and supplied to the voltage controlled oscillator 1. Yes. A loop filter (L / F) 9 is connected behind the phase comparator 8.

For example, a specific example in which fo is output in steps of 2607.5 to 2657.5 MHz in 10 MHz steps will be described. When the oscillation frequency fr of the reference signal generator 6 is 70 MHz and the frequency division ratio n of the programmable frequency divider 15 is 4, the offset frequency fos is 17.5 MHz, and the difference between the first and second mixers 12 and 13 is calculated. By extracting the output, the output of the image rejection mixer 17 has a frequency f1 of 2590 to 2640 MHz. Further, when the output frequency fo is 2617.5 MHz, the frequency division ratio M of the modulus prescaler 3 is 16, the frequency division ratio N of the programmable frequency divider 4 is 16, and the number A of the A counter 5 is 4, the modulus prescaler 3 The frequency of the signal that has passed through the programmable frequency divider 4 is
(2617.5-17.5) / (16 × 16 + 4) = 10
Thus, by setting the frequency division ratio Nr of the frequency divider 7 to 7, the phase comparator 8 compares the phase comparison frequency (frequency step size) fφ with 10 MHz of the output of the programmable frequency divider 4. In addition, the oscillation frequency of the voltage-controlled oscillator 1 can be adjusted to a desired 2617.5 MHz.

  Further, the phase noise characteristic at this time is 20.log260 = 48.3 (dBc / Hz) because the multiplication number (M · N + A) is 260 = 2600/10, and the phase noise of 10 MHz is − Since it is 142 dBc / Hz, the in-band noise is −142 + 48.3 = −93.7 (dBc / Hz). On the other hand, the measurement result of the noise characteristic is −93 dBc / Hz as shown in FIG. 3, and it can be seen that the measurement result of the noise characteristic is not affected by the 17.5 MHz noise added by the image rejection mixer. Conversely, it can be improved by about 13 dBc / Hz compared to the phase noise characteristic shown in FIG.

  According to the present invention, the offset frequency can be formed by using an image rejection mixer, and the offset frequency fos can be varied by using the programmable frequency divider 15. Therefore, the offset frequency is set to a very low frequency, several It can be set to kHz to several tens of MHz, and can be changed to a minute step size. As a result, it is not necessary to reduce the phase comparison frequency fφ, the multiplication number No (= fo / fφ) can be reduced, and the phase noise characteristics can be improved. In addition, since the image rejection mixer is used, spurious can be effectively removed, and it is not necessary to use a filter for removing spurious, and a frequency synthesizer that is extremely free from the effects of phase noise and spurious can be obtained.

1 is a circuit diagram illustrating an embodiment of a frequency synthesizer according to the present invention. It is explanatory drawing which shows the noise characteristic of the image rejection mixer part of FIG. It is a figure which shows the phase noise characteristic of the frequency synthesizer shown by FIG. It is a figure which shows the structural example of the conventional frequency synthesizer. It is a figure which shows the other structural example of the conventional frequency synthesizer. It is a figure which shows the phase noise characteristic of the frequency synthesizer shown by FIG.

Explanation of symbols

1 Voltage Control Oscillator 3 Modulus Prescaler 4 Programmable Divider 5 A Counter 6 Reference Signal Generator 7 Divider 8 Phase Comparator 9 Loop Filter 10 Image Rejection Mixer 12 First Mixer 13 Second Mixer 15 Programmable Divider

Claims (2)

  A voltage controlled oscillator, an image rejection mixer connected to the voltage controlled oscillator and offsetting an oscillation frequency of the voltage controlled oscillator to suppress an image component; and a frequency of an output signal of the image rejection mixer. Detecting a phase difference between an output signal of the divider and a signal having a phase comparison frequency generated from the reference signal generator; A PLL type frequency synthesizer having a phase comparator for supplying a control voltage to the voltage controlled oscillator based on a phase difference.   The image rejection mixer distributes the output of the voltage-controlled oscillator to signals having a phase difference of 90 degrees, and first and second connected to the output side of the 90-degree distributor, respectively. An offset frequency signal that is supplied to each of the mixer and each of the first and second mixers and whose frequency can be varied by a programmable frequency divider, and each mixed output of the first and second mixers are combined. The frequency synthesizer according to claim 1, further comprising:

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